JP3002561B2 - Modulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a modulator for linearly modulating a digital data signal, and more particularly, to a modulator in which a multiplier for multiplying a data signal and a carrier signal is digitized using a simple logic circuit.

[0002]

2. Description of the Related Art For example, FDMA (Frequency Division Multiple Access) communication has been adopted as a technique for transmitting a large amount of digital information over a small number of lines and at high speed as a mobile radio communication system between terrestrial networks. I have.

If the modulation method of the FDMA signal is, for example, only frequency modulation, the amplitude is constant as shown in FIG. The frequency characteristic has a mountain-shaped waveform as shown in FIG. Therefore, the occupied frequency band W _F of one signal becomes wider. As a result, the entire frequency domain cannot be used effectively. In order to solve such inconveniences, adoption of a linear modulation method as a modulation method of an FDMA signal has been proposed.

[0004] A linearly modulated signal by this linear modulation method is
It has the waveform shown in FIG. 3C and the frequency characteristics shown in FIG. That is, the amplitude is changed according to the information in order to reduce the included high frequency components. As a result, the frequency characteristic has a substantially square waveform as shown in the figure. Therefore, it is possible to effectively use the entire frequency range because the frequency band W _F occupied by the one signal can be set narrower than in FIG. 3 (b). Then, this linear modulation signal S
(t) is, as is well known, expressed by equation (1) where A (t) is a complex envelope and f _C is a carrier frequency. S (t) = Re [A (t) exp (j2πf C t)] ... (1) where the complex envelope A (t) is the envelope information of the linear modulation signal shown in FIG. 3 (c) (amplitude information) And is obtained as follows. That is, a transmission symbol sequence {Ak} corresponding to a digital data signal to be transmitted can be expressed as a set as in the following equation. {Ak} = {... A- ₂ , A- ₁ , 0, A _{+ 1} , A _{+ 2} ...} Each element Ak is a complex number and matches one element of the following finite set of M elements. Note that k is one element of all integers including positive, negative, and zero. Ak = S ₁ , S ₂ , S ₃ ,..., S _M

[0005] Here, M is an integer of 2 or more.
If shown by phase modulation, it is a value when the circumference is equally divided into M as shown in FIG. Therefore, the transmission symbol sequence {Ak}
Can be represented by a complex number as shown in equation (2). {Ak} = {exp [j2πm / M] exp [jφ]} (2) where m is an integer from 0 to (M−1). Then, assuming that the impulse response of the filter is h (t), the complex envelope A (t) at the time t can be generally expressed by Expression (3).

[0006]

(Equation 1) Here, T _S is a symbol period indicating the time during which one symbol (data value) in the digital data signal continues. Therefore, the power spectrum density (PSD) Sa (f) of the complex envelope A (t) is

[0007]

(Equation 2)

[0008] In FDMA communication method described above, as the signal does not leak into the frequency domain (adjacent channel) of the adjacent signals, as shown in FIG. 3 (d), the frequency band other than the frequency band W _F (| f | ≧ W _F ), the power spectrum density Sa (f) needs to be zero.

[0009] However, where the frequency band W _F by using a roll-off rate α, and the symbol period T _S on the cut-off frequency characteristics of the roll-off filter shown in FIG. 6 is defined as follows. W _F = (1 + α) / T _S

However, in reality, the above condition cannot be completely satisfied, and as shown in FIG. 5, the signal enters the frequency domain of an adjacent channel indicated by a dotted line. For example, indicating the carrier frequency f _c1, f _c2 and the frequency difference f _d between each other as a variable leakage E indicating the leak degree to adjacent channels (f _d) is within the frequency band W _F in the frequency characteristic of FIG. 5 It is indicated by the area ratio between the area and the area in the frequency domain of the adjacent channel indicated by the oblique line. Further, in digital wireless communication, the leakage E (f _d ) can be displayed only by the transfer function H (f) of the filter.

[0011]

(Equation 3)

Therefore, the leakage E to the adjacent channel
(F _d ) is determined only by the transfer function H (f) of the filter, that is, the roll-off filter. And this transfer function H
(f) is expressed by equation (6) using the impulse response h (t) described above.

[0013]

(Equation 4) Then, the leakage E in the actual digital wireless communication
(F _d ) satisfies 0 <E (f _d ) ≦ E (W _F ) under the condition of f _d > W _F. In the conventional digital radio communication, leakage E (W _F) is about _{^{10 -6 (E (W F)}} ≦
10 ^-6 ). A modulator for modulating such a transmission symbol string signal into a linear modulation signal is configured as shown in FIG. 7, for example.

Symbol period T _C input to input terminal 1
Is sampled by the input processing circuit 2 at the sampling period T _S (= 1 / f _B ) and is read inside. And the complex envelope A (t)
It is output as the real part A _I sample value A _I (mT _B) and the imaginary part A _Q sample value A _Q (mT _B). Input processing circuit 2
Sample values A _I (mT _B ), A _Q (m
T _B ) is converted into analog signals a ₁ and a ₂ by the DA converters 3a and 3b, respectively. Then, the signals are sent to the multipliers 7a and 7b via the low-pass filters 4a and 4b.
Then, for example, the following equation may be used. a ₁ = sin 2πf _B t a ₂ = cos 2πf _B t

The carrier signal (= sin 2πf _C ) output from the oscillating circuit 5 is shifted in phase by 90 ° with respect to the other by the 90 ° phase shifter 6, so that each of the multipliers 7a,
Multiplicand signal cos 2 [pi] f _C t to 7b, is input as sin 2πf _C t. Each of the multipliers 7a and 7b is formed of, for example, a double balanced mixer. Each multiplier 7a, multiplied signals of each signal from _{7b (sin 2πf B t · cos} 2πf
_C t) and (cos 2πf _B t · sin 2πf _C t) are sent to the next signal combiner 8. The signal synthesizing circuit 8 synthesizes the input signals and generates a synthesized signal [sin 2π (f _C + f _B )].
t] and output from the output terminal 9. Therefore, this output signal S (t) is calculated using the complex envelope A (t).
It can be shown by equation (7). S (t) = Re {A (t)} cos 2πf C t-Im {A (t)} cos 2πf C t = Re [{A (t)} exp (j2πf C t)] ... (7)

Therefore, this modulator modulates a transmission symbol sequence signal {Ak} into a linear modulation signal S (t). Where R
e [] and Im [] indicate the real part and the imaginary part of the data in [] respectively.

In the modulation device shown in FIG. 7, a circuit indicated by a chain line from each of the low-pass filters 4a and 4b to the signal combiner 8 is a quadrature modulation circuit 10, and an SSB
It is called a mixer.

[0018]

However, the conventional modulator shown in FIG. 7 still has the following problem.

That is, the frequency characteristic of the power spectrum density (PSD) of the output signal of the SSB mixer is as shown in FIG. The power spectrum P _1A is the required upper band (USB), the power spectrum P ₀ is the leakage spectrum at the carrier frequency f _C , and the power spectrum P _1B is the lower band (LS) called the image wave.
B). The power spectra P _2A and P _2B are the above-mentioned second-order spurious components. Similarly, power spectra P _3A and P _3B are third-order spurious components.

Here, the power spectrum P ₀ is generated by the DC offset voltage of each of the multipliers 7a and 7b. Then, assuming that the power spectrum P _1A of the upper side band (OSB) is a reference level (0 dB), the level is −40 to −40.
This is a value of 50 dB. Further, the power spectrum P _1B is generated due to the mismatch of the conversion loss of each of the multipliers 7a and 7b,
It has a level value of -30 to -40 dB. Since the power spectrum P ₀ as described above, P _1B enters the frequency band W _F of the linear modulation signal, there is no particular big problem even somewhat large value.

However, since the frequencies of the power spectra P _2A , P _2B , P _3A , and P _3B of the second and third order spurious components leak to the frequency band of the adjacent channel, it is necessary to suppress them. Then, each power spectrum P
_2A , P _2B , P _3A and P _3B are generated due to the nonlinearity existing in the multipliers 7a and 7b described above. In a modulator using the above-described ordinary double balanced mixer, the level values of these harmful power spectra P _2A , P _2B , P _3A , and P _3B are about −40 to −50 dB.

As described above, the multiplication process of the complex envelope A (t) and the carrier signal exp [j2πf _C t] is performed by using analog multipliers 7a and 7b such as a double balanced mixer. Therefore, the power leaking to the adjacent channel increases as shown in FIG. 5 due to the non-linearity of the double balanced mixer, mismatch of characteristic values, and the like. Accordingly, there is a problem that the communication in the adjacent channel is adversely affected and the communication is adversely affected by the adjacent channel.

The analog quadrature conversion circuit 10 shown in FIG. 7 incorporates two low-pass filters 4a and 4b and an LC circuit network constituting the 90 ° phase shifter 6. Therefore, these circuit elements cannot be easily integrated into an IC. As a result, it has been difficult to form the entire modulation device small and lightweight.

Further, since a local signal of about 10 dBm for driving the LC network and each double balanced mixer is required, a driving power source having a certain capacity or more is required. In particular, since the device in which this modulation device is incorporated is often a portable mobile radio device driven by a battery, for example, it is necessary to minimize power consumption.

The present invention has been made in view of such circumstances, and by performing a complex multiplication of a complex envelope and a carrier signal by using a simple logic circuit, it is possible to use an analog circuit element. It is an object of the present invention to provide a modulation device capable of suppressing leakage power to adjacent channels as much as possible, easily realizing an integrated circuit, making the entire device compact and lightweight, and greatly reducing power consumption. .

[0026]

In order to solve the above-mentioned problems, in the modulation apparatus of the present invention , the first input of 3 bits is performed.
Transmission indicating the digital information to be transmitted input from the input terminal
Data of the symbol sequence and the 3-bit second input terminal
And the data input from the
Output the added data from the 3-bit output terminal.
Output from the adder and the output terminal of the 3-bit adder
After holding the added data obtained for one symbol period, the second
Flip-flop applied to input terminal and 3-bit addition
Of upper 2 bits output data at the output terminal
A first exclusive OR gate for calculating a logical OR,
Output data of the lower 2 bits at the output terminal of the
Exclusive OR gate for calculating exclusive OR of data
And the output data of the first exclusive OR gate is inverted.
Having an inverter (12e) and having an output terminal of a 3-bit adder
1-bit output data and first exclusive logic in
Realizes 2-bit data synthesized with the output data of the sum gate.
Output as a number, and output data of the second exclusive OR gate.
2-bit data combining the data and the output data of the inverter
A separating circuit that outputs data as an imaginary part, and a first part that sequentially takes in the real parts separated by the separating circuit in a symbol cycle and outputs a plurality of continuous real parts stored in each register as an upper address. Shift register and the first
A first memory for storing a sample value of a waveform uniquely determined by an address value and an impulse response of a filter at an address obtained by combining an upper address output from the shift register and a lower address that changes in a symbol cycle;

A second shift register which takes in the imaginary parts separated by the separation circuit in order at a symbol cycle and outputs a plurality of continuous imaginary parts stored in each register as an upper address; and a second shift register. A second memory for storing a sample value of a waveform uniquely determined by the corresponding address value and an impulse response of a filter at an address obtained by combining an upper address output from the controller and a lower address that changes in a symbol cycle;

A first logic circuit for inverting the polarity of each sample value output from the first memory at a period twice as long as the sampling period (T _C ) of the output linear modulation signal, and an output from the second memory; a second logic circuit for polarity inverting each sample value which is twice the period of the sampling period, first, alternately each sample value outputted from the second logic circuit in a sampling period (T _C) And a D / A converter for converting each sampled value output at a sampling period from the selection circuit into an analog linear modulation signal,

Each memory is provided with a counter which outputs a lower address that changes at a symbol cycle and outputs a sampling cycle signal and a double sampling cycle signal to each of the selection circuits and each logic circuit.

[0030]

According to the modulator configured as described above, the input transmission symbol sequence {Ak} is converted into a 3-bit adder and a signal.
A pair of exclusive OR gate with a flip-flop, inverter and
And a real part Re {Ak} and an imaginary part Im {Ak}.

Each register of the first shift register stores the value of the real part of the transmission symbol sequence for each successive symbol period. That is, the upper address output from the first shift register is a plurality of continuous values in the real part. The value in the current symbol cycle is set in the lowest order of the upper addresses, and the value in the previous symbol cycle is set in the next address. Further, a value in the symbol cycle of the previous two times is set to the next address.
Thus, the output upper address includes information on the current symbol cycle and information on the past symbol cycle.

The address of the first memory is a combined address of the upper address and the lower address output from the counter every symbol period. The lower address is applied with a value that is incremented every symbol period and returns to 0 when the upper limit is reached.

Then, at each address of the first memory,
Each sample value of a waveform indicating a real part which is uniquely determined by the corresponding address value and the impulse response h (t) of the filter is stored.

That is, the input transmission symbol sequence ｛A
k｝ has a different value for each symbol period corresponding to the transmission digital data, and the address of the first memory contains the value of the current symbol period of the transmission symbol sequence and A value determined by the value is applied. The corresponding address stores each sample value of the waveform uniquely determined by the corresponding address value and the impulse response of the filter. Therefore, the real part of the complex envelope A (t) is output from the first memory. On the other hand, finds the linear modulation signal S (t) as described above, it is necessary to perform the calculation of _{A (t) exp (2πf C} t). In order to realize this operation, A (t) exp (jπm / 2) replaced with t = m / (4f _C ) is used. As is well known, exp (jπm / 2) can be expanded as shown below. exp (jπm / 2) = cos (πm / 2) + jsin (πm / 2) When m is a positive integer, exp (jπm / 2) becomes exp (jπm / 2) = 1, j, −1, −j

There are four types of values. Therefore, the first
Complex envelope A (t) output from the second memory
Of the sample values of 1, j, -1, -j
It is only necessary to multiply each value of the type. The multiplication process of -1 can be realized by inverting the polarity of the sample value of the real part of the complex envelope A (t) by the first and second logic circuits. Further, the multiplication process of j is performed by using a sample value from the first memory corresponding to the real part and a second value corresponding to the imaginary part.
By alternately selecting the sample values from the memory of FIG. Therefore, [A (t) exp (j) is obtained by the first and second logic circuits and one selection circuit.
πm / 2)].

When each digital sample value output from the selection circuit at each sampling period is converted into an analog waveform signal by a DA (digital / analog) converter,
The linear modulation signal S (t) shown in the equation (1) is obtained. S (t) = Re [A (t) exp (j2πf C t)] ... (1)

Thus, the complex envelopes A (t) and e
Since the multiplication with xp (j2πf _C t) can be realized by a simple digital circuit, unnecessary spurious components in the power spectrum due to non-linearity generated when an analog circuit such as a double balanced mixer is used are removed. , Leakage to adjacent channels is greatly suppressed.

In this case, the power spectrum density Sa (f) of the complex envelope A (t) is given by the above equation (4).
A roll-off roll-off rate of the filter to be connected after the DA converter alpha, | f | In ≧ [(1 + α) / 2T S] = W F / 2 condition, the Sa (f) = 0. Here, two types of modulated signals S (t) and S (t) 'are considered. Assuming that the sampling period T _C of the output linear modulation signal is T _C = 1 / (4f _C ) f _C : carrier frequency, each of the linear modulation signals S (t) and S ′ (t) is expressed by the following equation (8). Can be written as follows. _{S (nT C) = Re [} A (nT C) exp (jπn / 2)] S'(nT C) = Re [A (LT C) exp (jπn / 2)] ... (8) K = T B / T _C is a multiple of four. K = 4, 8, 12, 16, 20,..., And L is a value satisfying the following equation. n = KL + m 'where m' is an integer from 0 to K-1. m ′ = 0, 1, 2, 3,..., (K−1)

The sampling period T _{B of the} complex envelope A (t)
(= 1 / f _B ) is the frequency band W _F [= (1 + α) /
T _S ], the linear modulation signals S (t) and S ′ (t) having passed through the band-pass filter having the pass bandwidth B have the same waveform except for the delay time, according to the sampling theorem. Become. However, the pass bandwidth B of the filter needs to satisfy the following equation. W _F <B <1 / T _B

Therefore, assuming that frequency components other than the required band are cut off by a band-pass filter connected after the DA converter, one linear modulation signal S (nT _C ) in the equation (8) is converted from the DA converter. Instead of the output, the other linear modulation signal S ′ (nT _C ) may be output from the DA converter. However, the oversampling rate P (= T _S / T
_C ) needs to be set to 2 or more.

[0041]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of the modulation device of the embodiment. For the sake of simplicity, this embodiment shows a modulation device that performs π / 4 shift quadrature phase modulation (QPSK) in which the phase moves by 45 °.

For example, a 2-bit transmission symbol sequence {Ak} indicating digital information to be transmitted is input to each input terminal 11a,
The signal is input to the separation circuit 12 via 11b. Separation circuit 1
2 is an adder 12a, D-type flip-flop 12b, E
It is composed of XOR (exclusive OR) gates 12c and 12d and an inverter 12e, and separates an input transmission symbol sequence {Ak} into a real part Re {Ak} and an imaginary part Im {Ak}.

The counter 13 is constituted by, for example, a 74LS163A synchronous counter, and the sampling frequency (4f _C ) of the linear modulation signal output from a clock oscillator (not shown).
Are counted and output as 4-bit data. When the output value exceeds [1111], the value returns to [0000].

In this embodiment, oversampling is represented by the ratio of the symbol period T _S (= 1 / f _S ) to the sampling period T _B (= 1 / f _B ) of the complex envelope A (t). Rate P and sampling period T _B (= 1 / f _B )
A sampling period T _C of the linear modulation signal S (t) (= 1/ 4
The ratio K to f _c ) is set to 4 for simplicity. P = T _S / T _B = 4 K = T _B / T _C = 4 Therefore, a clock signal having the symbol period T _S is input from the counter 13.

A 2-bit transmission symbol sequence {Ak} whose value changes in the symbol period T _S input to the separation circuit 12
Is a 3-bit first input terminal B0, B0 of a 3-bit adder 12a of, for example, 74LS283 for differential encoding.
1 and B2 are input to the upper input terminals B1 and B2. The 3-bit adder 12a has input terminals B0, B1, B
2 3-bit data is output from the D-type flip-flop 12b every symbol period, and a 3-bit second input terminal
3-bit data by adding the input to the outputs from the 3-bit output of <br/> force terminals S0, S1, S2 as 3-bit data.

The output 3-bit data is supplied to the 3-bit adder 12a via the D-type flip-flop 12b .
The value is again input to the second input terminal as the value to be added. Lower rank
1 bit of the output terminal S0 and the upper output terminals S1 and S1
2 is output to the 2-bit input terminal of the first shift register 14a by a total of 2 bits including 1 bit obtained by performing an exclusive OR operation on each output data of the first shift register 14a by the first EXOR (exclusive OR) gate 12c. As the sample value of the real part Re {Ak} of the symbol sequence {Ak}, the first shift register 14a
Is input to

On the other hand, the lower order in the 3-bit adder 12a
Output terminals S0, S1 second EXOR each output data
A total of two bits, one bit obtained by performing an exclusive OR operation by the gate 12d and one bit obtained by inverting the first EXOR gate 12e by the inverter 12e, are transmitted to the input terminal of the two-bit configuration of the second shift register 14b. As a sample value of the imaginary part Im {Ak} of the symbol sequence {Ak} ,
The data is input to the shift register 14b .

The first shift register 14a is, for example, 74LS
This is a 2-bit × 8-word shift register formed by H.164, and contains eight (Ns = 8) 2-bit word registers therein. The sampled value of the real part Re {Ak} applied to the input terminal of the 2-bit configuration is
Each time a clock signal having a symbol period T _S is input from the register, the data is fetched into each register, and the 2-bit data already fetched into each register is shifted to the next register.

Therefore, the first shift register 1
4a, there are eight real parts R each of 2 bits.
The following sample values of e {Ak} are stored in the registers in the order of input. Re {Ak '}, Re {Ak'-1}
, Re {Ak'-2},..., Re {Ak'-Ns + 1}, that is, the sample values in each of the up to the eighth symbol periods from the latest symbol period are stored.

Then, 8 of the first shift register 14a
Each sample value of 2 bits stored in each of the registers is applied as an upper address to the upper 16 addresses of a total of 18 address terminals of the first memory 15a. A counter 1 is provided at each address terminal of the lower 2 bits of the first memory 15a.
From 3 the 2-bit address value L in synchronization with the symbol period
'(= 0, 1, 2, 3, 4) is applied. Therefore, an address AD composed of a total of 18 bits of eight sample values (upper 16 bits) and one count value (lower 2 bits) is applied to the 18 address terminals of the first memory 15a. AD = [Re {Ak '}, Re {Ak'-1}, ..., Re {Ak'-Ns + 1}, L']

Here, L = k′P + L ′, P is an oversampling rate (= T _S / T _B ), and L ′ indicates a sample value number within one symbol period T _S , and takes the following value. obtain. L '= 0, 1, 2, 3,..., P-1

The first memory 14a stores, for example, RO
M and the like, and a sample value of a waveform uniquely determined by an address value and an impulse response of a filter is stored at each address position designated by the 18 bits.

That is, the address AD applied to the address terminal of the first memory 15a can be expressed by the following equation (9).
(LT _B ) is expressed by equation (10).

[0055]

(Equation 5) However, h (t) holds when t <0 and t ≧ Ns T _S. Ns is the first shift register 14a described above.
Is the number of registers. | F | when a ≧ (1 + α) / 2T S (= W F / 2) ... (11), by setting the register number Ns of the first shift register 14a to about 8, to the adjacent channel leakage E
(F) can be reduced to 10 _-6 or less. Therefore, the sample value D of the waveform finally written to the address AD position is an integer value represented by, for example, 12 bits represented by the equation (12).

[0056]

(Equation 6) Here, round [] is a value obtained by rounding the data in []. Ac is a constant. Therefore, a 12-bit sample value D [= Re {A (L) corresponding to the real part for each symbol period T _S from the first memory 15a.
T _B}] is output.

The constant Ac is the D at the last stage of the modulator.
This is a constant for preventing an excessively large sample value from being input to the A-converter 20 (overflow), and is given by Expression (13).

[0058]

(Equation 7) Where dm = S ₁ , S ₂ ,... S _M

MAX││ is d ₀ , d ₁ . ... d
_{7 for} all combinations 4 ⁸ And L ′ = 0,
The combination that maximizes the absolute value || Thus, finally the absolute value from among the combinations of 2 ¹⁸ kinds | | is looking for a combination of maximum constant Ac
Is calculated. When the constant Ac is set in this way, it is possible to prevent an overflow phenomenon from occurring in the DA converter 20. That is, the sample value always satisfies equation (14).

[0060]

(Equation 8)

Therefore, the data is output from the first memory 15a. Each sample value D of the waveform is from 0 to (2 ¹² −
Address AD applied from the name of each integer value up to 1)
It becomes one value specified by. {D} = 0,1,2,3, ..., 2 ¹² -1

On the other hand, the second memory 15b has the same configuration as the first memory 15a. Then, the second memory 15b
The 18-bit imaginary part address AD is applied to the 18 address terminals. AD = [Im {Ak '}, Im {Ak'-1}, ..., Im {Ak'-Ns + 1}, L']

At the corresponding address AD position, a sample value represented by the equation (12) is stored as in the first memory 15a. Therefore, the second memory 15
Each sample value D [= Im {A (LT _B )}] of 12 bits corresponding to the imaginary part for each symbol period T _S is output from _b .

Each sample value Re {A (LT _B )}, Im {A (LT _B )} output from the first and second memories 15 a and 15 b.
Are input to D-type flip-flops 16a and 16b each having a 12-bit configuration. Each flip-flop 16
A clock signal of the second bit from the bottom of the counter 13 is applied to clock terminals a and 16b. That is, each memory every sampling period T _B of the complex envelope A (t) 1
Each sample value Re {A (L
T _B )} and Im {A (LT _B )} are latched until the next clock signal input. That is, each flip-flop 16
a and 16b are timings at which the sample value Re {A (LT _B )} of the real part and the sample value Im {A (LT _B )} of the imaginary part are input to the next EXOR (exclusive OR) gates 17a and 17b. Has the function of matching

Each of the lower two bits of the counter 13 is subjected to an exclusive OR operation by another EXOR gate 17c, and is converted into a one-bit control signal g (double sampling period signal) by each EXOR gate 17a. , 17b.

Each of the EXOR gates 17a and 17b incorporates 12 unit EXOR gates, respectively.
Each bit data of each 12-bit sample value output from each flip-flop 16a, 16b is applied to one input terminal of each unit EXOR gate. The control signal g is commonly input to the other input terminal of each unit EXOR gate. Then, each of the 12 units EX
The OR gate controls the corresponding bit data in the sample value and the control signal g.
And outputs the result to the next selection circuit 18.

As described above, the complex envelope A (t)
Since the sampling period T _B is four times the sampling period T _C of the linear modulation signal S output (t), the lower counter 13 2
The bits output four values m of [00], [10], [01], and [11] in the sampling cycle T _C of one linear envelope signal within the sampling cycle T _B of one complex envelope. I do. Therefore, for m = 0.1, 2, 3 the control signal g
Repeats [0], [1], [1], [0].

As a result, when m = 2 and m = 3, the sample value R output from each EXOR gate 17a, 17b
The signs of e {A (LT _B )} and Im {A (LT _B )} are inverted.
That is, each EXOR gate 17a, 17b. 17c the first to reverse the polarity opposite with twice the period (2T _C) of the sampling period T _C of each sample value _{Re {A (LT B)}} , Im {A (LT B)} linear modulation signal , And a second logic circuit.

The selection circuit 18 is formed of a multiplexer composed of, for example, three 74LS158s, and counts the input sample values Re {A (LT _B )} and Im {A (LT _B )} on the counter 1.
The data is alternately selected in synchronization with the 3 least significant bits and output to the next 12-bit D-type flip-flop 19. Since the clock signal of the least significant bit is inverted every sampling period T _C of the output linear modulation signal, four types of values m (=
0, 1, 2, 3), each sample value is selected alternately. As a result, sample values output from the selection circuit 18 for each value of m are as follows. Output the value of the first memory as it is for m = 0 [Re
{A (LT _B )}] Invert the value of the second memory for m = 1 and output [−I
m {A (LT _B )}] Invert the value of the first memory for m = 2 and output [−R
e {A (LT _B )}] For m = 3, output the value of the second memory as it is [Im
{A (LT _B )}] That is, [A (t) ex
p (2πf _C t)] has been digitally executed.

Each sample value output from the selection circuit 18 at each sampling cycle T _C of the linear modulation signal is latched once by a D-type flip-flop 19, and then converted by a DA converter 20 into an analog signal, that is, (1) ) Is converted to the final linearly modulated signal S (t) shown in the equation. In an actual transmission device, a band pass filter is connected after the DA converter 20.

According to the modulator configured as described above,
[A (t) exp (2πf
_C t)] each EXOR gate 17a calculates the, 17b, 1
This is realized by a digital circuit selection circuit 18 as well as a simple digital logic circuit composed of 7c. Since these digital circuits can be easily integrated into an IC, there is no error factor such as distortion that tends to occur in the analog circuit, and therefore, high-precision modulation is possible.

Therefore, the leakage E (f) to the adjacent channel due to the power spectrum of the spurious component generated due to the non-linearity generated when the conventional analog double parallel mixer is used can be greatly reduced. If the power spectrum P _1A of the upper band (USB) shown in FIG. 8 is set to a reference level (0 dB) in the device of the embodiment,
It could be reduced to 60 dB or less. As a result, the carrier frequency (the frequency difference f between the center frequencies f _{C) of the} signals shown in FIG.
The _d can be reduced up to the frequency band W _F of each signal, it is possible to effectively use the frequency used for communication.

For example, if the pass frequency bandwidth B of the band-pass filter connected to the DA converter 20 is set to 240 kHz and the roll-off rate α is set to 0.5, as in the embodiment, The conditions in the π / 4 shift four-phase modulation are as follows: symbol frequency f _S (= 1 / T _S ) = 160 kHz, carrier frequency f _C = 2.56 MHz, K = 4, sampling frequency f _B (=
When T _B ) = 640 kHz, linear modulation can be easily realized with a TTL circuit and a normal DA converter. Further, by setting as described above, also band-pass filter connected to the DA converter 20, it can be formed in a small size by using, for example, a LC filter Q _L = 10.about.5.

FIG. 2 shows the measured frequency characteristics of the linear modulation signal S (t) output from the modulator of the embodiment and FIG.
FIG. 7 is a diagram showing a comparison with a frequency characteristic of a linear modulation signal obtained by the conventional modulation device shown in FIG. As compared with the frequency characteristic of the conventional device shown by the dotted line B, the frequency characteristic of the device of the embodiment shown by the solid line A was confirmed to have the leakage to the adjacent channel suppressed by 10 dB or more.

Note that the chevron waveform in the portion Aa of the characteristics of the embodiment is a phenomenon that occurs because the number of resistors Ns is finite.
The noise is not caused by digital circuits such as the XOR gates 17a to 17c and the selection circuit 18.

Further, since all the circuits from the separation circuit 12 to the flip-flop 19 to which the transmission symbol string {Ak} is inputted can be constituted by digital TTL circuits, each circuit element can be formed into an IC and , All circuit elements can be incorporated into one large-scale IC element. Therefore, the entire device can be formed small and lightweight. Also,
Since a double parallel mixer or the like having large power consumption is not used unlike the conventional device, power consumption can be reduced.

As a result, by incorporating this modulator into a digital portable radio driven by a battery, the entire portable radio can be made compact and lightweight, and the battery life can be further extended.

[0078]

As described above, according to the modulation device of the present invention, the complex multiplication of the carrier signal and the complex envelope indicating the digital information to be transmitted is performed using a simple digital logic circuit. In addition, by storing each sample value of the output waveform in an address of the memory in advance and designating an address corresponding to each value of the input transmission symbol sequence,
Each sample value is taken out from the memory in a predetermined order, and a complex operation is executed by the logic circuit to obtain a linear modulation signal. Therefore, it is possible to minimize the leakage power to adjacent channels when an analog circuit element is used, to easily implement an IC, to reduce the size and weight of the entire device, and to significantly reduce the power consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a modulation device according to an embodiment of the present invention;

FIG. 2 is a power spectrum characteristic diagram of an output signal in the device of the embodiment;

FIG. 3 is a diagram showing a difference between a general frequency modulation method and a linear modulation method;

FIG. 4 is a diagram showing general phase modulation;

FIG. 5 is a diagram showing a relationship between a frequency band and leakage power in a linear modulation method;

FIG. 6 is a diagram showing cut-off frequency characteristics of a general roll-off filter;

FIG. 7 is a block diagram showing a schematic configuration of a conventional modulation device;

FIG. 8 is a power spectrum characteristic diagram in a conventional modulation device.

[Explanation of symbols]

12: separation circuit, 12a: adder, 13: counter, 1
4a: first shift register, 14b: second shift register, 15a: first memory, 15b: second memory, 17a: first EXOR gate, 17b: second E
XOR gate, 17c EXOR gate, 18 selection circuit, 20 DA converter.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-309841 (JP, A) JP-A-3-179954 (JP, A) JP-A-1-319798 (JP, A) JP-A-2-309 278932 (JP, A) 1990 IEICE Spring National Convention, Proceedings, Volume 2, p. 2-237, Article number B-237 (1990-3-15) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 27/00-27/38

Claims (1)

(57) [Claims] An input from a first input terminal of 3 bits.
Transmitted symbol sequence ({A
k}) and a 3-bit second input terminal.
Data in synchronization with the symbol period
3-bit addition to output data from 3-bit output terminal
(12a) and the output terminal of this 3-bit adder.
After holding the added data for one symbol period, the second
A flip-flop (12b) to be applied to the input terminal of
Output of upper 2 bits at output terminal of 3-bit adder
A first exclusive OR gate for calculating an exclusive OR of data
(12c) and the output terminal of the 3-bit adder.
A second one for calculating an exclusive OR of lower two bits of output data
Two exclusive OR gates (12d) and the first exclusive OR
An inverter (12e) that inverts the output data of the RIWA gate
And the lower 1 at the output terminal of the 3-bit adder.
Bit output data and the first exclusive OR gate.
The 2-bit data synthesized with the output data is converted to the real part (Re
{Ak}) and outputs the second exclusive-OR gate
And the output data of the inverter
Output 2-bit data as an imaginary part (Im {Ak})
A first shift register which takes in the real parts separated by the separation circuit in symbol cycle in order and outputs a plurality of continuous real parts stored in each register as an upper address.
(14a) and storing the corresponding address value and each sample value of the waveform uniquely determined by the impulse response of the filter in an address obtained by combining the upper address output from the first shift register and the lower address that changes in the symbol cycle. first memory and (15a), a plurality of imaginary successive stored in uptake each register sequentially imaginary part separated by the symbol period at the separating circuit
Shift register for outputting a portion as an upper address
(14b) and storing the corresponding address value and each sample value of the waveform uniquely determined by the impulse response of the filter in an address obtained by combining the upper address output from the second shift register and the lower address that changes in the symbol cycle. A second memory (15b) that performs a polarity inversion on a cycle twice as long as a sampling cycle (T _C ) of a linear modulation signal output from each of the sample values output from the first memory; A circuit (17a, 17c), and a second logic circuit (17b, 1c) for inverting the polarity of each sample value output from the second memory at a cycle twice as long as the sampling cycle.
7c) and a selection circuit (18) for alternately selecting each sample value output from the first and second logic circuits at the sampling period (T _C ).
And a D / A converter (20) for converting each sample value output from the selection circuit in the sampling period into an analog linear modulation signal.
A counter that outputs a lower address that changes in a symbol cycle to the first and second memories, and that outputs a sampling cycle signal and a double sampling cycle signal to the selection circuit and each of the logic circuits. 13).