KR0185437B1 - Multiplier having double edge clock structure and digital color space converter - Google Patents

Abstract

The present invention relates to a digital color space converter using a double edge clock structure. In particular, the variable data input is divided by n / 2, and the variable data is latched by n / 2 bits according to a double edge clock. A small area and high speed digital color space converter (DCSC) is obtained by reading the multiplication result of this variable data and coefficients from the partition and converting the Y, C _R , and C _b signals into R, G, and B signals. ).

Description

A multiplier having a double edge clock structure and a digital color space conversion device using the multiplier.

1 is an explanatory diagram for explaining a multiplication process by division.

2 is a ROM table showing a multiplication result stored in a partition ROM.

3 is a block diagram of a multiplier using a conventional split rom.

4 is a block diagram of an embodiment of a multiplier using a double edge clock according to the present invention.

5 is a circuit diagram of an embodiment of a dual port double edge register unit according to the present invention;

6 is a diagram illustrating a simulation waveform of a multiplier using a double edge clock according to the present invention of FIG. 4.

7 is a block diagram of an embodiment of a digital color space converter according to the present invention.

* Explanation of symbols for main parts of the drawings

1, 1 ': address decoder 2, 2': ROM core

3: adder 4: dual port double edge register

5: digit preservation adder 6 to 9: calculation unit

FF1, FF2: Flip-flop INT1, INT1: Inverter

MAND1 to MAND3: NAND gate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital color space converter (DCSC). In particular, a multiplier for dividing input variable data by n / 2 and multiplying according to a double edge clock and a digital color using the same A space converter (DCSC).

A digital color space converter (DCSC) is a device that converts Y, C _R , and C _b signals into R (red), G (green), and B (blue) signals.

Protocol of the CCIR (Center for Communication Interface Research) the 601 entries are at the luminance value (Iuminance) (hereinafter, Y "), color (chrominance) for the red color (hereinafter, C _r;), a chromaticity of the blue color In order to convert the signal (hereinafter referred to as C _b ) into R, G, and B signals, the following equation (1) is recommended.

R = Y + 1.370 × (C _r -128)

G = Y-0.698 × (C _r -128) -0.336 × (C _b -128)

B = Y + 1.730 × (C _b -128) (Eq. 1)

If you implement (1) using a direct multiplier, four multipliers are required, and m x n AND gates and m x (n-1) numbers are needed to perform m x n-bit multiplication with a general multiplier. You need a full-adder.

Therefore, assuming that the coefficients are 10 bits in Equation (1), since 100 AND gates and 90 full adders are required for one multiplier, there is a considerable difficulty in operating at high speed as well as a large area.

In addition, since the coefficient in Equation 1 has a unique value in each system, it can be implemented using ROM, but R, G, and B outputs are referred to as 8 bits, and 10-bit inputs as addresses. This method also takes up a fairly large area since a ROM of 2 ¹⁰ x 8 bits is required.

In the case of performing the multiplication operation of (fixed coefficient × n) bits as described above, the n bits are divided as shown in FIG. A multiplication operation in which each output value is added by performing a multiplication operation of the lower n / 2) bits may be used.

For example, if the fixed coefficient is 0.310, that is, 0010111101 in binary, and the variable is 19, 00010011, multiplying 00010011 into 0001, the upper 4 bits, and 0011, the lower 4 bits, the upper bit is multiplied. 0.370, lower bit 1.11, that is, the value of 00000110 and 00010010 can be obtained in binary, and if the upper bit is shifted 4 bits out of the result of the partial multiplication operation as above and added to the lower bit, 00000111, which is 0.370 × 19, You can get 7, rounded up to 6.63.

The partitioning scheme as described above may be implemented using a partition ROM having a ROM table as shown in FIG.

3 shows the structure of a conventional multiplier. The divided upper n / 2-bit variable data and the lower n / 2-bit variable data are received and decoded, respectively, and then output to the address (2 ^{n / 2} ) of the ROM core. ROMs for outputting a partial multiplication operation result value (8 bits) stored in response to an address decoder (1,1 ') and an address (2 ^{n / 2} ) output from the address decoder (1,1'). A core 2, 2 'and an adder 3 which adds the partial multiplication result (8 bits) output from the ROM cores 2, 2' and outputs the final multiplication result.

However, the multiplier as described above has a problem in that a circuit configuration is complicated and costs are increased by using two ROM cores storing the same data.

The present invention devised to solve the above problems of the prior art, the multiplier having a double edge clock structure, and using the same to convert the Y, C _R , C _b signals into R, G, B signals, The object is to provide a digital color space conversion device (DCSC) having a high speed.

In order to achieve the above object, the present invention receives an upper n / 2 bit and a lower n / 2 bit of n-bit variable data in response to a clock signal, multiplies a first coefficient by a first coefficient, and adds a luminance value to R. (Red) R conversion means for outputting a conversion output value; An operation value multiplied by a second coefficient after receiving the upper n / 2 bits and the lower n / 2 bits of the n-bit variable data in response to the clock signal, and the upper n / of the n-bit variable data in response to the clock signal; G conversion means for receiving an input of 2 bits and a lower n / 2 bit, multiplying by a third coefficient, and adding the luminance value and outputting a G (Green) conversion output value; And receiving an upper n / 2 bit and a lower n / 2 bit of the n-bit variable data in response to the clock signal, multiplying an operation value multiplied by a fourth coefficient, and adding the luminance value to output a B (Blue) converted output value. And B converting means.

The present invention also provides dual port double edge storage means for latching the lower n / 2 bits and the upper n / 2 bits of the variable data on the rising and falling edges of the clock signal, respectively; Decoding means for receiving, decoding and outputting the latched n / 2-bit data from the storage means; And a ROM core for outputting a multiplication result in response to the decoding result output from the decoding means.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 shows a configuration of a multiplier using a double edge clock according to the present invention, in which a divided variable is a dual port double edge register unit in which n / 2 bits are latched at the rising edge and the falling edge of the clock signal CLOCK ( 4), an address decoder 1 which sequentially receives n / 2 bits of data from the register unit 4, decodes it, and outputs the decoded address to the address 2 ^{n / 2} of the ROM core 2; A ROM core 2 for outputting a multiplication result stored in the ROM core ² in response to an address 2 ^{n / 2} output from the decoder 1, and the ROM core 2 in response to a clock. And an adder 8 for adding the partial multiplication result values sequentially outputted from and outputting the final multiplication result value. Here, the dual port double edge register section 4 includes n / 2 unit circuits for each n / 2 bits.

First, the dual port double register unit 4 receives and outputs variable data of the lower n / 2 bits on the rising edge of the clock, and the address decoder 1 and the ROM core 2 during the high level period of the clock. The multiplication result is output to the adder (3). That is, the ROM core decoded by the address decoder 1 after decoding the lower n / 2-bit variable data output through the dual port double register unit 4 and the result decoded by the address decoder 1 ( The multiplication result stored in 2) is output to the adder (8). In this case, the adder 8 includes a plurality of flip-flops, receives a result of the calculation operation output from the ROM core 2 in response to the rising edge of the clock, and adds the result of the multiplication operation with a meaningless value. do. However, the addition operation performed at this time is not a desired multiplication result and can be ignored.

Next, on the falling edge of the clock, the dual port double register section 4 outputs variable data of the upper n / 2 bits. The multiplication operation result is output to the adder 3 through the address decoder 1 and the ROM core 2 during the low level period of the clock. That is, the ROM core decoded the variable data of the upper n / 2 bits output through the dual port double register section 4 through the address decoder 1 and indexed by the result decoded through the address decoder 1. The multiplication result stored in (2) is output to the adder (8). The adder 8 receives the multiplication result output from the ROM core 2 in response to the falling edge of the clock and adds the previous multiplication result stored in the plurality of flip-flops to output the final result. The addition result at this time is the result of the multiplication operation on the actual n-bit variable data.

FIG. 5 is a unit circuit diagram of one bit of the dual port double edge register unit 4 according to the present invention, and is driven according to a clock signal CLOCK to convert an input signal IN-LOW to an output terminal Q. A pull-flop FF1 for outputting, a NAND gate NAND1 for NAND combining the output signal Q and the clock signal CLOCK of the flip-flop FF1, and the clock signal CLOCK Inverters INT1 and INT2, a flip-flop FF2 for outputting an input signal IN-HIGH to an output terminal Q according to the output of the inverter INT2, an output of the flip-flop FF2 and an inverter ( A NAND gate NAND2 for NAND combining the output of INT1 and a NAND gate NAND3 for NAND combining the outputs of the NAND gates NAND1 and NAND2. The signal IN-LOW is latched to the flip-flop FF1, and the input signal IN-HIGH is latched to the flip-flop FF2 at the falling edge of the clock. If the variable data is 8 bits, the dual port double edge register section 4 must be provided for each of 4 bits of n / 2 bits. Then, after outputting the variable data of the lower bit on the rising edge of the clock, the variable data of the lower bit is always maintained as the output of the dual port double edge register 4 during the high level of the clock, and on the falling edge of the clock, Variable data is output.

FIG. 6 is a waveform diagram of a multiplier using a double edge clock according to the present invention of FIG. 4, and simulates a multiplier using a double edge clock according to the present invention in the case where variable data is 8 bits 10010. One result is also. The dual port double edge register section 4 of the multiplier using the double edge clock for the simulation uses the circuit shown in FIG. 5, the address decoder 1 uses a general decoder circuit, and the adder 8 has a large number of flips. Adder circuits each having a flop at the input stage are used. The address decoder and ROM core circuit are well known in the art, and thus detailed descriptions thereof are omitted here.

In addition, IN_HIGH is the upper 4 bits of the variable data, IN_LOW is the lower 4 bits of the variable data, D_OUT is a signal output through the dual port double edge register section 4, mad is through the address decoder 1 The output signal, mout represents a signal output through the ROM core 2, and SUM represents a multiplication result of the variable data output through the adder.

First, the clock clocks with a predetermined period, and outputs the lower 4 bits, that is, 2 (ie 0010) through the dual port double edge register section 4 at the rising edge of the clock (10), and at the high level of the clock. The address decoder 1 receives and decodes the lower 4 bit value 2 and outputs a decoding result 4 (that is, 0000000000000100) (12). The ROM core 2, which stores the partial multiplication result, outputs the partial multiplication result 0B (i.e., 1011) indexed by the decoding result 4. [14] The adder 8 performs the multiplication operation. The result values 0B and 0 (all circuits perform an initialization operation before operation, so another input of the adder becomes a value of 0). (16) At this time, the adder 8 stores 8B values including eight flip-flops.

Next, at the falling edge of which the clock falls from the high level to the low level, the upper four bits, i.e., 1 (ie, 0001) are outputted through the dual port double edge register section 4 (18), and the address decoder at the low level of the clock. (1) receives the upper 4 bit value 1, decodes it, and outputs a decoding result 2 (that is, 0000000000000010) (20). The ROM core 2, which stores the partial multiplication result, outputs a partial multiplication result 5 (i.e., 101) indexed by the decoding result 2. (22) The adder 8 adds a multiplication result 5B for the lower 4 bits stored in the multiplication result 5 and the flip-flop of the adder 8, respectively, and outputs a multiplication output value 10000 of the 8-bit variable data 10010. (24)

FIG. 7 shows the configuration of a digital color space transformer using a multiplier using a double edge clock as shown in FIG. 4. It shows the overall structure of converting Y, C _R and C _b signals into R, G and B values. .

The R converter is a multiplier that receives the variables of the upper n / 2 bits and the lower n / 2 bits (C _r -128) at the rising edge and the falling edge, respectively, and outputs a multiplication operation value with the coefficient (1.370) stored in the ROM core. (6) and a carry save adder (5) which adds the output of the multiplier 6 and the Y-value to output the R-transformed output value.

The G converter receives multiply variables (C _r -128) of the upper n / 2 bits and the lower n / 2 bits at the rising edge and the falling edge, respectively, and outputs a multiplication operation value with the coefficient (0.698) stored in the ROM core. Multiplication operation with a multiplier (7) and a coefficient (0.336) stored in the ROM core by receiving variables of the upper n / 2 bits and the lower n / 2 bits (C _b -128) at the rising edge and the falling edge, respectively. A multiplier (8) for outputting the result, and a rounding storage adder (5) for adding the outputs of the multipliers (7, 8) and the Y value to output the G-transformed output value.

In addition, the B converter receives multiply variables (C _b -128) of the upper n / 2 bits and the lower n / 2 bits on the rising edge and the falling edge, respectively, and outputs a multiplication operation value with the coefficient (0.730) stored in the ROM core. A multiplier (9), and a carry-on storage adder (5) for adding the output of the multiplier (9) and the Y value to output a G-transformed output value.

Although the spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not for the purpose of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention operates by a double edge clock, and uses a ROM having a ROM table with a pre-calculated multiplication operation to configure a digital color space converter (DCSC). It can be easily built into. In addition, the digital color space converter (DCSC) of the present invention can be used in all image processing systems, HDTV (High Definition TeleVision), multimedia, and the like, and the effect of excellent performance can be obtained.

Claims (12)

R conversion means for receiving an upper n / 2 bit and a lower n / 2 bit of n-bit variable data in response to a clock signal and multiplying a first coefficient and a luminance value to output an R (Red) converted output value; ; An operation value multiplied by a second coefficient by receiving the upper n / 2 bits and the lower n / 2 bits of the n-bit variable data in response to the clock signal, and the upper n / of the n-bit variable data in response to the clock signal; G conversion means for receiving a two-bit and a lower n / 2 bit and multiplying an operation value multiplied by a third coefficient and the luminance value to output a G (Green) conversion output value; And receiving an upper n / 2 bit and a lower n / 2 bit of the n-bit variable data in response to the clock signal, multiplying an operation value by a fourth coefficient, and adding the luminance value to output a B (Blue) conversion output value. A digital color space conversion apparatus using a double edge clock structure including a B conversion means. 2. The operation of claim 1, wherein the R conversion means receives an upper n / 2 bit and a lower n / 2 bit of the n-bit variable data in response to the clock signal and outputs an operation value multiplied by the first coefficient. Way; And an adding means for adding the output from said calculating means and said luminance value and outputting it as said R conversion output value. 2. The apparatus of claim 1, wherein the G conversion means comprises: first arithmetic means for receiving an upper n / 2 bit of the n-bit variable data and outputting an arithmetic value multiplied by the second coefficient in response to the clock signal; Second arithmetic means for receiving an upper n / 2 bit and a lower n / 2 bit of the n-bit variable data in response to the clock signal and outputting an operation value multiplied by the third coefficient; And an adding means for adding the output from the first and second calculating means and the luminance value to output the G-transformed output value. The operation of claim 1, wherein the B conversion means receives an upper n / 2 bit and a lower n / 2 bit of the n-bit variable data in response to the clock signal and outputs an operation value multiplied by the fourth coefficient. Way; And adding means for adding the output from the computing means and the luminance value and outputting the luminance value as the B-transformed output value. 5. The dual port according to any one of claims 2 and 4, wherein said computing means latches the lower n / 2 bits and the upper n / 2 bits of the variable data, respectively, on the rising and falling edges of the clock signal, respectively. Double edge storage means; Decoding means for receiving and decoding the latched n / 2-bit data from the storage means and then outputting the data; And a ROM core for outputting a stored multiplication result in response to the decoding result output from the decoding means. The first flip of claim 5, wherein the dual port double edge storage unit is driven in response to any one of a falling edge and a rising edge of the clock signal, and outputs the lower n / 2 bits of the variable data to an output terminal. Flop; A second flip-flop that is driven in response to another edge of a falling edge or a rising edge of the clock signal and outputs upper n / 2 bits of the variable data to an output terminal; And output means for sequentially outputting the variable data output from the first and second flip-flops. 5. A digital color space conversion apparatus using a double edge clock structure as claimed in claim 2 or 4, wherein the adding means each includes a rounding storage adder. 4. The dual port double edge of claim 3, wherein the first or second computing means respectively latches the lower n / 2 bits and the upper n / 2 bits of the variable data on the rising and falling edges of the clock signal. Storage means; Decoding means for receiving and decoding the latched n / 2-bit data from the storage means and then outputting the data; And a ROM core for outputting a multiplication result in response to the decoding result output from the decoding means. According to claim 8, The dual port double edge storage means is driven in response to any one of the falling edge or the rising edge of the clock signal, the first flip for outputting the lower n / 2 bits of the variable data to the output terminal Flop; A second Philip flop that is driven in response to another edge of the falling edge or the rising edge of the clock signal and outputs the upper n / 2 bits of the variable data to an output terminal; And output means for sequentially outputting the variable data output from the first and second flip-flops. 4. The apparatus of claim 3, wherein said adding means comprises a carry-on preserver. 1. A multiplier having a double clock structure, comprising: dual port double edge storage means for latching a lower n / 2 bit and an upper n / 2 bit of variable data at rising and falling edges of a clock signal, respectively; Decoding means for receiving and decoding the latched n / 2-bit data from the storage means and then outputting the data; And a ROM core for outputting a multiplication result in response to the decoding result output from the decoding means. The first flip-flop of claim 11, wherein the dual port edge storage unit is driven in response to any one of a falling edge and a rising edge of the clock signal, and outputs the lower n / 2 bits of the variable data to an output terminal. ; A second flip-flop that is driven in response to another edge of the falling edge or the rising edge of the clock signal and outputs the upper n / 2 bits of the variable data to an output terminal; And output means for sequentially outputting the variable data output from the first and second flip-flops.