KR0183721B1 - Method of manufacturing pattern of metal wire - Google Patents
Method of manufacturing pattern of metal wire Download PDFInfo
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- KR0183721B1 KR0183721B1 KR1019950021382A KR19950021382A KR0183721B1 KR 0183721 B1 KR0183721 B1 KR 0183721B1 KR 1019950021382 A KR1019950021382 A KR 1019950021382A KR 19950021382 A KR19950021382 A KR 19950021382A KR 0183721 B1 KR0183721 B1 KR 0183721B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
Abstract
금속 배선의 패턴을 제조하는 방법에 관하여 개시한다. 포토리소그래피를 이용한 반도체 장치의 금속배선 패턴의 제조방법에 있어서, 반도체 기판상에 형성된 금속배선층위에 금속배선층의 식각시 내구성이 큰 물질층을 형성하는 단계, 상기 물질층위에 포토레지스트를 도포하고 상기 포토레지스트를 금속배선 패턴으로 패터닝하는 단계, 상기 포토레지스트 패턴을 식각마스크로 하여 상기 물질층을 이방성 식각함으로써 상기 포토레지스트 패턴과 상기 물질층의 측벽에 제1식각부산물을 형성하는 단계, 상기 포토레지스트 패턴과 상기 물질층 패턴과 상기 제1식각부산물을 식각마스크로 하여 상기 금속배선층을 이방성 식각하여 금속배선층 패턴의 측벽에 제2식각부산물을 형성하는 단계 및 상기 제1식각부산물, 제2식각부산물, 포토레지스트 패턴 및 물질층 패턴을 제거하는 단계로 이루어지는 것을 특징으로 하는 금속배선 패턴의 제조방법을 제공한다.A method of manufacturing a pattern of a metal wiring is disclosed. A method of manufacturing a metallization pattern of a semiconductor device using photolithography, comprising: forming a material layer having a high durability upon etching a metallization layer on a metallization layer formed on a semiconductor substrate, applying a photoresist on the material layer, and Patterning the resist into a metallization pattern, forming an etch byproduct on sidewalls of the photoresist pattern and the material layer by anisotropically etching the material layer using the photoresist pattern as an etch mask, the photoresist pattern And anisotropically etching the metal wiring layer using the material layer pattern and the first etching by-product as an etch mask to form a second etching by-product on sidewalls of the metal wiring layer pattern, and the first etching by-product, second etching by-product, and photo. Removing the resist pattern and the material layer pattern It provides a method for producing a metal wiring pattern.
본 발명에 의하면 금속배선의 부분적 손실 또는 단선 없이 금속배선 패턴을 형성할 수 있기 때문에 신뢰도 높은 반도체 장치를 제조할 수 있다.According to the present invention, since the metal wiring pattern can be formed without partial loss or disconnection of the metal wiring, a highly reliable semiconductor device can be manufactured.
Description
제1a도 및 제1b도는 종래기술에 의한 반도체 장치 금속 배선 패턴의 제조방법을 설명하기 위해 도시한 단면도들이다.1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device metal wiring pattern according to the prior art.
제2a도 내지 제2d도는 본 발명의 일실시예에 의한 반도체 장치 금속 배선 패턴의 제조방법을 설명하기 위해 도시한 단면도들이다.2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device metallization pattern in accordance with an embodiment of the present invention.
제3도는 본 발명에 의해 형성된 반도체 장치 금속 배선 패턴의 사진이다.3 is a photograph of a semiconductor device metal wiring pattern formed by the present invention.
본 발명은 반도체 장치 금속 배선 패턴의 제조방법에 관한 것으로, 특히 식각시 배선의 단선 및 부분적 손실없이 저결함을 지닌 금속 배선의 패턴을 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device metal wiring pattern, and more particularly, to a method of forming a metal wiring pattern having low defects without disconnection and partial loss of wiring during etching.
최근 반도체 장치의 고집적화 및 동작속도의 고속화에 대한 요구가 높아져 가고 있다. 그러나 기존의 단층 배선을 갖는 반도체 집적회로의 경우 고집적화에 따른 점유면적의 감소로 금속배선의 폭이 줄어들게 되어 배선의 전기저항이 증가하게 된다. 이러한 미세화로 인한 고저항의 금속배선에서 발생하는 도전물질의 전기적 이동과 스트레스에 의한 물질이동에 의한 여러 가지 문제점들이 지적되고 있다. 따라서 미세화에 따른 금속배선의 여러 가지 문제점을 해결하여 고신뢰성 및 고집적도의 반도체 장치를 제조하기 위해서 다층배선기술이 제안되었다.In recent years, the demand for higher integration of semiconductor devices and higher operation speeds is increasing. However, in the case of a conventional semiconductor integrated circuit having a single layer wiring, the width of the metal wiring is reduced due to the reduction of the occupied area due to the high integration, thereby increasing the electrical resistance of the wiring. Due to such miniaturization, various problems due to the electrical movement of the conductive material generated in the high resistance metal wiring and the material movement due to the stress have been pointed out. Therefore, in order to solve various problems of metal wiring due to miniaturization, multilayer wiring technology has been proposed in order to manufacture high reliability and high integration semiconductor devices.
그런데 다층배선구조에서 하층배선이 손상된 상태에서 상층배선을 증착할 경우 단차피복성(step coverge)이 불량하게 되어 상층배선이 단락되거나 접촉면적의 감소로 인하여 접촉저항이 증가됨에 의해 반도체 장치의 전기적 특성이 크게 저하된다.However, when the upper layer wiring is deposited in a state where the lower layer wiring is damaged in the multilayer wiring structure, the step coverge becomes poor, and the electrical resistance of the semiconductor device is increased due to the short circuit of the upper layer wiring or the increase in contact resistance due to the decrease of the contact area. This is greatly reduced.
즉, 반도체 장치의 금속배선 방법은 반도체 장치의 속도, 수율 및 신뢰성을 결정하는 요인이 된다. 따라서 반도체 제조방법의 신뢰도를 높이기 위해서는 금속배선과정에서 발생하는 문제점이 해결되어야만 한다.That is, the metal wiring method of the semiconductor device is a factor for determining the speed, yield and reliability of the semiconductor device. Therefore, in order to increase the reliability of the semiconductor manufacturing method, problems occurring in the metal wiring process must be solved.
제1a도 및 제1b도는 종래기술에 의한 금속배선 패턴의 제조방법의 일예를 설명하기 위해 도시한 단면도들이다.1A and 1B are cross-sectional views illustrating an example of a method of manufacturing a metal wiring pattern according to the prior art.
도면부호 10은 반도체 기판을, 12는 절연층을, 14는 금속층을, 18은 포토레지스트 패턴을 각각 나타낸다.Reference numeral 10 denotes a semiconductor substrate, 12 denotes an insulating layer, 14 denotes a metal layer, and 18 denotes a photoresist pattern.
제1a도는 금속배선 패턴을 형성하기 위한 포토레지스트 패턴(18)을 형성하는 단계를 나타낸다.FIG. 1A shows a step of forming the photoresist pattern 18 for forming the metallization pattern.
반도체 기판(10)상에 절연층(12)을 형성하고 상기 절연층(12)상에 금속, 예컨대 A1을 증착하여 금속층(14)을 형성한 다음 금속층(14)위에 포토레지스트를 도포한다. 이어서 금속배선 형성을 위한 마스크 패턴을 적용하여 포토리소그래피에 의해 포토레지스트 패턴(18)을 형성한다.An insulating layer 12 is formed on the semiconductor substrate 10 and a metal, for example, A1 is deposited on the insulating layer 12 to form a metal layer 14, and then a photoresist is applied on the metal layer 14. Next, a photoresist pattern 18 is formed by photolithography by applying a mask pattern for forming metal wiring.
제1b도는 금속배선 패턴(14A)을 완성하는 단계를 나타낸다.1B illustrates a step of completing the metallization pattern 14A.
상기 포토레지스트 패턴(18)을 식각마스크로 하여 Cl2, BCl3, 및 CHF3가스를 이용한 플라즈마 식각방법으로 상기 금속층(14)을 식각하여 이용한의 패턴(14A)을 형성한다. 이어서 상기 포토레지스트 패턴(18)을 제거함으로써 금속배선의 패턴(14A)을 완성한다.Using the photoresist pattern 18 as an etching mask, a pattern 14A is formed by etching the metal layer 14 by a plasma etching method using Cl 2 , BCl 3 , and CHF 3 gas. Subsequently, the photoresist pattern 18 is removed to complete the pattern 14A of the metal wiring.
그러나 상술한 종래의 기술에 의하면 다음과 같은 문제점이 있다.However, according to the conventional technology described above, there are the following problems.
상기 금속층(14)이 상기 포토레지스트 패턴(18)에 비해 식각 선택비가 높지 않으면 플라즈마를 이용한 식각이 진행되는 동안 상기 포토레지스트 패턴(18)이 식각된다. 따라서 식각에 의해 형성된 금속배선의 패턴이 제1b도에 도시한 바와 같이 배선이 얇아지거나 패턴이 갉아먹은 듯한 모양(20)으로 부분적 손실이 일어난 노칭 (notching) 현상이 발생한다.When the metal layer 14 has an etching selectivity higher than that of the photoresist pattern 18, the photoresist pattern 18 is etched during the etching using plasma. Therefore, a notching phenomenon occurs in which the pattern of the metal wiring formed by etching is partially lost due to the thinning of the wiring or the shape 20 of the pattern as shown in FIG. 1B.
특히 이런 현상은 기하학적인 단차가 커질수록, 포토레지스트의 도포시 도포된 두께가 단차부위에서 얇아지기 때문에 배선의 단선 및 노칭 현상이 심화된다.In particular, as the geometric step becomes larger, the disconnection and notching of the wiring is intensified because the thickness applied when the photoresist is applied becomes thinner at the stepped part.
그런데 배선이 얇아지게 되면 배선의 전기적 저항이 증가하게 되고, 다층배선구조에서 패턴의 프로파일이 불량한 배선이 하층배선으로 형성된 경우, 손상된 하층배선에 상층배선을 증착하면 단차피복성 (step coverge) 이 불량하게 되어 상층배선이 단락되거나 접촉면적의 감소로 인하여 접촉저항이 증가되기 때문에 반도체 장치의 전기적 특성이 크게 저하된다.However, as the wiring becomes thinner, the electrical resistance of the wiring increases, and when the wiring having a poor profile of the pattern is formed as the lower layer wiring in the multilayer wiring structure, if the upper layer wiring is deposited on the damaged lower layer wiring, the step coverge is poor. Therefore, the electrical resistance of the semiconductor device is greatly reduced because the contact resistance is increased due to the short circuit of the upper layer wiring or the decrease in the contact area.
상술한 문제점을 해결하기 위해서 포토레지스트의 높이를 높이거나 금속층의 포토레지스 패턴에 대한 식각선택비를 증가시켜 볼 수 있으나, 포토레지스트의 높이를 높이게 되면 로딩효과(loading effect)에 의해 식각균일성이 악화되는 새로운 문제점이 발생하고, 식각선택비의 증가에는 한계가 있다.In order to solve the above problems, it is possible to increase the height of the photoresist or increase the etching selectivity for the photoresist pattern of the metal layer. However, when the height of the photoresist is increased, the etching uniformity may be caused by the loading effect. New problems are exacerbated and there is a limit to the increase in the etching selectivity.
따라서, 본 발명은 상술한 문제점을 해결하기 위한 것으로, 식각시 배선의 단선 및 부분적 손실이 없는 금속 배선의 패턴을 형성하는 제조방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a manufacturing method for forming a pattern of a metal wiring without disconnection and partial loss of the wiring during etching.
상기 목적을 달성하기 위해 본 발명은, 포토리소그래피를 이용한 반도체 장치의 금속배선 패턴의 제조방법에 있어서, 반도체 기판상에 형성된 금속배선층위에 금속배선층보다 식각선택비가 낮은 물질층을 형성하는 단계; 상기 물질층위에 포토레지스트를 도포하고 패터닝하여 포토레지스트 패턴을 형성하는 단계; 상기 포토레지스트 패턴을 식각마스크로 하여 상기 물질층을 이방성 식각함으로써 상기 포토레지스트 패턴과 상기 물질층의 측벽에 제1식각부산물을 형성하는 단계; 상기 포토레지스트 패턴, 상기 물질층 패턴 및 상기 제1식각부산물을 식각마스크로 하여 상기 금속배선층을 이방성 식각하여 금속배선 패턴을 형성함과 동시에 상기 금속배선 패턴의 측벽에 제2식각부산물을 형성하는 단계; 및 상기 제1식각부산물, 제2식각부산물 및 포토레지스트 패턴을 제거하는 단계를 구비하는 것을 특징으로 하는 금속배선 패턴의 제조방법을 제공한다.According to an aspect of the present invention, there is provided a method of manufacturing a metallization pattern of a semiconductor device using photolithography, comprising: forming a material layer having an etching selectivity lower than that of a metallization layer on a metallization layer formed on a semiconductor substrate; Applying and patterning a photoresist on the material layer to form a photoresist pattern; Anisotropically etching the material layer using the photoresist pattern as an etching mask to form a first etching byproduct on sidewalls of the photoresist pattern and the material layer; Anisotropically etching the metal wiring layer using the photoresist pattern, the material layer pattern, and the first etching by-product as an etch mask to form a metal wiring pattern, and simultaneously forming a second etching by-product on sidewalls of the metal wiring pattern. ; And removing the first etch by-product, the second etch by-product and the photoresist pattern.
본 발명의 바람직한 실시예에 의하면, 상기 금속층은 A1을 이용하여 형성하고, 상기 물질층은 산화물이나 질화물중에서 어느 하나를 이용하여 형성하는 것이 바람직하다.According to a preferred embodiment of the present invention, it is preferable that the metal layer is formed using A1, and the material layer is formed using either oxide or nitride.
상기 물질층을 식각하고 제1식각부산물을 형성하는 이방성식각은 CF4, CHF3등의 불화탄소 (fluoro carbon) 및 O2가스를 이용한 반응성 이온 에칭 (reactive ion etching) 방식에 의해 행하고, 상기 반응성 이온 에칭 (reactive ion etching)시 CF4, CHF3등의 불화탄소 (fluoro carbon) 및 O2가스의 비를 변화시켜 상기 제1식각부산물의 양을 조절할 수 있으며, 상기 반응성 이온 에칭(reactive ion etching)은 O2가스의 유속(flow rate)이불화탄소(fluoro carbon)가스의 유속(flow rate)보다 2배 이상이 되는 조건으로 이방성식각을 행하는 것이 바람직하다.The anisotropic etching for etching the material layer and forming the first etching by-product is performed by reactive ion etching using fluoro carbon and O 2 gas such as CF 4 , CHF 3 , and the like. The amount of the first etch by-product can be controlled by changing the ratio of fluorocarbons such as CF 4 and CHF 3 and O 2 gas during reactive ion etching, and reactive ion etching ) Is preferably anisotropically etched under conditions such that the flow rate of the O 2 gas is more than twice the flow rate of the fluorocarbon gas.
또한 상기 금속배선층을 식각하고 제2식각부산물을 형성하는 이방성식각은 Cl2, BCl3및 CHF3가스를 이용한 반응성 이온 에칭(reactive ion etching)방식에 의해 행하는 것이 바람직하다.In addition, the anisotropic etching for etching the metal wiring layer and forming the second etching by-product is preferably performed by a reactive ion etching method using Cl 2 , BCl 3 and CHF 3 gas.
따라서 본 발명에 의한 반도체 장치의 금속배선 패턴의 제조방법에 의하면 금속 배선 패턴의 노칭현상이나 패턴이 얇아져서 단선되는 현상등이 방지되므로 신뢰도 높은 반도체 장치를 제조할 수 있다.Therefore, according to the method for manufacturing a metal wiring pattern of the semiconductor device according to the present invention, the notching phenomenon of the metal wiring pattern or the phenomenon that the pattern is thinned and disconnected can be prevented, so that a highly reliable semiconductor device can be manufactured.
이하 제2a도 내지 제2d도를 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to FIGS. 2A to 2D.
제1a도 내지 제1b도와 동일한 참조부호는 동일한 부재를 나타낸다.The same reference numerals as those in FIGS. 1A to 1B denote the same members.
제2a도는 절연층(12), 금속층(14), 식각마스크용 물질층(16) 및 포토레지스트 패턴 (18)을 형성하는 단계를 나타낸다.2A illustrates the steps of forming the insulating layer 12, the metal layer 14, the material layer 16 for the etching mask, and the photoresist pattern 18.
반도체 기판(10)상에 절연층(12)을 형성하고 상기 절연층(12)위에 금속, 예컨대 A1을 증착하여 금속층(14)을 형성한다. 상기 금속층(14)위에 식각마스크용 물질, 예컨대 산화물이나 질화물 중에서 어느 하나를 이용하여 물질층(16)을 형성한다. 상기 물질층(16)은 상기 금속층(14)에 대해서 식각선택비가 낮은 것이 바람직하다.The insulating layer 12 is formed on the semiconductor substrate 10, and a metal, for example, A1 is deposited on the insulating layer 12 to form the metal layer 14. The material layer 16 is formed on the metal layer 14 by using an etching mask material such as one of an oxide and a nitride. The material layer 16 may have a low etching selectivity with respect to the metal layer 14.
이어서, 상기 물질층(16)위에 포토레지스트를 도포한 다음, 금속배선 형성을 위한 마스크패턴을 적용하여 상기 물질층(16)위에 포토레지스트 패턴(18)을 형성한다.Subsequently, a photoresist is applied on the material layer 16, and then a photoresist pattern 18 is formed on the material layer 16 by applying a mask pattern for forming metal wiring.
제2b도는 물질층 패턴(16A)과 제1식각부산물(22)을 형성하는 단계를 나타낸다.2B illustrates forming the material layer pattern 16A and the first etching byproduct 22.
상기 포토레지스트 패턴(18)을 식각마스크로 하여 상기 물질층(16)을 예컨대 산화물이나 질화물층을 CF4, CHF3등의 불화탄소(fluoro carbon) 가스와 O2가스를 이용한 반응성 이온 식각(reactive ion etching) 방식으로 식각하여 물질층 패턴(16A)을 형성한다.Reactive ion etching using fluorocarbon gas such as CF 4 , CHF 3 , and O 2 gas as the material layer 16, for example, oxide or nitride layer using the photoresist pattern 18 as an etching mask. The material layer pattern 16A is formed by etching by ion etching.
이 때 상기 개스들이 서로 반응하여 형성된 폴리머인 CFx (X=1,2,3)와 상기 물질층(16)의 과식각(over etch)시 노출되는 A1 표면의 활성화된 A1과 상기 개스의 래디칼등이 반응하여 생성된 AlF3등과 같은 비휘발성 부산물이 상기 포토레지스트 패턴(18)과 상기 물질층 패턴(16A)의 측벽에 스페이서 형태의 제1식각부산물(22)을 형성한다.At this time, the gases formed by reacting with each other CFx (X = 1,2,3) and the activated A1 on the surface of the A1 exposed during overetching of the material layer 16 and the radicals of the gas, etc. The non-volatile by-products such as AlF 3 formed by the reaction form the first etching byproduct 22 in the form of a spacer on the sidewalls of the photoresist pattern 18 and the material layer pattern 16A.
여기에서 상기 CF4, CHF3등의 불화탄소(fluoro carbon) 가스와 O2가스의 비를 변화시켜서 상기 폴리머와 식각부산물의 양을 조절할 수 있고, 특히 CHF3가스의 몰(mole)비를 증가시키면 폴리머가 더욱 많이 형성되며, 식각 챔버내의 온도, 압력, 시간등을 변화시킴으로써 폴리머의 양을 용이하게 조절할 수 있다. 이렇게 폴리머의 양을 조절함으로써 다음 단계에서 형성할 금속배선 패턴의 임계치수를 조절할 수 있다.Here, the amount of the polymer and the etch by-product can be controlled by changing the ratio of the fluorocarbon gas such as CF 4 , CHF 3 and O 2 gas, and in particular, the mole ratio of CHF 3 gas is increased. When the polymer is formed more, the amount of the polymer can be easily controlled by changing the temperature, pressure, and time in the etching chamber. By controlling the amount of polymer in this way it is possible to control the critical dimension of the metallization pattern to be formed in the next step.
제2c도는 금속배선 패턴(14A)을 형성하는 단계를 나타낸다.2C shows the step of forming the metallization pattern 14A.
상기 포토레지스트 패턴(18), 물질층 패턴(16A), 및 제1식각부산물(22)을 식각마스크로 하여 금속층, 예컨대 A1층을 BCl3, Cl2및 CHF3가스를 이용한 반응성 이온 식각(reactive ion etching)방법으로 식각하여 금속배선 패턴(14A)을 형성한다.Reactive ion etching using the photoresist pattern 18, the material layer pattern 16A, and the first etching byproduct 22 as an etching mask using a metal layer such as an A1 layer using BCl 3 , Cl 2, and CHF 3 gases The metallization pattern 14A is formed by etching by ion etching).
이 때 상기 포토레지스트 패턴(18)의 C,H,O 성분은 플라즈마내의 가스와 반응하여 상기 제1식각 부산물(22) 및 금속층 패턴(14A)의 측벽에 제2식각부산물(24)인 폴리머가 스페이서 형태로 형성된다.In this case, the C, H, and O components of the photoresist pattern 18 react with the gas in the plasma to form a polymer as the second etching byproduct 24 on the sidewalls of the first etching byproduct 22 and the metal layer pattern 14A. It is formed in the form of a spacer.
상기 금속층 패턴(14A)의 측벽에 형성된 제2식각부산물(폴리머)(24)은 패시배이션층으로 작용하여 Cl2의 공격에 의해 금속층 측벽이 언더컷되는 것을 방지하는 역할을 한다.The second etching by-product (polymer) 24 formed on the sidewalls of the metal layer pattern 14A serves as a passivation layer to prevent the metal layer sidewalls from being undercut by the attack of Cl 2 .
제2d도는 물질층 패턴(16A)와 금속배선 패턴(14A)을 완성하는 단계를 나타낸다.2d illustrates a step of completing the material layer pattern 16A and the metallization pattern 14A.
상기 포토레지스트 패턴(18), 제1식각부산물(22) 및 제2식각부산물(24)을 에싱(ashing)과 스트립(strip)방법으로 제거함으로써 물질층 패턴(16A)과 금속배선 패턴(14A)을 완성한다.The photoresist pattern 18, the first etching by-product 22, and the second etching by-product 24 are removed by ashing and stripping to form a material layer pattern 16A and a metal wiring pattern 14A. To complete.
제3도는 본 발명에 의해 형성된 금속 배선 패턴의 사진이다.3 is a photograph of a metal wiring pattern formed by the present invention.
26은 절연층, 28은 금속배선 패턴, 30은 식각마스크 물질층을 각각 나타낸다.26 is an insulating layer, 28 is a metallization pattern, and 30 is an etch mask material layer.
제3도에 나타나 있듯이 본 발명에 의해서 금속배선 패턴을 형성하게 되면 배선의 단선 및 부분적 손실없이 저결함의 금속배선 패턴을 형성할 수 있다. 따라서 배선의 단선 및 부분적 손실에 의해서 전기 저항이 증가하여 반도체 장치의 전기적 특성이 열화되는 것이 방지되고 신뢰도 높은 반도체 장치를 제조할 수 있게된다.As shown in FIG. 3, when the metal wiring pattern is formed according to the present invention, a low defect metal wiring pattern can be formed without disconnection or partial loss of the wiring. Therefore, the electrical resistance increases due to disconnection and partial loss of the wiring, thereby preventing the electrical characteristics of the semiconductor device from being deteriorated and making it possible to manufacture a highly reliable semiconductor device.
본 발명이 상기 실시예에 한정되지 않으며, 많은 변형이 본 발명의 기술적 사상내에서 당분야에서 통상의 지식을 가진 자에 의하여 가능함은 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea of the present invention.
Claims (7)
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| KR1019950021382A KR0183721B1 (en) | 1995-07-20 | 1995-07-20 | Method of manufacturing pattern of metal wire |
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| KR1019950021382A KR0183721B1 (en) | 1995-07-20 | 1995-07-20 | Method of manufacturing pattern of metal wire |
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| KR0183721B1 true KR0183721B1 (en) | 1999-04-15 |
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