KR0182010B1 - Isolation method of semiconductor device - Google Patents
Isolation method of semiconductor device Download PDFInfo
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- KR0182010B1 KR0182010B1 KR1019950024828A KR19950024828A KR0182010B1 KR 0182010 B1 KR0182010 B1 KR 0182010B1 KR 1019950024828 A KR1019950024828 A KR 1019950024828A KR 19950024828 A KR19950024828 A KR 19950024828A KR 0182010 B1 KR0182010 B1 KR 0182010B1
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- 238000002955 isolation Methods 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 title abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 36
- 150000004767 nitrides Chemical class 0.000 claims abstract description 32
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 19
- 239000010703 silicon Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 125000006850 spacer group Chemical group 0.000 claims abstract description 11
- 238000005468 ion implantation Methods 0.000 claims abstract description 9
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052796 boron Inorganic materials 0.000 claims abstract description 8
- 238000001020 plasma etching Methods 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims description 12
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 7
- 238000001312 dry etching Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 claims description 2
- 230000003628 erosive effect Effects 0.000 abstract description 6
- 241000293849 Cordylanthus Species 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
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Abstract
반도체 장치의 소자 격리방법으로서 액티브 패턴을 형성한후 질화막을 적층시키고 반응성 이온 식각방식으로 질화막을 식각하고 스페이서를 형성하였다. 이 질화막 스페이서를 마스크로 하여 채널 스톱 이온주입을 실시하고 LOCOS 공정을 수행하여 필드산화막을 형성하였다. 이로써 웨이퍼 표면의 평탄화를 양호하게 하고 실리콘기판과 산화막 계면으로의 붕소에 의한 침식을 줄여 소자의 신뢰성을 높이며 공정의 쓰루풋을 향상시킬 수 있다.After forming an active pattern as a device isolation method of a semiconductor device, nitride films were stacked, nitride films were etched by reactive ion etching, and spacers were formed. Channel stop ion implantation was performed using the nitride film spacer as a mask, and a field oxide film was formed by performing a LOCOS process. This improves the planarization of the wafer surface, reduces the erosion by boron to the silicon substrate and the oxide film interface, thereby improving the reliability of the device and improving the throughput of the process.
Description
제1a도∼e도는 종래기술에 따르는 반도체 장치의 소자격리(Isolation)방법을 나타낸 단면도.1A to 1E are sectional views showing a device isolation method of a semiconductor device according to the prior art.
제2a도∼e도는 본 발명의 실시예에 의한 반도체 장치의 소자 격리방법을 나타낸 단면도이다.2A to 2E are sectional views showing the device isolation method of the semiconductor device according to the embodiment of the present invention.
본 발명은 반도체 장치의 소자 격리방법에 관한 것으로서, 더욱 상세하게 말하자면 웨이퍼 표면의 평탄화(planarization)를 양호하게 하고, LOCOS(Local Oxidation of Silicon) 공정에서 붕소(Boron)의 침식(encroachment)을 줄이며 공정을 단순화시킨 반도체 장치의 소자 격리방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method of a semiconductor device, and more particularly, to improve planarization of a wafer surface and to reduce boron encroachment in a local oxide of silicon (LOCOS) process. A device isolation method of a semiconductor device is provided.
반도체 공정에서 소자의 격리방법에 대한 기술은 매우 중요한 비중을 차지하고 있는데 지금까지 수십년간에 걸쳐 다양한 기술이 연구, 개발되어 왔다. 특히, MOS(Metal Oxide Semiconductor) 집적회로에서는 이웃한 소자들 사이에서 형성되는 기생채널(parasitic channel)을 방지하기 위하여 격리구조가 필요한데 지금까지 개발된 가장 중요한 기법은 LOCOS 격리방법이다. 이 기술은 반도체기판의 필드(field)영역이라고 불리우는 비활성영역에 반(半)우묵한(semirecessed) 산화막을 형성하는 것을 포함한다.Techniques for isolation of devices in semiconductor processes are very important, and various technologies have been researched and developed for decades. In particular, in an MOS integrated circuit, an isolation structure is required to prevent parasitic channels formed between neighboring devices. The most important technique developed so far is the LOCOS isolation method. This technique involves forming a semi- recessed oxide film in an inactive region called a field region of a semiconductor substrate.
소자의 크기가 서브마이크론(submicron) 수준으로 작아짐에 따라 종래의 LOCOS 격리방법은 그 유효성이 한계에 이르렀고 이를 대체할 수 있는 격리방법이 필요해졌다. 그리하여 수정된 LOCOS 공정, 트렌치(trench) 격리, 그리고 선택-에피택셜 (selective-epitaxial) 격리등이 채용되었다. 그밖에도 고전압과 심한 방사(radiation) 환경에서 기능을 수행하는 소자들은 다른 방법의 격리기술이 요구되는데, 이상과 같은 집적회로에 대한 격리기술은 스탠리울프(Stanley Wolf)가 저술한 Silicon Processing for the VLSI Era, Volume 2:Process Integration, CHAP.2 (출판사 : LATTICE PRESS)에 상세하게 나타나 있다.As the device size is reduced to submicron levels, the conventional LOCOS isolation method has reached its limit of effectiveness and an isolation method is needed to replace it. Thus, modified LOCOS processes, trench isolation, and selective-epitaxial isolation were employed. In addition, devices that function in high-voltage and severe radiation environments require different isolation techniques. The isolation techniques for integrated circuits described above include Silicon Processing for the VLSI, written by Stanley Wolf. Era, Volume 2: Process Integration, CHAP.2 (published by LATTICE PRESS).
종래기술의 하나로서 실리콘 식각을 이용한 완전히 우묵한(Fully recessed) 산화막 LOCOS 공정에 의한 격리기술이 제1도에 나타나 있다.As one of the prior art, the isolation technique by a fully recessed oxide LOCOS process using silicon etching is shown in FIG.
상기한 격리기술의 공정순서는 다음과 같다.The process sequence of the above isolation technique is as follows.
제1도(a)에서 보는 바와 같이, 반도체기판(10)에 산화막(11)과 질화막(12)을 차례로 적층시키고 마스크 패턴을 이용하여 비활성화영역(13)을 정의하고 질화막(12)과 산화막(11)을 식각한 다음 이온주입을 실시한다.As shown in FIG. 1A, the oxide film 11 and the nitride film 12 are sequentially stacked on the semiconductor substrate 10, and the inactive region 13 is defined using a mask pattern, and the nitride film 12 and the oxide film ( After etching 11), perform ion implantation.
그리고, 제2질화막(14)과 제2산화막(15)을 적층시킨다.(제1도(b) 참조)Then, the second nitride film 14 and the second oxide film 15 are laminated (see FIG. 1 (b)).
그다음 제1도(c)에서 보는 바와 같이, 건식식각을 이용하여 제1질화막의 사이드월(sidewall)(16)을 제외하고 제2산화막/질화막을 제거한 다음 스페이서(spacer)를 마스크로 하여 노출된 실리콘기판을 0.2㎛의 깊이로 식각한다.Then, as shown in FIG. 1 (c), the second oxide / nitride layer is removed except the sidewall 16 of the first nitride layer by dry etching, and then exposed using a spacer as a mask. The silicon substrate is etched to a depth of 0.2 mu m.
그리고, 실리콘기판이 식각된 홈에 채널-스톱(channel-stop) 이온주입을 실시하고 스페이서상에 남아있는 산화막을 제거하면 제1도(d)와 같은 구조가 된다.In addition, when channel-stop ion implantation is performed in the groove where the silicon substrate is etched and the oxide film remaining on the spacer is removed, the structure as shown in FIG.
그리고, 통상의 습식 산화공정을 거치면 제1도(e)와 같이 필드 산화막(17)이 형성되면서 활성영역(18)이 격리된 최종 프로파일을 얻는다.Then, through the normal wet oxidation process, as shown in FIG. 1 (e), the field oxide film 17 is formed to obtain a final profile in which the active region 18 is isolated.
그런데 상기한 바와 같은 종래의 격리기술은 실리콘기판과 산화막 계면에서의 붕소에 의한 침식현상과 필드산화막 성장시 전위(轉位,dislocation)결함을 발생시키고 공정이 복잡해지는 문제점이 있다.However, the conventional isolation techniques as described above have problems such as erosion caused by boron at the interface between the silicon substrate and the oxide film, dislocation defects during field oxide film growth, and complicated process.
따라서, 본 발명의 목적은 상기한 바와 같이 종래기술의 문제점을 해결하기 위한 것으로서, 웨이퍼 표면의 평탄화를 양호하게 하고 실리콘기판과 산화막 계면에서 붕소의 침식을 줄이며 공정을 단순화시킨 반도체 장치의 소자격리방법을 제공하는데 있다.Accordingly, an object of the present invention is to solve the problems of the prior art as described above, and to improve the planarization of the wafer surface, reduce the erosion of boron at the interface between the silicon substrate and the oxide film, and simplify the process of device isolation of a semiconductor device. To provide.
상기한 목적을 달성하기 위하여, 본 발명은, 실리콘기판 위에 산화막을 적층시키고 그 위에 저압 화학 기상증착(LPCVD,Low Pressure Chemical Vapor Deposition)에 의한 제1질화막을 증착하는 제1공정, 액티브(Active) 마스크를 이용하여 패턴을 형성하고 건식식각 방식으로 제1질화막과 산화막을 식각하고 실리콘을 식각하여 활성영역을 정의하고 감광막을 제거한 다음 제2질화막을 LPCVD방식으로 증착하는 제2공정, 반응성 이온 식각(RIE,Reactive Ion Etching) 방식으로 제2질화막을 식각하여 질화막 스페이서를 형성하는 제3공정, 상기한 스페이서를 마스크로하여 채널 스톱 이온주입을 실시하는 제4공정, LOCOS 공정으로 필드산화막을 형성시키는 제5공정으로 이루어짐을 특징으로 하는 반도체 장치의 소자 격리방법을 제공한다.In order to achieve the above object, the present invention, the first step of depositing an oxide film on a silicon substrate and a first nitride film by LPCVD (Low Pressure Chemical Vapor Deposition), active (Active) The second process of forming a pattern using a mask, etching the first nitride film and the oxide film by dry etching, etching the silicon to define an active region, removing the photoresist, and depositing the second nitride film by LPCVD, reactive ion etching ( A third process of forming a nitride spacer by etching the second nitride film by a RIE (Reactive Ion Etching) method, a fourth process of performing channel stop ion implantation using the spacer as a mask, and a process of forming a field oxide film by a LOCOS process A device isolation method for a semiconductor device, comprising five steps, is provided.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진자가 본 발명을 용이하게 실시할 수 있을 정도로 상세하게 설명하기 위하여 본 발명의 가장 바람직한 실시예를 첨부한 도면에 따라 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention.
제2도는 본 발명의 실시예에 의한 반도체 장치의 소자 격리방법을 나타낸 단면도이다.2 is a cross-sectional view showing a device isolation method of a semiconductor device according to an embodiment of the present invention.
우선, 제2도(a)에서 보는 바와 같이, 실리콘기판(20) 위에 200-500Å의 산화막(21)을 적층시키고 그 위에 LPCVD에 의한 제1질화막(22)을 1000-1500Å 증착한다. 여기서, 산화막 및 질화막의 두께는 LOCOS 공정시 새부리(Bird's beak) 모양의 침식에 대한 길이 및 두께를 좌우하고, 질화막의 스트레스를 결정하며 이 스트레스에 의한 필드산화막의 재질에 영향을 미친다.First, as shown in FIG. 2A, a 200-500 mW oxide film 21 is laminated on the silicon substrate 20, and the first nitride film 22 by LPCVD is deposited thereon. Here, the thicknesses of the oxide film and the nitride film determine the length and thickness of the bird's beak erosion during the LOCOS process, determine the stress of the nitride film, and affect the material of the field oxide film by the stress.
그 다음 제2도(b)에서와 같이, 액티브(Active) 마스크를 이용하여 패턴을 형성하고 건식식각 방식으로 제1질화막(22)과 산화막(21)과 실리콘(20)을 부분적으로 식각하여 활성영역을 정의한다. 여기서, 건식식각은 EDP(End Point Detection)방식을 사용하여 진행하는데, 식각 완료후 실리콘기판의 손상을 줄이기 위하여 CF4나 SF6를 사용하여 수초 정도 부드럽게 실리콘기판을 딥에치(dip-etch)한다. 이러한 실리콘기판의 식각은 LOCOS 공정후 웨이퍼 표면의 평탄화를 결정짓는 중요한 단계이다.Next, as shown in FIG. 2 (b), a pattern is formed using an active mask, and the first nitride layer 22, the oxide layer 21, and the silicon 20 are partially etched by dry etching. Define the area. Here, dry etching is performed by using an end point detection (EDP) method. To reduce damage to the silicon substrate after completion of etching, the silicon substrate is dip-etched smoothly for several seconds using CF 4 or SF 6 . do. The etching of the silicon substrate is an important step in determining the planarization of the wafer surface after the LOCOS process.
그리고, 감광막을 제거하고 제2질화막(23)을 LPCVD방식으로 1000-2000Å 증착한다. 여기서, 제2질화막은 액티브영역의 확보를 통하여 MOS 소자의 특성중 좁은 폭 효과(Narrow width effect)를 보완하거나 액티브의 리사이징(resizing) 요소의 적정조건을 조절할 수 있는 항목이 된다. 그런데, 제2질화막의 두께는 상기한 산화막의 두께보다 항상 두껍게 조절하는 것이 필요하다.Then, the photoresist film is removed and the second nitride film 23 is deposited at 1000-2000 Pa by LPCVD. Here, the second nitride film is an item that can compensate for the narrow width effect of the characteristics of the MOS device through the securing of the active region or to adjust the appropriate condition of the active resizing element. By the way, it is necessary to always adjust the thickness of the second nitride film to be thicker than the thickness of the oxide film.
그다음 제2도(c)에서 보는 바와 같이, 반응성 이온 식각 방식으로 제2질화막을 식각하여 질화막 스페이서(24)를 형성한다. 여기서, 질화막 스페이서(24)의 유효 길이의 조절이 액티브영역의 확보에 중요한 인자가 되며, 또한 채널 스톱 이온주입에 의한 붕소의 침식을 감소시킴으로써 신뢰성을 높일 수 있는 요소이다.Next, as shown in FIG. 2C, the second nitride layer is etched by using reactive ion etching to form the nitride layer spacer 24. Here, the adjustment of the effective length of the nitride film spacer 24 is an important factor in securing the active region, and the element which can increase the reliability by reducing the erosion of boron by channel stop ion implantation.
그리고, 상기한 스페이서를 마스크로하여 채널 스톱 이온주입을 실시하는데 소스로는 붕소 또는 이불화붕소(BF2)를 사용하고 에너지는 ∼E13 정도로 진행한다.(제2도(d) 참조)In addition, channel stop ion implantation is performed using the spacer as a mask, and boron or boron difluoride (BF 2 ) is used as a source, and the energy proceeds to about E13 (see FIG. 2 (d)).
그다음 LOCOS 공정으로 산화막을 성장시키면 제2도(e)에서 보는 바와 같이, 필드산화막(25)이 형성된다. 이때 상기한 실리콘기판의 식각 정도에 따라 LOCOS 산화막의 두께를 조절할 수 있다. 그런다음 제1, 2질화막과 산화막을 제거하고 이후 공정을 진행시킨다.Then, when the oxide film is grown by the LOCOS process, as shown in FIG. 2E, the field oxide film 25 is formed. In this case, the thickness of the LOCOS oxide layer may be adjusted according to the etching degree of the silicon substrate. Then, the first and second nitride films and the oxide film are removed, and then the process is performed.
이상과 같은 본발명에 따르는 제조공정을 이용하면, 실리콘 식각을 통하여 표면의 평탄화를 양호하게할 수 있고 질화막 스페이서를 이용한 붕소의 침식을 감소시켜 소자의 신뢰성을 높일 수 있는 효과가 있다. 또한, 버즈-빅(bird's beak)의 길이와 두께를 감소시키며 필드산화막의 두께를 낮추어 공정의 쓰루풋(throughput)을 증진시킬 수 있는 잇점이 있다.Using the manufacturing process according to the present invention as described above, it is possible to improve the planarization of the surface through the silicon etching, and to reduce the erosion of boron using the nitride film spacer has the effect of increasing the reliability of the device. In addition, there is an advantage that can reduce the length and thickness of the bird's beak and to improve the throughput of the process by reducing the thickness of the field oxide film.
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