KR970013185A - Device isolation method of semiconductor device - Google Patents

Device isolation method of semiconductor device Download PDF

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Publication number
KR970013185A
KR970013185A KR1019950024828A KR19950024828A KR970013185A KR 970013185 A KR970013185 A KR 970013185A KR 1019950024828 A KR1019950024828 A KR 1019950024828A KR 19950024828 A KR19950024828 A KR 19950024828A KR 970013185 A KR970013185 A KR 970013185A
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South Korea
Prior art keywords
nitride film
oxide film
thickness
device isolation
etching
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KR1019950024828A
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Korean (ko)
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KR0182010B1 (en
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배성열
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Drying Of Semiconductors (AREA)
  • Element Separation (AREA)

Abstract

반도체 장치의 소자 격리방법으로서 엑티브 패턴을 형성한후 질화막을 적층시키고 반응성 이온 식각방식으로 질화막을 식각하고 스페이서를 형성하였다. 이 질화막 스페이서를 마스크로 하여 채널 스톱 이온주입을 실시하고 LOCOS 공정을 수행하여 필드산화막을 형성하였다. 이로써 웨이퍼 표면의 평탄화를 양호하게 하고 실리콘기판과 산화막 계면으로서 붕소에 의한 침식을 줄여 소자의 신뢰성을 높이며 공정의 쓰루풋을 향상시킬 수 있다.After forming an active pattern as a device isolation method of a semiconductor device, nitride films were stacked, nitride films were etched by reactive ion etching, and spacers were formed. Channel stop ion implantation was performed using the nitride film spacer as a mask, and a field oxide film was formed by performing a LOCOS process. This improves the planarization of the wafer surface, reduces erosion by boron as the interface between the silicon substrate and the oxide film, thereby increasing the reliability of the device and improving the throughput of the process.

Description

반도체 장치의 소자 격리방법Device isolation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도의 (가)∼(마)는 본 발명의 실시예에 의한 반도체 장치의 소자 격리방법을 나타낸 단면도이다.2A to 2E are cross-sectional views showing a device isolation method of a semiconductor device according to an embodiment of the present invention.

Claims (9)

실리콘기판 위에 산화막을 적층시키고 그 위에 저압 화학 기상증착에 의한 제1질화막을 증착하는 제1공정, 액티브 마스크를 이용하여 패턴을 형성하고 건식식각 방식으로 제1질화막과 산화막을 식각하여 활성영역을 정의하고 감광막을 제거한 다음 제2질화막을 저압 화학 기상증착 방식으로 증착하는 제2공정, 반응성 이온 식각 방식으로 제2질화막을 식각하여 질화막 스페이서를 형성하는 제3공정, 상기한 스페이서를 마스크로하여 채널 스톱 이온주입을 실시하는 제4공정, LOCOS 공정으로 필드산화막을 형성시키는 제5공정을 포함하여 이루어지는 것을 특징으로 하는 반도체 장치의 소자 격리방법The first step of depositing an oxide film on a silicon substrate and depositing a first nitride film by low pressure chemical vapor deposition, forming a pattern using an active mask and etching the first nitride film and the oxide film by dry etching to define an active region. The second step of removing the photoresist film and depositing the second nitride film by low pressure chemical vapor deposition, the third step of etching the second nitride film by reactive ion etching to form nitride film spacers, and the channel stop using the spacer as a mask. And a fifth step of forming a field oxide film by a LOCOS step and a fourth step of performing ion implantation. 제1항에 있어서, 상기한 건식식각후에 실리콘기판을 딥에치하는 공정을 더 포함하여 이루어지는 것을 특징으로 하는 반도체 장치의 소자 격리방법2. The method of claim 1, further comprising a step of deep etching the silicon substrate after the dry etching. 제2항에 있어서, 상기한 딥에치의 소스로는 CF4나 SF6가스를 사용하는 것을 특징으로 하는 반도체 장치의 소자 격리방법The device isolation method of claim 2, wherein CF 4 or SF 6 gas is used as the source of the deep etch. 제1항에 있어서, 상기한 제2질화막의 두께는 상기한 산화막의 두께보다 항상 크게 성장시키는 것을 특징으로 하는 반도체 장치의 소자 격리방법The method of claim 1, wherein the thickness of the second nitride film is always larger than the thickness of the oxide film. 제1항 또는 제4항에 있어서, 상기한 산화막의 두께는 200-500Å의 범위인 것을 특징으로 하는 반도체 장치의 소자 격리방법5. The device isolation method of claim 1 or 4, wherein the oxide film has a thickness in the range of 200 to 500 mW. 제1항에 있어서, 상기한 제1질화막의 두께는 1000-1500Å의 범위인 것을 특징으로 하는 반도체 장치의 소자 격리방법2. The method of claim 1, wherein the thickness of the first nitride film is in the range of 1000-1500 GPa. 제1항 또는 제4항에 있어서, 상기한 제2질화막의 두께는 1000-2000Å의 범위인 것을 특징으로 하는 반도체 장치의 소자 격리방법The device isolation method of claim 1, wherein the thickness of the second nitride film is in the range of 1000-2000 kPa. 제1항에 있어서, 상기한 채널 스톱 이온주입의 소스는 붕소나 이불화붕소인 것을 특징으로 하는 반도체 장치의 소자 격리방법The method of claim 1, wherein the source of the channel stop ion implantation is boron or boron difluoride. 제1항 또는 제8항에 있어서, 상기한 이온주입의 에너지는 13 누승인 것을 특징으로 하는 반도체 장치의 소자 격리방법The device isolation method of claim 1, wherein the energy of the ion implantation is 13 power.
KR1019950024828A 1995-08-11 1995-08-11 Isolation method of semiconductor device KR0182010B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100439110B1 (en) * 1997-12-31 2004-07-16 주식회사 하이닉스반도체 Isolation method of semiconductor device to improve separation characteristic and reliability

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100439110B1 (en) * 1997-12-31 2004-07-16 주식회사 하이닉스반도체 Isolation method of semiconductor device to improve separation characteristic and reliability

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