KR0164846B1 - Circuit for making a son-screen video signal of digital vcr - Google Patents

Abstract

None.

Description

Sub picture signal generation circuit in digital VCR

1 is a circuit diagram of the present invention.

(A)-(l) of FIG. 2 are operation waveform diagrams of each part of the circuit of the present invention.

3 is an operation principle and a screen output state diagram of the circuit of the present invention.

4 is an output waveform diagram of a D / A converter 17 in the circuit of the present invention.

(A) of FIG. 5 is a window state increase state by this invention.

Figure 5 (b) is a window reduction state in accordance with the present invention.

6 is a conventional digital sub picture image signal generation circuit.

* Explanation of symbols for main parts of the drawings

1: synchronous separator 2: clock generator

3,7: R-S flip-flop 4,8,13: 8-bit up / down counter

5,9: Inverter 6,11,17: D / A Converter

10,12,16: AND Gate 14: System Microcomputer

15: ORGATE 18, 19: Comparator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sub picture video signal generation circuit in a digital VCR, and more particularly to a sub picture video signal in a digital VCR, which enables a mother / child screen to be easily switched without using a separate dedicated microcomputer or a dedicated integrated IC. It relates to a generation circuit.

As shown in FIG. 6, a sub picture image signal generating circuit of a conventional digital VCR includes a microcomputer 31 for receiving horizontal and vertical synchronization signals H-SYNC and V-SYNC and outputting various timing signals; A triangular wave oscillator 32 for receiving a horizontal synchronization signal H-SYNC from the microcomputer 31 and outputting a predetermined triangular wave; A D / A converter 33 for converting digital predetermined data output from the microcomputer 31 into an analog signal; A comparator (34) for comparing the output of the triangular wave oscillator (32) with the output of the D / A converter (33); The vertical timing signal output from the microcomputer 31 and the output of the comparator 34 are logically applied to the switch SW ₁ to which the mother video signal and the digital video signal are respectively input to the fixed terminals A and B, respectively. It is provided with the AND gate 35 to make, the operation relationship is as follows.

First, the triangular wave oscillator 32 receives the horizontal synchronizing signal (H-SYNC) from the microcomputer 31 and outputs a triangular wave to the inverting input terminal (-) of the comparator 34, and the D / A converter 33 The microcomputer 31 receives a predetermined digital signal in parallel from the microcomputer 31 in parallel and converts the digital signal into an analog signal and outputs it in series to the non-inverting input terminal (+) of the comparator 34. When both the vertical signal output from the output terminal and the output of the comparator 34 are 'high', the output of the AND gate 35 becomes 'high', so the movable terminal C of the switch SW ₁ is fixed to the terminal A. Video signal of the mother screen is output, and when the output of the comparator 34 is 'low' or the vertical signal is not output from the microcomputer 31, the movable terminal C of the switch SW ₁ is fixed. It is connected to the terminal B side, and typically a digital video signal is output.

However, such a conventional device requires a dedicated microcomputer or a dedicated IC for oscillating a triangular wave, so that the production cost of the product is increased and it cannot be integrated into a gate array or a custom IC. there was.

The present invention has been proposed to solve such a conventional problem, and the screen is easier to convert from a digital video signal to a mother / child screen through a synchronous separator, a counter, a D / A converter, a comparator, and a plurality of logic gates. In addition, it is possible to easily use the signals output from the system microcomputer even without using a dedicated microcomputer or a dedicated IC, so that the video signal generation circuit of the digital screen can be greatly reduced. An object of the present invention will be described in detail below with reference to the accompanying drawings.

As shown in FIG. 1, the configuration of the present invention comprises: a sync separator 1 for separating horizontal and vertical sync signals in a mother screen video signal; A clock generator (2) for receiving a horizontal sync signal (HD) from the sync separator (1) and generating a predetermined (256 fH) clock signal; An RS flip-flop (3) which is set to a horizontal synchronizing signal (HD) output from said synchronizing separator (1) and outputs a predetermined up / down control signal to an 8-bit up / down counter (4); An 8-bit up / down counter (4) for counting the clock signal output from the clock generator (2) up or down and outputting it in 8 bits; An inverter ( ₅ ) for inverting the output (Q6) signal of the 8-bit up / down counter (4) and applying it to the reset signal of the RS flip-flop (3); A D / A converter (6) which receives a predetermined digital signal from the 8-bit up / down counter (4) in parallel and converts it into an analog signal; An RS flip-flop (7) which is set by the vertical synchronizing signal (VD) output from the synchronizing separator (1) and outputs a predetermined up / down control signal to the 8 beater up / down counter (8); An 8-bit up / down counter (8) which receives the horizontal synchronizing signal (HD) output from the sync separator (1) as a clock signal and performs up or down counting; Inverting the output Q ₆ signal of the 8-bit up / down counter 8 to output a reset signal to the RS flip-flop 7 and to apply a predetermined signal to one input terminal of the AND gate 10. An inverter 9; A D / A converter (11) for converting a predetermined digital signal output from the 8-bit up / down counter (8) into an analog signal; An AND gate 10 that applies a clock signal to an 8-bit up / down counter 13 by logically outputting the vertical synchronization signal VD outputted from the synchronization separator 1 and the output signal of the inverter 9; An 8-bit up / down counter 13 for up or down counting the output signal of the AND gate 10 by an up / down control signal output from the system microcomputer 14; An OR gate and an AND gate for inputting the output Q ₀ and Q ₆ signals of the 8-bit up / down counter 13 to the input terminals END ₁ and END ₂ of the system microcomputer 14, respectively. 15,16); A D / A converter 17 for converting a predetermined digital signal output from the 8-bit up / down counter 13 into an analog signal; Comparators 18 and 19 for comparing the output signals of the D / A converters 6 and 11 and the output signals of the D / A converters 17, respectively; An AND gate 12 that logically outputs the output signals of the comparators 18 and 19 to the fixed terminals A and B as control signals of the switch SW ₁ to which the mother screen video signal and the digital video signal are respectively input. In this case, reference numeral EN denotes an enable terminal, REF H, and REF L, a terminal for controlling the output voltage of the D / A converters 6, 11, and 17, and 4V is applied to the REF H terminal. 1V is set to be applied to the REF L terminal, so that the maximum output voltage of the D / A converters 6, 11 and 17 is 4V, and the minimum output voltage is 1V.

Referring to the effects of the present invention configured as described above with reference to (a)-(l) of FIG. 2 to (a), (b) of FIG.

First, the mother screen image signal as shown in (a) of FIG. 2 is separated into horizontal and vertical sync signals (HD and VD) as shown in (b) and (c) of FIG. The generator 2 receives the horizontal synchronizing signal HD as shown in (b) and (h) of FIG. 2 from the synchronizing separator 1 and generates 256 pulses during 1H.

In addition, the RS flip-flop 3 is set by the horizontal synchronizing signal HD output from the synchronizing separator 1, and the 'high' signal as shown in (i) of FIG. 2 is output from the output terminal Q thereof. The 8-bit up / down counter 4 enters the up count state.

Therefore, the 8-bit up / down counter 4 is cleared by the first horizontal synchronization signal HD and then starts to count the 256fH clock output from the clock generator 2, so that the D / A counter 6 The output becomes as shown in (l) of FIG. 2, wherein the count value of the 8-bit up / down counter 4 reaches 128 and a 'high' signal is output from the output terminal Q _{6 thereof} . RS output flop 3 is reset because the output of? Becomes 'low' as shown in (k) of FIG.

Accordingly, since the output of the RS flip-flop 3 becomes 'low' as shown in (i) of FIG. 2, the 8-bit up / down counter 4 starts the down counting, and the output of the D / A converter 6 stops. It decreases as (1) of 2 degrees, and this output waveform is repeated every 1H.

In addition, the 8-bit up / down counter 8 is cleared by the vertical synchronizing signal VD as shown in (c) of FIG. 2 output from the synchronous separator 1, and then output terminal Q of the RS flip-flop 7. When the up-sync state is changed by the 'high' signal as shown in (l) of FIG. 2, and the vertical sync signal VD is released, the up-count coefficient is applied whenever the horizontal sync signal HD is input (that is, every 1H). Done.

Thereafter, when the count value of the 8-bit up / down counter 8 reaches 128 and the output of the inverter 9 becomes 'low' as shown in FIG. 2 (f), the output of the RS flip-flop 7 becomes second. As shown in (d) of FIG. 8, the 8-bit up / down counter 8 starts the down counting. At this time, the output of the D / A converter 11 is displayed for each field as shown in (g) of FIG. The waveform is repeated.

Meanwhile, the 8-bit up / down counter 13, which is controlled by the system micom 14 and controls the increase and decrease of the sub picture window, loads predetermined data when the start pulse is output from the system micom 14. After that, the up or down coefficient is performed according to the output pulse of the AND gate 10. That is, when the window of the child screen is increased as shown in (a) of FIG. 5, the down counter operates. When the window of the child screen is reduced as shown in (b) of FIG. 5, the 8-bit up / down counter 13 is operated. The output of the D / A converter 17 is as shown in FIG.

In addition, the output of the AND gate 10 is a logic between the vertical synchronization signal VD output from the synchronization separator 1 and the inverted output Q ₆ of the 8-bit up / down counter 12, so that two pulses are provided in one field. Is generated (i.e., one pulse is generated every 1/120 seconds).

Therefore, the output of the D / A converter 17 outputs the waveform shown in Fig. 4, and the full swing time is 1/120 sec. X 2 ⁸ = 2.13 sec. The window increases as shown in Fig. 5 (a). In this case, it takes 2.13 seconds for the screen to start at the center point and become full screen. In addition, if the output of the D / A converter 17 becomes equal to FIG. 3 at a certain time when the window is increased as shown in (a) of FIG. 5, the outputs of the comparators 18 and 19 are all 'high'. Since the output of (12) becomes 'high' and the movable terminal C of the switch SW ₁ is connected to the fixed terminal B side, the child screen is output and any one of the outputs of the comparators 18 and 19 is output. When the output of the AND gate 12 becomes low, the movable terminal C of the switch SW ₁ is connected to the fixed terminal A side, and the mother screen is output during this period.

Therefore, in the case of (a) of FIG. 5, the output voltage of the D / A converter 17 gradually decreases, so that the area of the magnetic screen becomes wider. In the case of the window of FIG. 5 (b), the microcomputer ( 14) clears the 8-bit up / down counter 13 by outputting a clear signal, so that the 8-bit up / down counter 13 performs the up count, so that the output of the D / A converter 17 is a dotted line in FIG. As shown in Fig. 1, the screen is gradually increased from 1V, and the sub-screen is gradually reduced from the full-screen display and finally appears as a dot and disappears.

As described above, according to the present invention, not only screen switching is more easily performed when switching between mother and child screens in digital video signals, but also a predetermined control signal and a plurality of predetermined control signals outputted from the system microcomputer without using a dedicated microcomputer or a dedicated IC. The system can be configured using two counters and D / A converters, which greatly facilitates integration and significantly reduces the production cost of the product.

Claims (1)

A sync separator 1 for separating horizontal and vertical sync signals in the mother screen video signal; A clock generator (2) for receiving a horizontal synchronizing signal (HD) from the synchronous separator (1) and generating a predetermined clock signal; An RS flip-flop (3) which is set to a horizontal synchronizing signal (HD) output from said synchronizing separator (1) and outputs a predetermined up / down control signal to an 8-bit up / down counter (4); An 8-bit up / down counter (4) for counting the clock signal output from the clock generator (2) up or down and outputting it in 8 bits; An inverter ( ₅ ) for inverting the output (Q6) signal of the 8-bit up / down counter (4) and applying it to the reset signal of the RS flip-flop (3); A D / A converter (6) which receives a predetermined digital signal from the 8-bit up / down counter (4) in parallel and converts it into an analog signal; An RS flip-flop (7) which is set by the vertical synchronizing signal (VD) output from the synchronizing separator (1) and outputs a predetermined up / down control signal to the 8 beater up / down counter (8); An 8-bit up / down counter (8) which receives the horizontal synchronizing signal (HD) output from the sync separator (1) as a clock signal and performs up or down counting; Inverting the output Q ₆ signal of the 8-bit up / down counter 8 to output a reset signal to the RS flip-flop 7 and to apply a predetermined signal to one input terminal of the AND gate 10. An inverter 9; A D / A converter (11) for converting a predetermined digital signal output from the 8-bit up / down counter (8) into an analog signal; An AND gate 10 that applies a clock signal to an 8-bit up / down counter 13 by logically outputting the vertical synchronization signal VD outputted from the synchronization separator 1 and the output signal of the inverter 9; An 8-bit up / down counter 13 for up or down counting the output signal of the AND gate 10 by an up / down control signal output from the system microcomputer 14; An OR gate and an AND gate for inputting the output Q ₀ and Q ₆ signals of the 8-bit up / down counter 13 to the input terminals END ₁ and END ₂ of the system microcomputer 14, respectively. 15,16); A D / A converter 17 for converting a predetermined digital signal output from the 8-bit up / down counter 13 into an analog signal; Comparators 18 and 19 for comparing the output signals of the D / A converters 6 and 11 and the output signals of the D / A converters 17, respectively; An AND gate 12 that logically outputs the output signals of the comparators 18 and 19 to the fixed terminals A and B as control signals of the switch SW ₁ to which the mother screen video signal and the digital video signal are respectively input. A sub picture video signal generation circuit in a digital VCR, characterized in that it is provided.

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