KR920001485A - Sub picture signal generation circuit in digital VCR - Google Patents

Abstract

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Description

Sub picture signal generation circuit in digital VCR

As this is a public information case, the full text was not included.

1 is a circuit diagram of the present invention.

(A)-(d) of FIG. 2 are operation waveform diagrams of each part of the circuit of the present invention.

3 is an operation principle and a screen output state diagram of the circuit of the present invention.

Claims (1)

A synchronous separator 1 for separating horizontal and vertical synchronous signals in the mother screen image signal; and a clock generator 2 for receiving a horizontal synchronous signal HD from the synchronous separator 1 and generating a predetermined clock signal; Wow; An RS flip-flop (3) which is set to a horizontal synchronizing signal (HD) output from the synchronizing separator (1) and outputs a predetermined up / down control signal to an 8-bit up / down counter (4); An 8-bit up / down counter 4 for counting a clock signal output from the clock generator 2 up or down and outputting 8 bits; An inverter ( ₅ ) for inverting the output (Q6) signal of the 8-bit up / down counter (4) and applying it to the reset signal of the RS flip-flop (3); A D / A converter (6) which receives a predetermined digital signal from the 8-bit up / down counter (4) in parallel and converts it into an analog signal; An RS flip-flop (7) which is set by the vertical synchronizing signal (VD) output from the synchronous separator (1) and outputs a predetermined up / down control signal to an 8-bit up / down counter (8); An 8-bit up / down counter (8) which receives the horizontal synchronizing signal (HD) output from the sync separator (1) as a clock signal and performs up or down counting; Inverting the output Q ₆ signal of the 8-bit up / down counter 8 to output a reset signal to the RS flip-flop 7 and to apply a predetermined signal to one input terminal of the AND gate 10. An inverter 9; A D / A converter (11) for converting a predetermined digital signal output from the 8-bit up / down counter (8) into an analog signal; An AND gate 10 for applying a clock signal to the 8-bit up / down counter 13 by logically combining the vertical synchronizing signal VD output from the synchronizing separator 1 and the output signal of the inverter 9, and a system; An 8-bit up / down counter 13 for up or down counting the output signal of the AND gate 10 by an up / down control signal output from the microcomputer 14; An OR gate and an AND gate for inputting the output Q ₀ and Q ₆ signals of the 8-bit up / down counter 13 to the input terminals END ₁ and END ₂ of the system microcomputer 14, respectively. 15,16); A D / A converter 17 for converting a predetermined digital signal output from the 8-bit up / down counter 13 into an analog signal; Comparators (18, 19) for comparing the output signals of the D / A (6, 11) and the output signals of the D / A converter (17), respectively; The AND gate 12 which logically outputs the output signals of the comparators 18 and 19 and applies them to the fixed terminals A and B as control signals of the switch SW ₁ to which the mother screen video signal and the digital video signal are respectively input. And a sub picture image signal generation circuit in a digital VCR. ※ Note: It is to be disclosed based on the initial application.