KR0159432B1 - Circuit and method for operating non-sync. screen - Google Patents

Abstract

[Technical field to which the invention described in the claims belong]

Asynchronous screen processing device that handles asynchronous between main screen and sub screen of video

[Technical Challenges to Invent]

The present invention provides an asynchronous screen processing apparatus and method for preventing image distortion (line reversal) and passing through between asynchronous screens regardless of the capacity of the external memory of the chip, and operating with compatibility with the double window mode and the PIP mode.

[Summary of the solution of the invention]

In the present invention, when the sub-memory memory is used as a memory for storing one field, the sub-screen is ignored so as to ignore the passing throw and prevent only line inversion, and the memory for storing two fields and the memory for storing three fields are used. In this case, it prevents both passing throw and line reversal.

[Important Uses of the Invention]

Picture In Picture System

Description

Asynchronous Screen Processing Unit and Method

1 is a block diagram of a conventional asynchronous screen processing apparatus.

2 is a block diagram of an asynchronous screen processing apparatus according to the present invention.

FIG. 3 is a block diagram illustrating a concrete block of the write row address generator of FIG.

4 is a detailed block diagram of a read row address generator of FIG.

5A to 5C are diagrams showing the screen configuration when one field memory is used as the field memory of FIG.

6A and 6B are diagrams for explaining the generation of passing throws and vertical salts according to the shape of the main field and the subfield of the screen, and a method of correcting them.

7A and 7B are diagrams for explaining that passing through does not occur when two field memories are used as the field memories of FIG.

The present invention relates to an image processing system, and more particularly, to an asynchronous screen processing apparatus for processing asynchronous processing between a main screen and a sub screen of an image.

Passing through phenomenon in a device that handles asynchronous processing between the main screen (the screen used as the display standard) and the sub screen, such as a double window, a double scan double-picture picture in picture, and a four-screen CCTV There is a need for a technique that prevents excessive vertical jolts. Passing through refers to a phenomenon in which the read speed of the video RAM storing the sub picture is overtaken by the write speed so that the current field and the previous field are simultaneously displayed on one sub picture. The vertical jolt phenomenon refers to a phenomenon in which line inversion occurs due to a misalignment between a field of a main screen (hereinafter referred to as a main field) and a field of a sub screen (hereinafter referred to as a subfield).

FIG. 1 is a block diagram of a conventional asynchronous screen processing apparatus that is implemented to prevent such a pass through phenomenon (hereinafter referred to as a line inversion phenomenon) and a vertical salt phenomenon.

The field discrimination unit 2 has the vertical synchronization signal of the main screen, and the field discrimination unit 4 has the vertical synchronization signal of the sub screen, and discriminates each field, and outputs it to the sub lead address generator 6 which determines the lead address of the sub screen. do. Video RAM 8, on the other hand, has three field capacities as a memory for storing a sub picture. At this time, the sub picture data writing to the memory is performed in the order of A → B → C → A area for each sub vertical synchronizing signal at a predetermined interval by the control of the write address generation unit 5 of the sub vertical synchronizing signals generated every time. The lead is determined by the sub lead address generator 6 based on the main field and the sub field. If the fields of the sub screen and the main screen are the same, the sub lead address generation unit 6 selects two previous areas of the area to be written now, that is, one area after the one (B area if the area to be written is A area) and the fields are different from each other. In this case, the generation unit 6 controls to lead the area before one, that is, the area after the two (C area if the area to be written is A area). This memory write and read operation prevents passing throws and vertical salts. Since the sub picture read from the video RAM 8 is synthesized with the main screen by the synthesizer 10, the synthesizer 10 outputs the PIP data.

The above-described conventional asynchronous screen processing apparatus solves the problem of passing through or vertical salt, but there is a disadvantage that the application can be applied only when the video RAM storing the sub-screen always uses three-field memory.

Accordingly, an object of the present invention is to provide an asynchronous screen processing apparatus and method for preventing distortion of an image between asynchronous screens regardless of the capacity of the video RAM storing the sub screen.

Another object of the present invention is to provide an apparatus and method for preventing a passing throw occurring in a sub picture and a vertical salt occurring between the sub picture and the main picture regardless of the capacity of the video RAM storing the sub picture.

Another object of the present invention is to provide an asynchronous screen processing apparatus and method that operates with compatibility for the double window mode and the PIP mode.

In accordance with the above object, in the present invention, when the memory for storing the sub picture is used as a memory for storing one field (hereinafter, referred to as one field memory), it ignores the passing throw and prevents only line inversion. When used as a memory for storing fields (hereinafter referred to as two-field memory) and a memory for storing three fields (hereinafter referred to as three-field memory), both passthrough and line inversion are prevented.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the same parts or the same components in the drawings use the same reference numerals and the same reference signs wherever possible.

2 is a block diagram of an asynchronous screen processing apparatus according to the present invention.

Referring to FIG. 2, the field memory 32 is actually located outside the predetermined chip and has one field capacity, two field capacity, three field capacity and more according to the capacity required by the circuit. Therefore, in the present invention, image distortion should be processed to prevent image distortion between asynchronous screens regardless of the capacity of the field memory 32.

In order to implement the present invention, first, when the field memory 32 is used with a memory of one field to three fields, a method of preventing passing through or vertical vertical (line inversion) is illustrated in FIGS. 5A to 5C and 6A. Consider it with reference to FIG.

(1) When 1 field memory is used

FIG. 5A shows a screen configuration when one field memory is used, in which odd fields are stored as shown in FIG. 5B and even fields are stored as shown in FIG. 5C.

First, referring to FIG. 6A, when the main field and the subfield have the same shape (odd / even), a passing throw and a vertical salt are generated and a method of correcting the same is explained. If the main field is proceeding as an odd field, the subfield may proceed in the order of odd lines ① ③ and if a passing throw occurs, it may proceed in the order of even lines ⑥⑧. When the main field is proceeding as an even field, the subfield may proceed in an even line ②④, and if a passing throw occurs, it may proceed in an odd line ⑤⑦. Referring to Fig. 6a, the one-frame screen configuration is shown as ①②③④⑥⑤⑧⑦ lines from the top of the screen. That is, the lines ⑥⑤⑧⑦ represent the line reversal phenomenon.

To eliminate this line inversion, change line ⑤⑦ to line ⑦⑨. This is solved by +1 the value of the read row address for reading the field memory.

Next, with reference to FIG. 6b, a description will be given of a passing throw and a vertical salt when the main field and the subfield have different shapes (odd / even numbers), and a method of correcting the same. If the main field is going as an odd field, the subfield will go as an even field. That is, it will proceed in the order of even line ②④. At this time, if a passing throw occurs, it may proceed in the order of odd lines ⑤⑦. And when the main field is progressing as an even field, the subfield will proceed as an odd field. That is, it will proceed in the order of odd lines ①③. At this time, if passing throw occurs, it can proceed to even line ⑥⑧. Referring to Fig. 6b, the one-frame screen configuration is shown as ②①④③⑤⑥⑦⑧ from the top of the screen. In other words, the lines ①①④③ indicate the line reversal phenomenon.

To eliminate this line reversal phenomenon, change ①③ line to ③⑤line. The screen configuration will then appear as ②③④⑤⑤⑥⑦⑧. This is solved by +1 the value of the read row address for reading the field memory.

However, when one memory is used as described above, the passing throw phenomenon caused by the read row address overwriting the write row address cannot be prevented. However, passing through does not have much effect because it is not so noticeable.

(2) When using 2-field memory

Passing throw does not occur if the field memory 32 in Fig. 2 is a memory of two fields. Referring to FIG. 7A, an even region is read when the odd region is being written, and conversely, an odd region is read when the even region is being written. However, line inversion is not prevented with the two-field memory. If the main screen is an even field and the sub screen leads an odd field, the one-frame screen configuration is shown as ②①④③⑥⑤⑧⑦①⑩⑨ as shown in FIG. This shows line inversion on all lines. In order to prevent the line inversion, the lead low address may be +1 when the main is an even field and the sub is an odd field.

(3) When using 3-field memory

In the case of using the three-field memory, passing through the conventional method described above with reference to FIG. 1 prevents the passing throw and line inversion. That is, two previous areas of the area to be written now, that is, one area behind one (area B if the area to be written is A), and one area before the other if the fields are different, that is, two areas above the area to be written (A In the case of an area, the field memory 32 may be controlled to lead to area C).

The asynchronous screen processing apparatus of FIG. 2 according to the present invention, as described above, prevents passthrough (except for one field memory) and vertical salt phenomenon in any of the one to three field memories.

On the other hand, the asynchronous screen processing apparatus of FIG. 2 is configured to select both the double window mode and the PIP mode. The circuit blocks used for the processing of the double window mode and the PIP mode are the horizontal compression unit 14, the vertical decimation unit 22, the multiplexers 26, 30, 34, and the like.

In double window mode, multiplexers 26, 30, and 34 all select input zero. Data on the main screen is compressed horizontally in the horizontal compression unit 14 and then stored in the line memory 28 through the multiplexer 26. It is then applied to the synthesis section 36 through the multiplexer 34. The data of the sub picture is immediately applied to the multiplexer 32 and stored in the field memory 32. Then, the data of the sub picture is ½ horizontally by the read / write addresses of the read row address generator 16 and the write row address generator 24, and is applied to the synthesizer 36. do. Accordingly, the synthesizer 36 synthesizes and outputs the ½ main screen and ½ sub screens.

In PIP mode, multiplexers 26, 30, and 34 all select input stage 1. Data of the main screen is directly applied to the synthesis unit 36 through the multiplexer 34. The data of the sub picture are stored in the line memory 28 through the multiplexer 26 after the lines are vertically interpolated in the decimation unit 14. Thereafter, the data is stored in the field memory 32 through the multiplexer 30, and then predetermined compression (for example, horizontally and vertically) by the read / write addresses of the read row address generator 16 and the write row address generator 24 is performed. Compressed to a length) and applied to the synthesis section 36. Accordingly, the synthesizer 36 synthesizes and outputs a predetermined compressed subscreen on the main screen.

Referring now to FIG. 2, the operation of preventing the passing throw and vertical solute (line inversion) of the present invention will be described in more detail.

The data of the main screen is separated into the main vertical synchronization signal MVS and the main horizontal synchronization signal MHS in the synchronization separator 10, and the main vertical synchronization signal MVS is discriminated in the field discriminator 12 as an odd field or an even field. Similarly, the data of the sub picture is separated into the sub vertical synchronization signal SVS and the sub horizontal synchronization signal SHS in the synchronization separator 20, and the sub vertical synchronization signal SVS is discriminated in the field discriminator 18 as an odd field or an even field.

The write row address generator 24 receives the sub vertical synchronization signal SVS, the sub horizontal synchronization signal SHS, and the subfield discrimination signal SOE to generate the write row address WRA in response to the field memory mode signal Vmode.

The concrete block of the write row address generator 24 is shown in FIG. 3 and includes a write address counter 40, a 2-bit count 42, and a multiplexer 44. As shown in FIG. When the field memory mode signal Vmode is in one field mode (Vmode = 1), the output of the write address counter 40 immediately becomes the write row address WRA, and when the field memory mode signal Vmode is in two field mode (Vmode = 10), it is odd. The write row address WRA is generated so that the even field areas are separately written. When the field memory mode signal Vmode is in the 3-field mode (Vmode = 11), a write row address WRA is generated so that the fields are written in different fields.

Returning to FIG. 2 again, the field memory 32 stores data in the double window mode or data in the PIP mode output from the multiplexer 30 in response to the write row address WRA.

In FIG. 2, the read-low address generator 16 responds to the field memory mode signal Vmode by inputting the main vertical synchronization signal MVS and the main horizontal synchronization signal MHS, the main field discrimination signal MOE, the subfield discrimination signal SOE, and the write row address WRA. To generate the read row address RRA.

A concrete block of the read row address generator 16 is shown in FIG. In the block configuration of Fig. 4, the read control operation is performed when the above-mentioned one-field memory to three-field memory are used.

First, when the field memory 32 of FIG. 2 is a one field memory, as described above, a line reversal phenomenon occurs when the main is an even field (MOE = 1) and the sub is an odd field (SOE = 0). At this time, the operation to prevent the line inversion phenomenon is examined. The field memory mode signal Vmode is 1 in one field memory area. Your multiplexer 80 selects input 1.

When the main field discrimination signal MOE is 1 and the subfield discrimination signal SOE is 0, the output of the AND gate 56 is 1. On the other hand, the main horizontal synchronization signal MHS is counted at the read row address counter 50 and applied to the comparator 52, and the write row address WRA generated from the write row address generator 24 is immediately applied to the comparator 52. Comparator 5 outputs 1 when the value counted in the read row address counter 50 matches the write row address WRA. Thereafter, if the read address count value exceeds the value of the write row address, a passing throw will occur. Therefore, the output of the AND gate 58 is 1. The output of the exclusive oragate 60 is converted from 1 to 0, so a value of +1 is output at line offset 62. The line offset 62 outputs a value of +1 when 0 is input, and outputs nothing when it is not input (if 1 is input). Therefore, the output value of the read-low address counter is added to +1 which is the output of the line offset 62 in the adder 66 and output through the multiplexer 80. The signal output through the multiplexer 80 is the read-low address signal RRA.

Next, when the field memory 32 of FIG. 2 is a two-field memory, it is necessary to prevent line inversion which occurs when the main is an even field (MOE = 1) and the sub is an odd field (SOE = 0). When the memory odd area is written, the even area should be read. When the even area is written, the odd area should be read. The field memory mode signal Vmode is 10 when the field memory 32 is a two field memory. Multiplexer 80 then selects input 2.

The most significant bit MSB of the write low address WRA is inverted by inverter 64 and connected to node 71, and the output value of the read low address counter 50 is connected to node 71 without the most significant bit MSB.

On the other hand, when the main field discrimination signal MOE is 1 and the subfield discrimination signal SOE is 0, the output of the AND gate 68 becomes 0. Therefore, the output value of line offset 70 becomes +1. The data from node 71 is output via multiplexer 80 in addition to the value +1 output from line offset 70 in adder 72. The signal output through the multiplexer 80 is the read-low address signal RRA.

Next, when the field memory 32 of FIG. 2 is a three-field memory, as described above, two previous areas of the area to be written now, that is, one area after the one (B area if the area to be written is A area) and the other fields are different. In this case, the field memory 32 may be controlled so as to lead one area before, that is, two areas behind it (where C is the area to be written).

When the field memory 32 is 3 field memory, the field memory mode signal Vmode is 11. Multiplexer 80 then selects input stage 3.

The output of read low address counter 50 is connected to node 79 with n-1 bits except the most significant bit MSB and the most significant bit MSB-1. On the other hand, when the main field discrimination signal MOE and the subfield discrimination signal SOE are different from each other, the output of the exclusive noar gate 74 is zero. Then, the lower part of the table 78 is enabled and the table value corresponding to the input VCNT value is output. If the main field discrimination signal MOE and the subfield discrimination signal SOE are the same, the output of the exclusive NOR gate 74 becomes 1. Then, the upper portion of the table 78 is enabled and a table value corresponding to the input VCNT value is output.

Data output from Table 78 is connected to node 79 as the most significant bit MSB and the most significant bit immediately lower bit MSB-1. The data of node 74 is output via multiplexer 80. The signal output through the multiplexer 80 is a readout address RRA.

Returning to FIG. 2 again, data stored in the field memory 32 is read by the write row address WRA and applied to the combiner 36. The synthesizing section 36 combines the data in the double window mode or the PIP mode data output from the multiplexer 34 with the output data of the field memory 32 for output.

As described above, the asynchronous screen processing apparatus of the present invention not only prevents image distortion between the asynchronous screens regardless of the capacity of the video RAM storing the sub screen, but also operates with the compatibility of the double window mode and the PIP mode. have.

Claims (2)

An asynchronous screen processing apparatus for processing asynchronous processing between a main screen and a sub-screen of a video, comprising: field memory means for storing at least one field of video data and storing data of the sub-screen under predetermined control; A first synchronous separation and field discrimination means for outputting vertical and horizontal synchronous signals by synchronously separating the data on the screen and discriminating and outputting odd and even fields, and outputting vertical and horizontal synchronous signals by synchronously separating data on the sub-screen. Second synchronous separation and field discrimination means for discriminating and outputting odd and even fields, horizontal compression means for compressing the data of the main screen to be ½ horizontally, vertical interpolation means for vertically interpolating the data of the subscreen, Selects the output of the horizontal compression means in the double window mode in which the main screen and the sub screen occupy ½ of the full screen. First selecting means for selecting an output of the vertical interpolation means in a PIP mode in which a sub-screen of the full screen is occupied at least ½ of the main screen, and line memory means for storing the output of the first selecting means on a line-by-line basis; Second selecting means for selecting data of a sub-screen in the double window mode and selecting an output of the line memory means in the PIP mode, and selecting an output of the line memory means in the double window mode and in the PIP mode. Third selection means for selecting data of the main screen, and the output of the write address counter immediately becomes a write row address when the field memory is in one field mode, and an odd / even field area when the field memory is in two field mode. When the field memory is in the three field mode, the area is changed every field so that the output of the second selecting means is Write address generating means for generating a write row address to be written to the de memory, and a value of the read row address for reading the field memory when the field memory is in an even line of the main field and the subfield is an odd line in one field at a time; +1 to increase the read low address, and when the field memory is 2 fields, the even area is read when the odd area of the field memory is written, and the odd area is read when the even area is written, and the even area of the main field is read. When the line and the subfield are in the odd line, the read low address is increased by +1 for reading the field memory, and when the field memory is 3 or more fields, two previous areas of the write area are generated. Area, that is, the area after one (B area if the area to be written is A area), In other cases, a lead low address generating means for generating a lead address so as to lead an area before one, that is, two areas behind it (or C area if the area to be written is A area), the output of the third selection means, and the false lead. And synthesizing means for synthesizing and outputting data of the sub picture read by the row address. In the asynchronous screen processing method which processes asynchronously between the main screen and the sub screen of an image regardless of the capacity of the field memory of 1 to 3 fields, the vertical and horizontal synchronization signals are output by separating the main screen data synchronously. A first synchronous separation and field discrimination process for discriminating and outputting odd and even fields, and a second synchronous separation and field for outputting vertical and horizontal synchronous signals by synchronizing data on a sub-screen and identifying and outputting odd and even fields. The field memory is arranged so that the output of the write address counter is a write row address when the field memory is in the one field mode, and the odd / even field areas are written in the field memory in the two field mode. In the 3-field mode, a write address that generates a write row address to be written in different fields for each field. When the field memory is one field and the even line of the main field and the subfield is the odd line, the read low address is increased by +1 to generate the read low address. When the field memory is 2 fields, the even area is read when the odd area of the field memory is written, the odd area is read when the even area is written, and the field is the even line of the main field and the subfield is the odd line. The read low address is generated by increasing the value of the read low address for reading a memory, and when the field memory is three or more fields, two previous areas of the area to be written, that is, one area after the one If it is A area, B area. If the fields are different, the area before one, that is, the area after the two (light area is A area). A process of generating a read address that generates a read address to read a C region), and a synthesis process of synthesizing and outputting the data of the main screen and the data of the sub screen read by the read address; Processing unit.