KR970019367A

KR970019367A - Asynchronous Screen Processing Unit and Method

Info

Publication number: KR970019367A
Application number: KR1019950033229A
Authority: KR
Inventors: 백승웅
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1995-09-30
Filing date: 1995-09-30
Publication date: 1997-04-30
Also published as: KR0159432B1

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

영상의 메인화면과 서브화면 간의 비동기를 처리하는 비동기 화면처리 방치 및 방법Asynchronous screen processing method and method for asynchronous processing between main screen and sub screen of video

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

칩 외부 메모리의 용량에 관계없이 비동기 화면간에 생기는 영상의 찌그러짐(라인 역전현상) 및 패싱스로우를 방지하고, 더블윈도우모드와 PIP모드에 대한 호환성을 가지고 동작하는 비동기 화면 처리장치 및 방법을 제공한다.The present invention provides an asynchronous screen processing apparatus and method for preventing image distortion (line reversal) and passing through between asynchronous screens regardless of the capacity of the external memory of the chip, and operating with compatibility with the double window mode and the PIP mode.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

본 발명에서는 본 발명에서는 서브화면을 저장용 메모리가 1필드를 저장하는 메모리로 사용되었을 경우에는 패싱스로우를 무시하고 라인반전현상만 방지하도록 구현하고, 2필드를 저장하는 메모리 및 3필드를 저장하는 메모리로 사용되었을 경우에는 패싱스로우현상과 라인반전 현상 모드를 방지하도록 구현한다.According to the present invention, when the memory for storing a sub picture is used as a memory for storing one field, the present invention implements to ignore the passing throw and prevent only line inversion, and to store a memory for storing two fields and three fields. When used as a memory, it implements to prevent passing throw and line inversion mode.

4. 발명의 중요한 용도4. Important uses of the invention

PIP(Picture In Picture)시스템Picture In Picture System

Description

Asynchronous Screen Processing Unit and Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 비동기 화면 처리장치의 블록 구성도,2 is a block diagram of an asynchronous screen processing apparatus according to the present invention,

제3도는 제2도의 라이트 로우 어드레스(Write row address) 발생부의 구체 블록구성도,FIG. 3 is a detailed block diagram of the write row address generator of FIG.

제4도는 제2도의 리드 로우 어드레스(Read row address) 발생부의 구체 블록 구성도.4 is a detailed block diagram of a read row address generator of FIG.

Claims

An asynchronous screen processing apparatus for processing asynchronous processing between a main screen and a sub screen of an image, the apparatus having a capacity to store at least one field of image data, wherein the sub screen stores data under predetermined control. First synchronous separation and field discrimination means for outputting vertical and horizontal synchronous signals by synchronizing the data and discriminating and outputting odd and even fields; and outputting vertical and horizontal synchronous signals by synchronizing the data on the sub-screen and outputting odd and Second synchronous separation and field discrimination means for discriminating and outputting even fields, and when the field memory is in one field mode, the output of the write address counter becomes a write low address. When the field memory is in 3-field mode, each field is zeroed so that the field areas are separately written. The write address generating means for generating the write row address to be written in different manners and the value of the read row address for reading the field memory when the field memory becomes an even line in the main field and the subfield is an odd line in one field at a time. +1 increase to generate the read low address, when the field memory is 2 fields, the even area is read when the odd area of the field memory is written, and the odd area is read when the even area is written, and the even line is displayed in the main field. When the subfield is in an odd line, the read low address is increased by +1 to generate the read low address. When the field memory is 3 fields or more, two previous areas of the write area are generated. That is, if the field after one (the area to be written is A area, B area) In other cases, the read-lower address generating means for generating a read-out address to read one previous area, i.e., the area behind the two (C area if the area to be written is A area), the data on the main screen and the read-low address And a synthesizing means for synthesizing and reading the data of the read sub-screen.

An asynchronous screen processing apparatus for processing asynchronous processing between a main screen and a sub-screen of a video, comprising: field memory means for storing at least one field of video data and storing data of the sub-screen under predetermined control; A first synchronous separation and field discrimination means for outputting vertical and horizontal synchronous signals by synchronously separating the data on the screen and discriminating and outputting odd and even fields, and outputting vertical and horizontal synchronous signals by synchronously separating data on the sub-screen. Second synchronous separation and field discrimination means for discriminating and outputting odd and even fields, horizontal compression means for compressing the data of the main screen to be 1/2 horizontally, and vertical interpolation means for vertically interpolating the data of the subscreen; Selects the output of the horizontal compression means in the double window mode in which the main screen and the sub screen are each half filled First selecting means for selecting an output of the vertical interpolation means in a PIP mode in which a sub-screen of at least one full screen is occupied at least one half of the main screen, and a line memory storing the output of the first selecting means on a line-by-line basis; Means, second selection means for selecting data of a sub-screen in the double window mode and an output of the line memory means in the PIP mode, and an output of the line memory means in the double window mode and selecting the PIP. Third selection means for selecting data on the main screen in mode and the output of the write address counter immediately becomes a write row address when the field memory is in one field mode, and odd / even fields when the field memory is in two field mode. When the field memory is in the 3-field mode, the area is changed every field so that the output of the second selecting means is changed so that the area is written separately. Write address generating means for generating a write address to be written to a field memory, and a value of a read address for reading the field memory when the field memory is in an even line of the main field and the subfield is an odd line in one field at a time; +1 to increase the read low address, and when the field memory is 2 fields, the even area is read when the odd area of the field memory is written, and the odd area is read when the even area is written, and the even line of the main field is read. When the subfield is in an odd line, the read address is increased by +1 to generate the read address, and when the field memory is 3 fields or more, two previous areas of the write area are written. In other words, if the area after one (the area to be written is A area, B area) In other cases, a lead low address generating means for generating a lead address so as to lead an area before one, that is, two areas behind it (or C area if the area to be written is A area), the output of the third selection means, and the lead. And synthesizing means for synthesizing and outputting the data of the sub picture read by the row address.

In the asynchronous screen processing method that processes asynchronously between the main screen and the sub screen of the image regardless of the capacity of the field memory of 1 to 3 fields, the vertical and horizontal sync signals are output by synchronously separating the main screen data. And a first synchronous separation and field discrimination process for discriminating and outputting even fields and a second synchronous separation and field discrimination process for outputting vertical and horizontal synchronous signals by synchronizing data on a sub-screen and discriminating and outputting odd and even fields. When the field memory is in the 3-field mode, the output of the write address counter becomes the write row address immediately when the field memory is in the 1-field mode. A write address generator that generates a write row address to be written in different fields for each field. If the field memory is 1 field and the even line of the main field and the subfield is an odd line, the read address is increased by +1 to generate the read address, and the field When the memory is 2 fields, the even area of the field memory is read, the even area is read, the odd area is read, the odd area is read, and the field memory is an even line and the subfield is an odd line. The read low address is generated by increasing the value of the read low address for reading by +1, and when the field memory is 3 fields or more, two previous areas of the area to be written, that is, one area after the one (when the area to be written is A area), If the field is different, the area before one, that is, the area after the two (if the area to be written is area A, the area C is zero). ) Asynchronous display processing method characterized by constituted by any synthesis process for synthesizing and outputting the data from the read sub-screen by the data and the read row address of the read row address generated process as a main screen for generating a read row address to read.

※ Note: The disclosure is based on the initial application.