JPH1127599A - Dual-screen display television receiver and overtake control circuit for dual-screen display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the disturbance of a video image due to the phase difference between synchronization signals, to simplify the circuit configuration and to realize a field memory to be not more a two-fields' capacity in the dual-screen display television receiver that displays video signals of two systems at the same time. SOLUTION: This circuit is provided with a line memory 1 that stores a main video signal, a 1st synchronization signal processing circuit 2, a line memory write control circuit 3 that controls writing to the line memory 1, a video output control circuit 4, a field memory 5 that stores a sub video signal, a 2nd synchronization signal processing circuit 6, a field memory write control circuit 7, an overtake control circuit 8, a field memory read control circuit 9, and a changeover 10 that selects a signal outputted from the line memory 1 or from the field memory 5. Thus, the dual-screen television receiver is realized, where a frame memory whose capacity is not more 2 fields with only the control of reading side is employed and video signals of two systems are simultaneously displayed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a two-screen display television for simultaneously displaying two video signals on a 6: 9 liquid crystal monitor and an overtaking control circuit.

[0002]

2. Description of the Related Art In general, the basic structure of a two-screen television is a system using a field memory for a sub-picture signal in order to absorb a synchronization phase difference generated between a main picture signal and a sub-picture signal. It has been published. In the operation, the sub video signal is written into the field memory by synchronization separated from the sub video signal, and read out in synchronization with the synchronization of the main video signal.

[0003] In this case, there are a problem such as flicker occurring when the field relationship between the two screens is different, and a problem that different fields are displayed in the middle of the display screen of the sub-picture signal via the field memory due to the phase difference of synchronization. Two points have been pointed out. On the other hand, various solutions have been proposed, but have four to two fields of field memories to solve the above two problems (Japanese Patent Publication No. Hei 8-294677).
Reference).

[0004] Here, referring to Fig. 22, the operation of a system used to prevent the problem that different fields are displayed in the middle of the display screen of the sub-picture signal via the field memory due to the phase difference of synchronization will be described. Will be described.

First, a main video signal and a main composite synchronization signal generated from the main video signal are input as a main screen. The synchronization signal processing circuit 102 separates the input main composite synchronization signal into a horizontal reference signal and a vertical reference signal. The line memory write control circuit 103 performs write control of the line memory 101 based on the horizontal reference signal output from the synchronization signal processing circuit 102, and writes a main video signal to the line memory 101.

[0006] As the sub-screen, a sub-picture signal and a sub-composite synchronizing signal generated from the sub-picture signal are input. The synchronization signal processing circuit 106 separates the input sub composite synchronization signal into a horizontal reference signal and a vertical reference signal. The field memory write control circuit 107 performs write control of the field memory 105a or 105b using the vertical reference signal and the horizontal reference signal output from the synchronization signal processing circuit 106, and the field memory selection signal output from the overtaking control circuit 108. , Field memory 105a or 1
05b is written in the sub-picture signal.

The video output control circuit 104 performs control for synthesizing the data written in the line memory and the field memory, and the switching circuit 110 switches and outputs the video of the main screen and the video of the sub-screen. On the main screen side, the video output control circuit 104 controls reading of the line memory 101 based on the horizontal reference signal output from the synchronization signal processing circuit 102. On the sub-screen side, the field memory read control circuit 109 controls reading of the field memory 105a or 105b based on the horizontal reference signal output from the synchronization signal processing circuit 102 and the field memory selection signal output from the overtaking control circuit 108. And the switching is performed by the switching circuit 105c.

If the subfield is rewritten to the next field information while the sub-picture is being read from the field memory due to the phase difference of the synchronization, the overwriting is performed by writing to the other field memory twice or more. We are taking measures.

[0009]

However, even in the case of the above configuration, it is necessary to have two or more field memories, and there is a problem that the system cost increases. An object of the present invention is to further reduce the number of fields of a field memory from two to reduce costs and to simplify a circuit configuration.

[0010]

To achieve this object, a dual screen television according to the present invention comprises a read field counter, a read reset timing detection circuit, a write field counter, a write reset timing detection circuit, A write field value delay circuit is used to write and read the field memory by using an overtaking processing circuit that delays the read address of the frame memory with respect to the write address by a predetermined time.

With this configuration, the problem that different fields are displayed in the middle of a sub-picture which occurs when the phase difference between the two video signals is different can be solved by using a field memory of less than two fields. .

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is directed to a dual screen television for displaying a main video signal and a sub video signal side by side at the same time, and a line memory for storing the main video signal. A first synchronization signal processing circuit for outputting a horizontal reference signal, a vertical reference signal, and a field discrimination signal of the main video signal based on a main composite synchronization signal separated from the main video signal, and the first synchronization signal processing A line memory write control circuit that controls writing of the line memory based on a horizontal reference signal output from the circuit,
A video output control circuit that controls reading of the line memory based on a horizontal reference signal output from the first synchronization signal processing circuit, a field memory that stores the sub-video signal, and a video signal that is separated from the sub-video signal A second synchronization signal processing circuit for outputting a horizontal reference signal, a vertical reference signal, and a field discrimination signal of the sub video signal based on the sub composite synchronization signal; and a horizontal reference signal output from the second synchronization signal processing circuit. A field memory write control circuit for controlling writing in the field memory based on a signal, a vertical reference signal, and a field discrimination signal; and a horizontal output from the first and second synchronization signal processing circuits. Detecting a temporal relationship between the two video signals based on a reference signal, a vertical reference signal, and a field determination signal; An overtaking control circuit that outputs a read permission signal of a read address, a field memory read control circuit that controls reading of the field memory based on a read permission signal of the read address output from the overtaking control circuit, and the video output control. A switching circuit for switching a signal output from the line memory and the field memory based on a switching signal output from a circuit,
This has the effect of realizing a system for simultaneously displaying two systems of video signals only by controlling the reading side of the frame memory.

According to a second aspect of the present invention, there is provided the dual screen television according to the first aspect, wherein a read field counter, a read reset timing detection circuit, a write field counter, and a write reset timing detection are provided. A circuit and a write field value delay circuit are used to delay a read address of a frame memory with respect to a write address for a fixed time, and simultaneously display two video signals in a field memory of less than two fields. It has the effect of realizing a system that performs

According to a third aspect of the present invention, there is provided the dual-screen display television according to the first aspect, wherein a read field counter, a read reset timing detection circuit, a write field counter, and a write reset timing detection are provided. Circuit, a write field value delay circuit, and a field period discrimination circuit, and automatically detects the temporal relationship between the two video signals, thereby automatically delaying the read address of the frame memory with respect to the write address. And has the effect of reducing the overtaking margin of the field memory.

According to a fourth aspect of the present invention, there is provided the dual-screen display television according to the first aspect, wherein a read field counter, a read reset timing detection circuit, a write field counter, and a write reset timing detection are provided. A circuit, a write field value delay circuit, a field cycle discrimination circuit, and a field phase difference discrimination circuit are used, and the overtaking control of the frame memory is temporarily stopped based on the temporal relationship between the two video signals. This has the effect of improving the transient characteristics of the field memory when passing.

According to a fifth aspect of the present invention, there is provided the dual-screen display television according to the first aspect, wherein a read field counter, a read reset timing detection circuit, a write field counter, and a write reset timing detection are provided. A horizontal reference signal, a vertical reference signal, and a field determination signal obtained from the first or second synchronization signal processing circuit using a circuit, a write field value delay circuit, a field cycle determination circuit, and a field phase difference determination circuit. Thus, the overtaking control is automatically suspended when an abnormal state of the synchronization signal is detected, and has an effect of improving the system margin when an abnormal signal is input.

An embodiment of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 is a block diagram of the present invention. As an example of the present invention, an operation of outputting a main video signal to a left half and a sub-video signal to a right half will be described. explain. In order to specifically explain, the two-screen display device is a liquid crystal display device corresponding to 480 pixels × 234 lines.

First, a main video signal and a main composite synchronization signal generated from the main video signal are input to the left screen. The synchronization signal processing circuit 2 separates the input main composite synchronization signal into a horizontal reference signal, a vertical reference signal, and a field determination signal. The line memory write control circuit 3 performs write control of the line memory 1 based on the horizontal reference signal output from the synchronization signal processing circuit 2,
The main video signal converted into pixels is written in the line memory 1.

A sub-picture signal and a sub-composite synchronizing signal generated from the sub-picture signal are input to the right screen. The synchronizing signal processing circuit 6 separates the input sub-composite synchronizing signal into a horizontal reference signal and a vertical reference signal from the field determination signal. The field memory write control circuit 7 controls the writing of the field memory 5 using the vertical reference signal and the horizontal reference signal output from the synchronization signal processing circuit 6 and the write address reset permission signal output from the overtaking control circuit 8.

At this time, a sub-picture signal which has been subjected to horizontal interpolation processing and vertical interpolation processing and converted into 240 pixels × 234 lines is written in the field memory 5. The video output control circuit 4 performs control for synthesizing data written in the line memory and the field memory.

For the left half data, the read control of the line memory 1 is performed by the video output control circuit 4 on the basis of the horizontal reference signal output from the synchronizing signal processing circuit 2 in the 1 / 2H section.

The right half of the data is read by the field memory read control circuit 9 based on the horizontal reference signal output from the synchronizing signal processing circuit 2 and the read address reset enable signal output from the overtaking control circuit 8. Is performed in the 1 / 2H section.

The switching circuit 10 switches and outputs the left half of the 1H video section so as to be output from the line memory and the right half is output from the field memory.

Next, the operation of the field memory control system will be described in detail with reference to the drawings.

First, the configuration of the field memory will be described. In this embodiment, a 1M field memory is used.

[0026]

[Table 1]

As shown in the figure, the block is divided into eight blocks and used. At this time, the data of one block is 16 per pixel.
As pixel data, 240 pixels * 34 lines are assigned. In addition, since data of one field is realized by 234 lines or more, 7 blocks of 238 lines are allocated. However, the size of the field memory increases or decreases depending on the number of pixels, but may be configured with less than two fields.

Next, the circuit configuration will be described with reference to FIGS. Overtaking control circuit 8 shown in detail in FIG.
Uses a horizontal reference signal and a vertical reference signal from the synchronization signal processing circuit 6 and a vertical reference signal from the synchronization signal processing circuit 2. The write field counter 82 counts up on a field-by-field basis by the sub-picture signal vertical reference signal. Here, in the present embodiment, 8 fields are set to 1
To control in cycles, this field counter is set to 0
To 7 cyclic counters.

Write reset timing detection circuit 83
3 includes a decode circuit 83a as shown in FIG. 3, and uses the count value of the write field counter 82 to output a write address reset permission signal when the count value is 0. As shown in FIG. 4, the write field value delay circuit 84a includes a line counter 841, a decode circuit 842, and a latch circuit 843. The line counter 841 resets with the sub-picture signal vertical reference signal, counts up with the horizontal reference signal, and decodes a constant value, 16 in this embodiment, and outputs a pulse by the decoding circuit 842. The latch circuit 843 latches the field count value at the timing of the latch pulse and outputs it as a delayed field count value.

Next, the read field counter 80
Counts up for each field according to the main video signal vertical reference signal. Here, in the present embodiment, 8
In order to control the field in one cycle, the field counter is composed of cyclic counters from 0 to 7. The read reset timing detection circuit 81 includes a decode circuit 81a, an edge cutout circuit 81b, and a decode circuit 81c as shown in FIG. Decode circuit 81a
Decodes the field count value 0 of the readout field counter 80 and cuts out the leading edge by the edge cutout circuit 81b. The decode circuit 81c latches the delay field value by the pulse generated by the edge cutout circuit 81b, and outputs a read address reset enable signal when 0 is decoded.

The field memory write control circuit 7
As shown in FIG. 6, an address counter 70, a decode circuit 71, an AND circuit 72, and an OR circuit 73 are provided. The logical product circuit 72 calculates the logical product of the vertical reference signal and the horizontal reference signal output from the synchronization signal processing circuit 6 and the write address reset permission signal output from the overtaking control circuit 8, and the decode circuit 71 stores the logical product of the field memory. An OR operation is performed with a signal obtained by decoding the final address, and the address counter 70 is reset. After resetting, the address counter 70 counts up the address in each cycle of writing to the field memory, outputs an address signal, and performs writing to the field memory.

The field memory read control circuit 9 shown in FIG. 7 comprises an address counter 90, a decode circuit 91, an AND circuit 92, and an OR circuit 93. The AND circuit 92 calculates the logical product of the vertical reference signal and the horizontal reference signal output from the synchronization signal processing circuit 2 and the read address reset enable signal output from the overtaking control circuit 8, and the decode circuit 91 stores the logical product of the field memory. An OR operation is performed with a signal obtained by decoding the final address, and the address counter 90 is reset. After reset, the address counter 90 counts up the address and outputs the address in each cycle of writing to the field memory, and the address is written to the field memory.

Next, the circuit operation will be described in detail with reference to the timing charts of FIGS. FIG. 8 is a timing chart when a video signal having the same period is input to two input signals, and the operation will be described.

First, the write field value (b) circulates from 0 to 7 according to the sub-video signal vertical reference signal (a).
Field memory write address reset signal (c)
Is output by detecting the last address of the write address counted up in the field memory write section (d). At this time, the write address corresponding to each field count value is the field counter 0 as shown in the field memory write block (e).
Sometimes, 7 blocks are used in the order of 1 to 7 blocks, and in the case of 1, 8 to 6 blocks.

Therefore, the writing of the eighth field is performed in
By performing the processing for eight blocks, one cycle is completed.
The write field value (b) is output to the reading side when the writing of the ブ ロ ッ ク block is completed. This value becomes the delay field value (f). On the other hand, the read field value (h) cycles from 0 to 7 by the main video signal vertical reference signal (g). The field memory read address reset signal (i) outputs the last address of the read address counted up in the field memory read section (j) upon detection. At this time, as shown in the field memory read block (k), the address at which reading is performed in accordance with each field count value is 1 to 7 blocks when the field counter is 0.
At the time of 1, 7 blocks are used in the order of 8 to 6 blocks.

Therefore, the reading of the eighth field is performed in two to
By starting from eight blocks, one cycle is completed. Further, the read side sets the delay field value (f) to 0.
, The read field value (h) is reset to 0, and blocks based on the field count value (h) are sequentially read. However, in this case, since the field memory read address reset signal (i) is the same as the signal output after detecting the last address, it does not affect the operation. Therefore, by the above processing, the master image via the line memory and the slave image via the field memory are combined and output.

Next, FIG. 9 shows a timing chart in the case where the main video cycle is longer than the sub-video cycle in two input signals, and the operation will be described. The control on the writing side is the same as the operation described above, and will not be described.

On the read side, in normal timing, the field memory read address reset signal (i) is output with the main video signal vertical reference signal (g) input when the delay field count value (f) is 0.

Thereafter, when the reading of data for eight fields is completed, a case may occur where the delay field value (f) has not returned to 0. This is so-called overtaking timing. At this time, the read-side field memory is reset by the last address, and the read cycle is automatically performed from one block.

However, at the time when the delay field value (f) outputs 0, since 1/2 block of data has been written in the actual memory, the read is delayed from 0H to 16H with respect to the write. If the condition is met, it is performed normally. Further, when the next main video signal vertical reference signal (g) is input, the delay field value indicates 0,
Field memory read address reset signal (i)
Resets the field memory forcibly.

At this time, the writing side is writing the eighth block, and the write data in the zeroth field of the first to seventh blocks has not been changed. Therefore, it is possible to read again from the 0th block on the reading side, and after displaying the same field twice, the cyclic operation is performed again.
By repeating the above operation, it is possible to absorb the period difference between the input signals of the two systems and display normally.

Here, the normal reset state of the readout field value will be described in detail with reference to FIG. 11, and the reset state of the readout field value at the time of the overtaking timing will be described in more detail with reference to FIG.

In FIG. 11, the write field value (e) is cleared to 0 by the sub-picture signal vertical reference signal (a). The delay reference signal (f) is output when a constant value, for example, 17 is detected after the write line counter value (c) is counted up by the sub-picture signal horizontal reference signal (b). At this timing, the delay field value (g) is updated.

Thereafter, upon detection of the main video signal vertical reference signal (h), the read line counter value of the field value 0 is counted up and read. On the other hand, in FIG. 12, the write field value (e) is cleared to 0 by the sub-video signal vertical reference signal (a). The delay reference signal (f) is output when a constant value, for example, 17 is detected after the write line counter value (c) is counted up by the sub-picture signal horizontal reference signal (b).

At this timing, the delay field value (g) is updated. Where the delay field value (g)
Is not used, the main video signal vertical reference signal (h) is detected before the delay reference signal, so that the zero field that should be read cannot be read. However, by using the delay field value (g), it is possible to use the read data of the normal field value 0 as the actual read data.

Next, FIG. 10 shows a timing chart in the case where the main video cycle is shorter than the sub-video cycle in two input signals, and the operation will be described. The control on the writing side is the same as the operation described above, and will not be described.

On the read side, in normal timing, the field memory read address reset signal (i) is output with the main video signal vertical reference signal (g) input when the delay field count value (f) is 0. After that, the delay field value (f) may return to 0 before the reading of the data for eight fields is completed. This is the so-called reverse overtaking timing.

At this time, since the read address is reset by the read address reset signal (i) of the field memory, the reading of the data in the seventh field written in the second to eighth blocks is omitted.
The next field data is written in the block. Therefore, reading can be performed from the 0th block on the reading side, display for one field is omitted, and the cyclic operation is performed again. By repeating the above operation,
It is possible to absorb the period difference between the input signals of the two systems and display normally.

As described above, by using the present embodiment, the overtaking process is performed under the control of the reading side, the capacity of the field memory is realized with less than two fields, and the two-screen display process can be performed with a simple configuration.

(Embodiment 2) FIG. 13 is a block diagram of an overtaking control circuit according to the present invention. The operation as a two-screen television using the overtaking control circuit shown in FIG.
The description is omitted because it is the same as that of the first embodiment, and only the overtaking control operation, which is a feature of the present invention, will be described.

An overtaking control circuit 8 whose details are shown in FIG.
Performs control using a sub video signal horizontal reference signal, a sub video signal vertical reference signal, and a main video signal vertical reference signal. The write field counter 82 counts up on a field-by-field basis by the sub-picture signal vertical reference signal. The write reset timing detection circuit 83 uses the count value of the write field counter 82 to set the count value to 0.
The write address reset signal is output at the time of. As shown in FIG. 14, the write field value delay circuit 84b includes a line counter 841, a decode circuit 844, and a latch circuit 843. After the line counter 841 is reset by the sub-picture signal vertical reference signal, it counts up by the horizontal reference signal, and the decode circuit 844 switches the decode value according to the phase relationship detection signal detected by the field period determination circuit 85 and outputs a pulse. . The latch circuit 843 latches the field count value at the timing of the latch pulse and outputs it as a delayed field count value.

The read field counter 80
Counts up for each field according to the main video signal vertical reference signal. The read reset timing detection circuit 81 latches the delay field counter value and outputs a read address reset signal when 0 is decoded.

Here, the operation of the field period discriminating circuit 85 will be described in detail with reference to FIG. First, a delay field value is input to the field cycle determination circuit 85 from the write field value delay circuit 84b. This signal is based on the main video signal vertical reference signal 85a, 85a.
The latch is performed by b, and the difference between the two fields is obtained by the subtractor 85c. By decoding this value by the decoding circuit 85d, a period difference between the main video signal and the sub video signal is obtained.

This operation will be further described with reference to the timing charts of FIGS. FIG. 16 is a timing chart in the case where the main video cycle is shorter than the sub-video cycle in two input signals.

First, the writing side creates a writing field value (b) and a delay field value (c) based on the sub-picture signal vertical reference signal (a). The difference between the read field value (e) latched by the main video signal vertical reference signal (d) and the read field value (f) obtained by latching the read field value (e) again is calculated. This value is the cycle information (h) between the fields, and the difference value when overtaking occurs is 0, and 1 (the main video cycle is shorter than the sub-video cycle) is output as the cycle information in this case.

On the other hand, FIG. 17 is a timing chart in the case where the main video cycle is shorter than the sub-video cycle in the two input signals, and the difference value when an overtaking occurs is -6.
In this case, 2 (the main video cycle is longer than the sub video cycle) is output as cycle information. If this is used and the delay value after the period information is detected is increased or decreased, the margin at the time of passing is increased.

As described above, by using the present embodiment, it is possible to reduce the overtaking margin capacity to half the capacity of the field memory of the first embodiment. In addition, when having the same capacity, the margin for overtaking increases.

(Embodiment 3) FIG. 18 is a block diagram of an overtaking control circuit of the present invention. The operation as a two-screen television using the overtaking control circuit shown in FIG.
The description is omitted because it is the same as that of the first embodiment, and only the overtaking control operation, which is a feature of the present invention, will be described.

The overtaking control circuit 8 shown in detail in FIG.
Performs control using a sub video signal horizontal reference signal, a sub video signal vertical reference signal, and a main video signal vertical reference signal. The write field counter 82 counts up on a field-by-field basis by the sub-picture signal vertical reference signal. The write reset timing detection circuit 83 uses the count value of the write field counter 82 to set the count value to 0.
The write address reset signal is output at the time of. The write field value delay circuit 84b switches the delay amount based on the cycle information detected by the field cycle determination circuit 85, and outputs it as a delay field count value. The readout field counter 80 counts up for each field based on the main video signal vertical reference signal. The read reset timing detection circuit 87 stops outputting the address reset signal based on the detection information of the field phase difference determination circuit 86.

The operation of the field phase difference discriminating circuit 86 will now be described in detail with reference to FIG. First, a delay field value is input to the field phase difference determination circuit 86 from the write field value delay circuit 84b.
This signal is latched at 86c by the main video signal vertical reference signal, and the difference between 86d and 86e latched again after a delay of Z clocks (Z = 4 in this embodiment) in a subtraction period 86f. From this value, it can be detected that the vehicle is near the switching of the overtaking timing. Therefore, if the phase difference is within a certain range, the overtaking process should be temporarily interrupted so that the transient state of the overtaking process due to jitter does not occur, and the actual process should be performed when a sufficient phase difference occurs. Becomes possible.

This operation will be further described with reference to the timing chart of FIG. FIG. 20 is a timing chart in the vicinity of performing the overtaking process. First, the main video signal vertical reference signal (b) is converted to a read reference clock (a).
Is a delayed pulse (c) delayed by the Z clock (Z = 4 in the present embodiment). The delay field value (d) is temporarily latched by the latch 86c based on the main video signal vertical reference signal (b), and the field value (e) is obtained.

Further, the field value (f) and the field value (g) are obtained from the delay pulse (c), and the difference between them is obtained. Here, the difference value (h) when jitter can occur is 7, and only in this case, the overtaking process is stopped.

As described above, by using the present embodiment, when jitter occurs, it is conceivable that repeated writing and skipping of the same field may be repeated every eight fields, but the synchronization position exists nearby. In such a case, it is possible to control the overtaking process to be stopped and to perform the overtaking process only when the phase condition does not cause repetition, so that the transient characteristics of the field memory at the time of overtaking are improved.

(Embodiment 4) FIG. 21 is a block diagram of an overtaking control circuit according to the present invention. The operation as a two-screen television using the overtaking control circuit shown in FIG.
The description is omitted because it is the same as that of the first embodiment, and only the overtaking control operation, which is a feature of the present invention, will be described.

The overtaking control circuit shown in FIG. 21 is different from the third embodiment in that when an abnormal mode detection signal is detected,
The overtaking control is stopped by constantly switching and outputting the switching circuits 88 and 89 to the reset permission signal.

This operation assumes that the number of horizontal scanning lines per field is changed at the time of special reproduction of a VTR or the like. In this case, a different field is output in the middle of the field. However, since an incomplete video signal is originally output by a noise bar or the like, a step between the fields can be ignored. Thus, the system can be configured without having to unnecessarily increase the margin of the phase difference.

As described above, by using this embodiment, even when an abnormal signal is input in a system with a reduced memory capacity, abnormal display in the V direction is prevented, and the margin of the system is improved.

[0068]

As described above, according to the present invention, by setting the margin of the system, it is possible to realize a two-screen television by setting the capacity of the field memory to 1 field + α (for example, 8/7 fields). can get.

[Brief description of the drawings]

FIG. 1 is a configuration diagram according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of the overtaking control circuit.

FIG. 3 is a configuration diagram of the write reset timing detection circuit;

FIG. 4 is a configuration diagram of the write field value delay circuit;

FIG. 5 is a configuration diagram of the read reset timing detection circuit.

FIG. 6 is a configuration diagram of the field memory write control circuit.

FIG. 7 is a configuration diagram of the field memory read control circuit.

FIG. 8 is an explanatory diagram for explaining an operation of the overtaking process;

FIG. 9 is an explanatory diagram for explaining an operation of the overtaking process.

FIG. 10 is an explanatory diagram for explaining an operation of the overtaking process;

FIG. 11 is an explanatory diagram for explaining an operation of the overtaking process;

FIG. 12 is an explanatory diagram for explaining an operation of the overtaking process;

FIG. 13 is a configuration diagram of an overtaking control circuit according to the second embodiment of the present invention;

FIG. 14 is a configuration diagram of the write field value delay circuit.

FIG. 15 is a configuration diagram of the write field cycle determination circuit.

FIG. 16 is an explanatory diagram for explaining the operation of the field period discriminating circuit;

FIG. 17 is an explanatory diagram for explaining the operation of the field period determination circuit;

FIG. 18 is a configuration diagram of an overtaking control circuit according to the third embodiment of the present invention.

FIG. 19 is a configuration diagram of the write field phase difference determination circuit.

FIG. 20 is an explanatory diagram for explaining the operation of the field phase difference discriminating circuit;

FIG. 21 is a configuration diagram of an overtaking control circuit according to a fourth embodiment of the present invention.

FIG. 22 is a configuration diagram in a conventional embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Line memory 2 Synchronous signal processing circuit 3 Line memory write control circuit 4 Video output control circuit 5 Field memory 6 Synchronous signal processing circuit 7 Field memory write control circuit 8 Overtaking control circuit 9 Field memory read control circuit 10 Switching circuit 80 Read field counter 81 Read reset timing detection circuit 82 Write field counter 83 Write reset timing detection circuit 84 Write field value delay circuit 85 Field period discrimination circuit 86 Field phase difference discrimination circuit 87 Read reset timing detection circuit 88 Switching circuit 89 Switching circuit

Continued on the front page (72) Inventor Takahiro Kobayashi 1006 Kazuma Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd.

Claims (5)

[Claims] 1. A two-screen display television for displaying a main video signal and a sub video signal side by side at the same time on a left and right side, wherein a line memory for storing the main video signal and a main composite synchronization signal separated from the main video signal are used as references. A first synchronization signal processing circuit for outputting a horizontal reference signal, a vertical reference signal, and a field discrimination signal of the main video signal, and the line memory based on a horizontal reference signal output from the first synchronization signal processing circuit. A line memory write control circuit for controlling writing of data, a video output control circuit for controlling reading of the line memory based on a horizontal reference signal output from the first synchronization signal processing circuit, and storing the sub-video signal And a horizontal reference signal and a vertical reference signal of the sub video signal based on a sub composite synchronization signal separated from the sub video signal. A second synchronization signal processing circuit for outputting a field discrimination signal, and controlling writing of the field memory based on a horizontal reference signal, a vertical reference signal, and a field discrimination signal output from the second synchronization signal processing circuit. A two-system video signal based on a horizontal reference signal, a vertical reference signal, and a field discrimination signal output from a field memory write control circuit, and a first synchronization signal processing circuit and a second synchronization signal processing circuit. An overtaking control circuit that detects a temporal relationship between the two, and outputs a reset permission signal of a read address of the field memory; and reads out the field memory based on a reset permission signal of a read address output from the overtaking control circuit. A field memory read control circuit to be controlled, and a switching signal output from the video output control circuit. 2 screen display television, characterized in that a switching circuit for switching signals output from said line memory to reference the field memory. 2. A two-screen display television according to claim 1, further comprising a read field counter, a read reset timing detection circuit, a write field counter, a write reset timing detection circuit, and a write field value delay circuit. An overtaking control circuit, wherein a read address of a frame memory is delayed for a predetermined time with respect to a write address. 3. The dual-screen display television according to claim 1, wherein a read field counter, a read reset timing detection circuit, a write field counter, a write reset timing detection circuit, a write field value delay circuit, Overtaking control using a field period discriminating circuit and automatically switching a time for delaying a read address of a frame memory with respect to a write address by detecting a temporal relationship between two video signals. circuit. 4. A dual-screen display television according to claim 1, wherein: a read field counter, a read reset timing detection circuit, a write field counter, a write reset timing detection circuit, a write field value delay circuit, An overtaking control circuit using a field period discriminating circuit and a field phase difference discriminating circuit, and temporarily stopping overtaking control of a frame memory based on a temporal relationship between two video signals. 5. The dual-screen display television according to claim 1, wherein a read field counter, a read reset timing detection circuit, a write field counter, a write reset timing detection circuit, a write field value delay circuit, Using a field period discriminating circuit and a field phase difference discriminating circuit,
Alternatively, the overtaking control is automatically suspended when an invalid state of the synchronization signal is detected based on the horizontal reference signal, the vertical reference signal, and the field determination signal obtained from the second synchronization signal processing circuit. Overtaking control circuit.