KR0157547B1 - Device for restoring the sync. signal of transprot demultiplexer - Google Patents

Abstract

The present invention relates to a synchronous recovery apparatus of a transport demultiplexer which is capable of synchronizing a PCR data embedded in a bit string in a transport demultiplexer for separating a transport bit string according to the MPEG2 standard into video and audio. The PCR data is compared with the STC data generated at the receiving side, and the pulse width modulation is performed by the error data corresponding to the difference. Accordingly, as the oscillation frequency is variable, the STC data is regenerated, thereby synchronizing with the PCR data that changes frequently.

Description

Synchronous Recovery Unit for Transport Demutipxer

1 is a data format diagram showing the structure of a transport packet.

2 is a block diagram of a transport demultiplexer to which the synchronous recovery device of the present invention is applied.

3 is a detailed configuration diagram of a synchronous recovery device according to the present invention.

4 is a conceptual diagram showing the temporal relationship between the PCR data of the transmitting side and the STC data of the receiving side according to the present invention.

5 is a graph showing an operating range according to the present invention.

6A and 6B are waveform diagrams for index pulses and bit pulses for generating pulse width modulated signals in the pulse width modulator of the present invention.

7 is a waveform diagram showing the correlation between the error data of the comparison unit and the pulse width modulation data of the pulse width modulation unit according to the present invention.

* Explanation of symbols for main parts of the drawings

10: comparison unit 20: pulse width modulator

30: loop filter 40: VCO

50: STC generator 51: the first comparator

52: second comparator 53: 1D flip flop

54: 2D flip-flop 55: Error generating unit

56: first counter 57: detection unit

58: second counter 61: second pulse width modulator

62: first pulse width modulator 63: fifth counter

64: fourth counter 65: fourth comparator

66: third comparator 67: third counter

The present invention compares the PCR (Program Clock Reference) data added to the transport bit string transmitted from the transmitting side with the STC data obtained from the system clock at the receiving side according to the recommendation of MPEG2, and compares the system clock by the error data corresponding to the difference. The present invention relates to a synchronization recovery device of a Transport Demutiflexer that allows synchronization by varying.

Recently, the necessity of standardization of international data transmission standard of digital data has emerged for the smooth transmission and sharing of information between different devices. H.261 is mainly used for multimedia communication terminals for video telephony and conference system. JPEG, which targets still image processing such as graphics, is actively used not only for storing and transmitting still images but also for storing and editing moving images in broadcasting stations or for electronic cameras. In addition, MPEG1 standardized in 1993 is used to compress and restore video and audio signals, and is used in CD-ROM, which is recently gaining popularity, and the expanded MPEG2 is a digital satellite broadcast that has recently gained worldwide attention. The trend is to adopt compression algorithms such as digital cable TV and high definition TV.

The multiplexing method according to MPEG2 video and audio compression algorithm is briefly described. To store audio and video data and other auxiliary data encoded in the form of bit strings in digital media or to transmit them through cable, network, or satellite, these bit strings must be packetized and multiplexed. In detail, each elementary stream (elementary stream (audio, video, data)) is packetized packetized elementary stream (PES) and one of the program bit stream (Program stream) or transport bit stream (Transport stream) It is selected to use. The program bit string is basically a standard for use in an environment where there is little error in transmission, such as data storage, and is very similar to the form of a bit string based on MPEG1. On the other hand, the transport bit string is used in an error-prone environment, that is, a transmission or a noisy over a network or satellite.

Therefore, it is possible to transmit by adding a parity bit to the transport bit string. That is, the transport bit string is used when a bit string is transmitted through a medium that is likely to cause an error. The transport bit string is used by fixing a packet size so that parity information can be added for error correction. This packet size is set to 188 bytes, which is determined by considering the following two factors. First, to make it easier to use the RS coding technique, which is currently used error correction technique, the packet has a size of 255 bytes or less. Second, this transport packet can be easily applied to ATM networks. That is, the size of the ATM cell is 53 bytes, which is to be inserted into 48 bytes except for the header five bytes. At this time, 1 byte is required for the additional adaptation field, so 188 bytes selected from the remaining integer number of 47 bytes are determined to be the most appropriate.

1 is a data format diagram showing the structure of a transport packet. As shown in the figure, a packet header has a sync word of one byte defined first, a transprot_error_indicator indicating whether an error has occurred in the packet, a transport_priority for determining the priority of the packet, and a payload scrambling. A number of parameters for compression and multiplexing are inserted, such as transport_scrambling_control, which indicates whether this is done, and continuity_counter, which is incremented from 0 to 15 to see if a packet loss has occurred. Among them, adaptation field existing after header is mainly used when inserting stuffing byte or transmitting PCR (Program Clock Reference). In this case, the PCR is used for the same purpose as the SCR (System Clock Reference) of the program bit string, and the time interval between two consecutive PCRs is defined so as not to exceed 0.1 second.

As shown in FIG. 1, this PCR data is composed of 42 bits. The system clock on the transmitting side is counted and the counting value is added to the bit string and sent.

Therefore, the transport demultiplexer that separates the multiplexed bit streams into video and audio at the receiving side compares the PCR data added at the transmitting side with the STC (System Time Clock) data generated by the system clock (27MHz). Synchronization is restored by varying the system clock (27 MHz) according to the degree of difference.

An object of the present invention is to provide a synchronous recovery apparatus of a transport demultiplexer which is capable of synchronizing with PCR data embedded in a bit string in a transport demultiplexer for separating a multiplexed bit string transmitted through a transmission medium into an image and an audio signal.

In order to achieve the above object, the present invention receives a transport bit string according to the MPEG2 standard, and separates the same number of bits according to PCR data of a predetermined bit added to the bit string to separate and detect a desired video and audio bit string. In the synchronous recovery apparatus of a transport demultiplexer for varying the STC data to restore synchronization, the PCR data and the STC data are respectively input and compared with each other to compare whether they have the same data value, and then output error data corresponding to the difference between the two data. A pulse width modulator coupled to a comparator and an output terminal of the comparator, and connected to an output terminal of the pulse width modulator for receiving a pulse width modulated according to a pulse type of the error data and receiving the error data; A loop filter for receiving data and filtering a predetermined band, and connected to an output terminal of the loop filter, The oscillation frequency is varied according to the signal filtered by the loop filter to be used as a clock and is connected to the output terminal of the VCO and the VCO. The system clock is counted using the oscillation frequency applied from the VCO as the system clock. In addition, the counted STC data is achieved by the STC generation unit for feeding back to the comparison unit.

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a transport demultiplexer to which the synchronous recovery device of the present invention is applied. The transport demultiplexer on the receiving side receives the multiplexed transport bit stream, divides it into an image bit stream and an audio bit stream, and outputs the PCR data. The PCR data added to the transport bit stream is applied to the comparator 10. The comparison unit 10 compares the PCR data with the feedback input STC data and outputs error data corresponding to the difference to the pulse width modulator 20 at the rear stage. The error data is pulse width modulated by the pulse width modulator 20 according to the pulse state of the error data, that is, the error value, and then applied to the loop filter 30. The modulated error data is filtered over the effective band by the loop filter 30 and then applied to the VCO 40 as an adjustment signal for varying the oscillation frequency of the VCO 40. Accordingly, the VCO 40 varies the oscillation frequency according to the adjustment signal. That is, the error data serves as an adjustment signal for varying the oscillation frequency output from the VCO 40, and the oscillation frequency of the VCO 40 is increased or decreased according to the pulse state of the error data. This is for synchronizing the STC data with the PCR data of the transmitting side. The oscillation frequency is applied to the STC generating unit 50 as a system clock, and the regenerated STC data is fed back into the comparator 10.

The synchronous recovery operation of such a transport demultiplexer will be described sequentially. First, an operation in which the comparison unit 10 compares PCR data and STC data and outputs error data will be described with reference to FIG. 3. 3A is a detailed configuration diagram of the synchronous recovery device of the present invention. As shown, the present invention includes a comparator 10 and an STC generator 50.

First, the STC generator 50 is composed of first and second counters 56 and 58 and a detector 57 that receive and count an oscillation frequency applied from the VCO 40, that is, a system clock (27 MHz). . The second counter 58 is a 9-bit counter and when the enable signal of the high state is applied to the terminal CT1, the system clock is applied through the terminal CK1 to start counting, and the counting value is input through the terminal Qout. Output Meanwhile, when the counting value of the second counter 58 reaches 299, the detector 57 receiving one end of the output data of the second counter 58 sends a reset signal to the terminal R1 of the second counter 56. At the same time, a carry generation signal is output to the terminal CK2 of the first counter 56. Of course, the output data of the second counter 58, that is, the lower STC data, is applied to the first comparator 51. In addition, when a first load signal having a low state is applied to the terminal L1, the second counter 58 receives a first initial value output from a microcomputer (not shown) through the terminal Qin. This is to set the lower PCR data among the previous PCR data to the initial value under the control of the microcomputer since the error interval between the PCR data of the transmitting side and the STC data of the receiving side is large.

In addition, the first counter 56 is a 33-bit counter and performs a counting operation while an enable signal in a high state is applied through the terminal CT2. That is, whenever the carry generation signal is applied from the detector 57 through the terminal CK2, the carry generation count is counted, and the counting value (upper STC data) is output to the second comparator 52 through the terminal Qout. do. Of course, when the reset signal supplied from the microcomputer (not shown) is applied to the terminal R2, the first counter 56 also sets the counting value to 0, and the second load of the low state in the terminal L2 is set. When the signal is applied, the second initial value is applied through the terminal Qin, which is the same as that of the second counter 58 to set the upper PCR data among the previous PCR data as the initial value.

Meanwhile, the comparison unit 10 receives the PCR data and the STC data, respectively, and outputs first and second comparators 51 and 52 for outputting subtraction data corresponding to the difference, and first and second D flips connected to the output terminals. It consists of a flop 53, 54 and an error generating unit 55 connected to the rear end thereof. First, the 42-bit PCR data detected by the transport multiplexer is separately applied to the first and second comparators 51 and 52. The 9-bit PCR data including the least significant bit (LSB) in the first comparator 51 is applied. While the lower PCR data is input, the remaining 33 bits of the upper PCR data such as the most significant bit (MSB) are applied to the second comparator 52. In addition, the first comparator 51 receives the input from the second counter 58 of the STC generator 50 in the lower PCR data, subtracts the lower STC data, and then returns the result to the first 1D flip-flop 53. Output On the other hand, the second comparator 52 also subtracts the upper STC data received from the first counter 56 in the upper PCR data and outputs the result value to the second 2D flip-flop 54. Meanwhile, the first and second D flip-flops 53 and 54, which receive output data from the first and second comparators 51 and 52, respectively, are assigned a sign bit according to a comparison signal applied from the outside. Then output to the error generating unit 55, respectively. For example, the 1D flip-flop 53 outputs the first order data of 10 bits to which a sine bit is added, which is negative as the result of the subtraction operation becomes 2's complement as shown in the following relation. It is to indicate the quantity.

Primary data [9: 0] = Lower PCR data [8: 0]-Lower SCC data [8: 0]

The range of the primary data is -300 to +300, and the most significant bit (MSB) of the primary data is a sine bit. Similarly, the 2D flip-flop 54 also outputs the 34-bit secondary data having a sine bit to the error generating unit 55, and the secondary data ranges from-(2 ³³ -300) to ( 2 ³³ -300), and the least significant bit (MSB) of the secondary data becomes a sine bit. Usually, the difference data output of the first and second D flip-flops 53 and 54 is represented by a small value, which is a microcomputer (not shown) as PCR data is added to the bit string at relatively short intervals (within 0.1 seconds). Since the initial values are applied to the first and second counters 56 and 58 described above based on the previous PCR data, the difference is rarely large.

On the other hand, the error generating unit 55 receives the first and second data, respectively, and converts the data into 8 bits of error data according to the degree of difference, and the error data will be described in more detail with reference to FIG. . 4 is an explanatory diagram showing the relationship between PCR data and STC data. FIG. 4 (a) shows the case where PCR data is ahead of STC data in time, while (b) is where STC data is ahead of PCR data. to be. As shown in FIG. 4 (a), when PCR data is earlier than STC data, the char data (PCR data-STC data) has a negative value, and otherwise the tea data has a positive value. . In addition, in FIG. 4A, when the STC data is earlier than the PCR data, the char data (PCR data-STC data) has a positive value. Otherwise, the tea data has a negative value. As described above, in the synchronous recovery device according to the present invention, the generation range of the primary data is -300 to +300, and the generation range of the secondary data is-(2 ³³ -300) to (2 ³³ -300). Said. However, the error generating unit 55 should also consider the portion outside the generation range of the first and second secondary data. In other words, when the primary data is in the generation range (-300 to +300) or when the secondary data is smaller than-(2 ³³ -300) or exceeds (2 ³³ -300), an error generator ( 55) recognizes that the mismatch between the PCR data and the STC data is small and outputs zero error data, while the primary data is out of the occurrence range (less than -300 or greater than 300) or If the secondary data is in the range of occurrence [-(2 ³³ -300) to (2 ³³ -300)], the discrepancy between the PCR data and the STC data is recognized as large and-(PCR data-STC data) / 4 Convert the error data.

Therefore, the operating range according to the present invention is shown in FIG.

3B is a detailed configuration diagram of the pulse width modulator 20 for pulse width modulating the error data [7: 0] output by the error generating unit 55. As shown in FIG. First, when the enable signal of the high state is applied to the terminal CT3 as the 5-bit counter, the third counter 67 counts the system clock applied to the terminal CK3, and counts the count value through the terminal Qout. 3 is output to the comparator 66. The third comparator 66 compares the output data of the third counter 67 applied to the terminal E with the '11010' signal applied to the terminal B. FIG. If the comparison result is matched, the reset signal is output to the terminal R3 of the third counter 67 and the enable signal is output to the terminal CT4 of the fourth counter 64. At this time, the counting value is set to '0' by the reset signal of the third counter 67, and the fourth counter 64 is a 7-bit counter, and the terminal (whenever the enable signal of the third comparator 66 is applied to the third counter 67. The system clock supplied to CK4 is counted, and the counting value is output to the fourth comparator 65 through the terminal Qout. The fourth comparator 65 compares the output data of the fourth counter 64 applied to the terminal G with the 'pulse width signal' applied to the terminal H. If the result of the comparison matches, the reset signal is output to the terminal R4 of the fourth counter 64 and the enable signal is output to the terminal CT5 of the fifth counter 63. At this time, the counting value of the fourth counter 64 is set to '0' according to the reset signal, and the fifth counter 63 is an 8-bit counter, and the terminal is applied whenever the enable signal of the fourth comparator 65 is applied. The system clock supplied to the CK5 is counted, and the counting value is output to the first pulse width modulator 62 and its own terminal R5 through the terminal Qout. Types of the index signal PWM_Index output by the fifth counter 63 may be classified into seven types as shown in FIG. The first pulse width modulator 62 outputs the bit signal PWM_Bit of a predetermined period corresponding to the applied index signal PWM_Index to the second pulse width modulator 61. That is, the bit signal PWM_Bit corresponding to the corresponding index signal PWM_Index is output by the following correspondence.

The second pulse width modulator 61 selects a corresponding bit signal PWM_Bit from the error generating unit 55 according to the error data [7: 0] to perform pulse width modulation, and the number of valid pulses of the error data. Select and collect the seven types of bit signals PWM_Bit that are already mapped. That is, pulse width modulation is performed using the corresponding bit signal PWM_Bit as a comparison signal. This is for the pulse width modulated signal to obtain a DC voltage proportional to the error data [7: 0] in an external loop filter 30. The capacitance Q of the capacitor of the loop filter 30 is Q = CV. Therefore, ΔV = t (1 / C) during charging and ΔV = t (1 / C) during discharge, so that the error data [is converted to charge time and discharge time in proportion to the error data [7: 0]. 7: 0] capacitor voltage proportional to. The pulse width modulated signal output by the second pulse width modulator 61 has a period of 256T, where T = (26 × pulse width signal) × 1 / (27 × 10 ⁶ ). The total section of the high pulse becomes the charger section and the total section of the low pulse becomes the discharge section in the 256T period. Therefore, the pulse width modulation can be performed in the entire high pulse section in 256T period in proportion to the error data.

An example of the pulse width modulated signal corresponding to the error data is shown in FIG. 7 is a waveform diagram showing pulse width modulated data according to error data. 7 is a number indicating the pulse state of the error data output by the error generating unit 55, and a pulse width modulated (PWM) waveform is shown on the right side of each number. A positive value indicates that the number of high pulses is greater than the number of low pulses. A negative number indicates that the number of low pulses is larger than the number of high pulses. For example, if the pulse state of the error data is +127, the PCR data is faster than the STC data with no low pulses, whereas if the pulse state of the error data is -127 or -128, there is no high pulse. This means that PCR data is slower than STC data. In addition, if the error data is 0, the number of low pulses and high pulses is the same, and this means that there is no difference between the PCR data and the STC data.

The second pulse width modulator 61 receives the error data [7: 0] of the error generating unit 55 and selects the bit signal PWM_Bit according to the number of pulses in the high state.

As can be seen from Table 1, the frequency of pulse generation is correlated according to the error data. That is, as the error data has a large value (positive value), the pulse width modulated data has a high pulse, while the error data has a small value (negative value), so the low pulse increases. have. For example, when the error data is +64, 192 high pulses and 64 low pulses have a ratio of 3: 1. However, when the error data is -64, the high pulses are 64 and the low pulses are 192, so the ratio is 1: 3. This pulse state is shown in FIG. 7 as a waveform. In [Table 1], N denotes the charging or discharging of the loop filter 30, and the positive value indicates the state of charge, and the negative value indicates the state of discharge, and the numerical value indicates the charge or discharge period quantitatively. It is the converted number. Therefore, as the charging and discharging is differently performed by the loop filter 30, the oscillation frequency output by the VCO 40 is also varied.

The synchronous clock recovery apparatus of the present invention can synchronize the PCR data by comparing the PCR data added at the transmitting side and the STC data generated at the receiving side and regenerating the STC data by varying the oscillation frequency according to the difference. It has an effect.

Claims (14)

Transport that recovers synchronization by varying STC data of the same number of bits according to PCT data of predetermined bits added to the bit stream to receive the transport bit stream according to the MPEG2 standard and to separately detect desired video and audio bit streams. A synchronous recovery apparatus of a demultiplexer, comprising: a comparison unit which receives the PCT data and the STC data, compares each other to have the same data value, and outputs error data corresponding to the difference between the two data; A pulse width modulator connected to an output terminal of the comparator and configured to receive the error data and modulate a pulse width according to a pulse type of the error data; A loop filter connected to an output terminal of the pulse width modulator and receiving a pulse width modulated error data to filter a predetermined band; A VCO connected to an output terminal of the loop filter and varying an oscillation frequency according to a signal filtered by the loop filter for use as a system clock; And an STC generation unit connected to an output terminal of the VCO and counting the system clock using the oscillation frequency applied from the VCO as a system clock and returning the counted STC data to the comparison unit. Synchronous recovery device of demultiplexer. 2. The apparatus of claim 1, wherein the comparing unit comprises: a first comparator configured to receive and subtract the upper PCR data including the most significant bit (MSB) of the PCR data and its corresponding upper STC data, and the least significant bit (LSB) of the PCR data; A second comparator configured to receive and subtract the lower PCR data and the corresponding lower STC data, respectively; And first and second D flip-flops for outputting secondary data, and commonly connected to output terminals of the first and second D flip-flops, and receiving the first and second secondary data to receive current PCR data and STC data. An error recovery unit for outputting error data corresponding to the difference of the synchronous recovery device of the transport demultiplexer. The first and second counters of claim 1, wherein the STC generation unit receives and counts one end of the system clock when the first enable signal is applied, and outputs a predetermined lower STC data to the second comparator. A detector for outputting a reset signal to the first counter and a carry signal to the second counter when the lower STC data reaches 299, and a carry count every time a carry generation signal is applied from the detector. And a second counter outputting the predetermined upper STC data to the comparator's second comparator, wherein the synchronous recovery device of the transport demultiplexer is counted. The method of claim 1, wherein the pulse width modulator of the third counter to count the system clock applied to the Clk terminal when the second enable signal is applied, the output data of the third counter and '11010' is applied from the outside If a comparison is made, the first comparator outputs a reset signal to the third counter and outputs a third enable signal to the fourth counter, and a system clock supplied from the outside whenever the third enable signal is applied. Outputs the reset signal to the fourth counter and matches the fourth enable signal to the fifth counter when the fourth counter counting the number and the output data of the fourth counter match with the external pulse width signal. A second comparator for outputting a signal, a fifth counter for counting a system clock supplied from the outside whenever the fourth enable signal is applied, and a small counter corresponding to the index signal PWM_Inex outputted by the fifth counter. A first pulse width modulator for outputting a period bit signal PWM_Bit and a second pulse width modulator for selectively collecting the bit signal PWM_Bit and pulse-width modulating predetermined error data applied from the error generating unit; A synchronous recovery device for a transport demultiplexer, comprising: The method of claim 3, wherein the first counter outputs to the first comparator by replacing the first initial value applied from the outside with the lower STC data when the error interval between the PCR data and the STC data on the receiving side is large. Synchronous Recovery Unit for Transport Demultiplexer. The method of claim 3, wherein the second counter outputs to the second comparator by replacing the second initial value applied from the outside with the upper STC data when the error interval between the PCR data and the STC data on the receiving side is large. Synchronous Recovery Unit for Transport Demultiplexer. 3. The synchronous recovery apparatus of a transport demultiplexer according to claim 2, wherein the first and second comparators allow the result of the subtraction operation to have a two's complement value. 3. The synchronous recovery apparatus of the transport demultiplexer according to claim 2, wherein the first and second D flip-flops are provided with the most significant bit of the first and second order data as a sine bit representing a negative / positive value. The synchronous recovery apparatus of the transport demultiplexer according to claim 8, wherein the first order data has a value of -300 to +300 when converted to a decimal number. The synchronous recovery apparatus of a transport demultiplexer according to claim 8, wherein the second secondary data has a value of-(2 ³³ -300) to (2 ³³ -300) when converted to a decimal number. The method of claim 2, wherein the error generator comprises: first data are present in the set range (-300~ + 300) or the second data is set in the range [- less than ^(233-300) or ^(233-300 Exceeding)] Outputs error data of 0, and if the 1st primary data is out of the setting range (less than -300 or exceeds 300), the 2nd secondary data is within the setting range [-(2 ³³ -300 ) - (2 If present in the ³³ -300) - (PCR data -STC data) / 4 sync recovery device of a transport demultiplexer characterized in that the output in accordance with the. The pulse width modulator of claim 4, wherein the second pulse width modulator maps and sets a bit signal PWM_Bit having a different pulse width according to the number of high or low pulses of the error data, and sets the error data according to the input bit signal. A synchronous recovery device for a transport demultiplexer, characterized in that for modulating. 13. The synchronous recovery apparatus of the transport demultiplexer according to claim 12, wherein the second pulse width modulator sets a period of the pulse width modulated signal outputted by modulating the pulse width according to the pulse state of the error data to 256T. Here, T = (26 × pulse width) × 1 / (27 × 10 ⁶ ). The synchronous recovery apparatus of the transport demultiplexer according to claim 13, wherein the second pulse width modulator modulates the pulse width in proportion to the entire high pulse section of the error data.