KR0155857B1 - Semiconductor apparatus having multilayer interconnection and forming method thereof - Google Patents
Semiconductor apparatus having multilayer interconnection and forming method thereof Download PDFInfo
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- KR0155857B1 KR0155857B1 KR1019950021393A KR19950021393A KR0155857B1 KR 0155857 B1 KR0155857 B1 KR 0155857B1 KR 1019950021393 A KR1019950021393 A KR 1019950021393A KR 19950021393 A KR19950021393 A KR 19950021393A KR 0155857 B1 KR0155857 B1 KR 0155857B1
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
- H01L21/76852—Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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Abstract
다층배선을 갖는 반도체 장치 및 그 제조방법에 관하여 게시한다. 반도체 기판 또는 다층구조의 도전층 상에 형성된 절연막 상에 하부도전층을 형성하고, 그 도전층 양 측벽에 티타늄막을 형성한다. 이어서, SiOF 를 함유하는 층간 절연막을 형성하고, 상부 도전층과 하부 도전층을 연결하기 위한 비아 콘택홀을 형성한 다음, 티타늄막을 형성하고 그 위에 알루미늄을 포함한 금속막을 형성하여 상부 도전층을 형성한다. 본 발명에 의하면, 후 속의 열처리 과정에서 발생하는 SiOF막의 장력으로 인해 도전층에 나타나는 스트레스 마이그레이션을 완전히 방지할 수 있어서, 그로 인해 발생하는 배선저항의 증가 및 단선을 줄일 수 있으며, 또한 반도체 장치의 수율 및 신뢰성을 높일 수 있다.Disclosed are a semiconductor device having a multilayer wiring and a method of manufacturing the same. The lower conductive layer is formed on the insulating film formed on the semiconductor substrate or the conductive layer of the multilayer structure, and the titanium film is formed on both sidewalls of the conductive layer. Subsequently, an interlayer insulating film containing SiOF is formed, a via contact hole for connecting the upper conductive layer and the lower conductive layer is formed, a titanium film is formed, and a metal film including aluminum is formed thereon to form an upper conductive layer. . According to the present invention, it is possible to completely prevent the stress migration appearing in the conductive layer due to the tension of the SiOF film generated in the subsequent heat treatment process, thereby reducing the increase in wiring resistance and disconnection, and also the yield of the semiconductor device. And reliability can be improved.
Description
제1도는 종래 기술에 의한 다층배선 형성방법을 설명하기 위하여 도시한 단면도이다.1 is a cross-sectional view for explaining a method for forming a multilayer wiring according to the prior art.
제2도 내지 제5도는 본 발명에 의한 다층배선 형성방법의 일예를 도시한 공정순서도이다.2 to 5 are process flowcharts showing an example of the method for forming a multilayer wiring according to the present invention.
본 발명은 다층배선을 갖는 반도체 장치 및 그 제조방법에 관한 것으로, 특히 도전층 사이에 불소산화(Fluorine doped oxide film:이하 SiOF라 칭함)을 사용할 때 발생하는 알루미늄의 스트레스 마이스레이션(Stress Migration)을 방지하기 위한 다층배선을 갖는 반도체 장치 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a multi-layered wiring and a method for manufacturing the same. In particular, stress migration of aluminum generated when a fluorine oxide (hereinafter referred to as SiOF) is used between conductive layers is provided. A semiconductor device having a multilayer wiring for preventing and a method of manufacturing the same.
반도체 장치의 배선 방법은 반도체 장치의 속도, 수율 및 신뢰성을 결정하는 요인이 되기 때문에 반도체 제조공정 중 가장 중요한 위치를 점유하고 있다. 한편, 반도체 장치가 고집적화 되고 그 내부 회로가 복잡해짐에 따라 반도체 장치는 단일금속배선에서 다층금속배선을 필요로 하게 되었다. 일반적으로, 다층 구조로 금속배선을 형성할 경우, 상하 도전층을 전기적으로 분리시키기 위하여 상하 도전층 사이에 절연막을 형성한다.The wiring method of the semiconductor device occupies the most important position in the semiconductor manufacturing process because it is a factor for determining the speed, yield and reliability of the semiconductor device. On the other hand, as semiconductor devices are highly integrated and their internal circuits become more complex, semiconductor devices require multi-layer metal wiring on single metal wiring. In general, when forming a metal wiring in a multilayer structure, an insulating film is formed between the upper and lower conductive layers in order to electrically separate the upper and lower conductive layers.
한편, 반도체 장치의 집적도가 VLSI에서 ULSI로 높아짐에 따라 상기 도전층 사이에 기생용량이 발생하고, 이 기생용량이 발생하고, 이 기생용량은 도전층에 흐르는 전기 신호의 속도 지연을 초래한다. 따라서 속도를 높이기 위해서는 기생용량을 줄여야 하며, 기생용량을 줄이는 방법은 도전층간 절연막의 유전율을 낮추는 것이다. 유전율이 낮은 도전층간 절연막으로 SiOF가 많이 사용되고 있는데, SiOF는 화학증착(CVD)공정에서 산화막 증착시 일정한 양의 불소(fluorine)를 도우핑시켜 형성한다.On the other hand, as the degree of integration of semiconductor devices is increased from VLSI to ULSI, parasitic capacitances are generated between the conductive layers, and these parasitic capacitances occur, which causes a speed delay of the electric signal flowing through the conductive layer. Therefore, to increase the speed, the parasitic capacitance must be reduced, and the method of reducing the parasitic capacitance is to lower the dielectric constant of the insulating interlayer. SiOF is widely used as a low dielectric constant interlayer insulating film. SiOF is formed by doping a certain amount of fluorine during oxide deposition in a chemical vapor deposition (CVD) process.
제1도는 종래 기술에 의한 다층배선을 갖는 반도체 장치의 제조방법을 설명하기 위한 단면도이다.1 is a cross-sectional view for explaining a method for manufacturing a semiconductor device having a multilayer wiring according to the prior art.
제1도를 참조하면, 반도체 기판(11)상에 절연막(13)을 증착한다. 다음에, 알루미늄(Al)을 증착하여 하부도전층(15)을 형성한다. 그런다음, 층간 절연막(17)을 증착한다. 이때, 사용되는 절연막은 불소를 포함하고 있는 SiOF막이다. 이어서, 상기 하부도전층과 상부도전층을 연결하기 위해 SiOF막을 패터닝한 후 습식식각하여 비아콘택홀 형성한다. 이어서, 알루미늄 증착하여 상부도전층(20)을 형성하여 하부도전층과 연결한다.Referring to FIG. 1, an insulating layer 13 is deposited on the semiconductor substrate 11. Next, aluminum (Al) is deposited to form the lower conductive layer 15. Then, the interlayer insulating film 17 is deposited. At this time, the insulating film used is a SiOF film containing fluorine. Subsequently, in order to connect the lower conductive layer and the upper conductive layer, a SiOF layer is patterned and wet etched to form via contact holes. Subsequently, aluminum is deposited to form an upper conductive layer 20 to be connected to the lower conductive layer.
상기 졀연막(13) 형성방법으로 스퍼터법에 의한 산화막(SiO2)또는 질화막(Si3N4) , CVD에 의한 산화막 또는 PSG(Phospho-Silicate Glass) 및 플라즈마 CVD에 의한 산화막 또는 질화막이 많이 사용되고 있다. 한편, 다층배선 구조에서의 표면의 평탄화를 위해서 도포법에 의한 산화막 또는 폴리이미드(Polyimide)와 양극 산화법에 의한 산화알루미늄(Al2O3)막이 선택적으로 사용되고 있다.Oxide films (SiO 2) or nitride films (Si 3 N 4) by the sputtering method, oxide films by CVD, or oxide films or nitride films by PSG (Phospho-Silicate Glass) and plasma CVD are frequently used as the method for forming the quench film 13. On the other hand, an oxide film by a coating method or an aluminum oxide (Al 2 O 3) film by anodizing is selectively used to planarize a surface in a multilayer wiring structure.
그러나, 상술한 SiOF를 사용하여 배선을 형성할 때 층간절연막은 후속 공정에 따르는 열처리 과정에서 Si-F결합력이 파괴되면서 높은 장력이 발생하고, 이로 인해 알루미늄 배선에 스트레스 마이그레이션(Stress Migration : S/M) 이 일어나 보이드(Void)나 다른 모양의 변형이 생겨, 배선이 단선되거나 저항이 증가하여 수율 및 신뢰도의 저하를 초래한다.However, when the wiring is formed using the above-described SiOF, the interlayer insulating film has a high tension as the Si-F bonding force is destroyed in the heat treatment process according to the subsequent process, which causes stress migration to the aluminum wiring (Stress Migration: S / M Occurs and voids or other shapes deform, leading to wire breakage or increased resistance resulting in lower yield and reliability.
따라서, 본 발명의 목적은 상기 SiOF 절연막으로부터 도전층을 격리시킨 다층배선을 갖는 반도체 장치를 제공하는데 있다.Accordingly, it is an object of the present invention to provide a semiconductor device having a multilayer wiring in which a conductive layer is isolated from the SiOF insulating film.
본 발명의 다른 목적은 상기한 격리구조의 반도체 장치를 효율적으로 제조할 수 있는 제조방법을 제공하는데 있다.Another object of the present invention is to provide a manufacturing method capable of efficiently manufacturing the semiconductor device of the above-described isolation structure.
상기 목적을 달성하기 위하여 본 발명은, 상부도전층과 하부도전층을 비아홀을 갖는 충간절연막을 통하여 연결하는 다층배선을 갖는 반도체 장치에 있어서, 상기 하부도전층의 양 측벽과 상기 비아홀을 덮도록 층간절연막 상에 금속막이 형성되어, 상기 상부도전층과 하부도전층을 연결하는 것을 특징으로 하는 다층배선을 갖는 반도체 장치를 제공한다.In order to achieve the above object, the present invention is a semiconductor device having a multi-layer wiring connecting the upper conductive layer and the lower conductive layer through the interlayer insulating film having a via hole, the interlayer so as to cover both sidewalls of the lower conductive layer and the via hole A metal film is formed on an insulating film, and the upper conductive layer and the lower conductive layer are connected to each other.
상기 다른 목적을 달성하기 위한 본 발명은, 반도체 기판 또는 다층배선 상에 절연막을 형성하는 단계와, 상기 절연막 상에 하부도전층을 형성하는 단계와, 상기 하부도전층 양 측벽의 제1금속막을 형성하는 단계와, 상기 제1금속막이 형성된 기판의 전면에 층간절연막을 형성하는 단계와, 상기 층간절연막 상에 상기 하부도전층이 대기에 노출되도록 비아 콘택홀을 형성하는 단계와, 상기 층간절연막이 형성된 기판의 전면에 제2금속막을 형성하는 단계 및 상기 제2금속막 상에 상부 도전층을 형성하는 단계를 구비하는 것을 특징으로 하는 다층배선을 갖는 반도체 장치의 제조방법을 제공한다.According to another aspect of the present invention, there is provided a method of forming an insulating film on a semiconductor substrate or a multilayer wiring, forming a lower conductive layer on the insulating film, and forming first metal films on both sidewalls of the lower conductive layer. Forming an interlayer insulating film on the entire surface of the substrate on which the first metal film is formed; forming a via contact hole on the interlayer insulating film so that the lower conductive layer is exposed to the air; and forming the interlayer insulating film. A method of manufacturing a semiconductor device having a multi-layer wiring, comprising forming a second metal film on an entire surface of a substrate and forming an upper conductive layer on the second metal film.
이하, 첨부한 도면을 참조하여 본 발명에 따른 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
제2도 내지 제5도는 본 발명에 따른 반도체 장치의 다층배선 형성방법의 일 예를 나타내는 공정순서도이다.2 to 5 are process flowcharts showing an example of a method for forming a multilayer wiring of a semiconductor device according to the present invention.
제2도를 참조하면, 반도체 기판(21) 상에 또는 다층의 배선 상에, CVD산화막, SOG(Spin On Glass)도는 BPSG(Boro-Phopho-Silicate Glass) 등의 절연막(23)을 평탄화 방법을 사용하여 증착한다. 이때 사용하는 평탄화 방법으로서는 수지 절연법, 양극 산화법, Al리프트오프법, 플라즈마 평탄화법 등이 있다. 다음에, 상기 절연막(23) 상에 하부도전층(25)을 알루미늄을 함유하는 다층 구조의 금속배선, 즉 Ti＼TiN＼Al＼TiN, Al＼TiN, Al＼Ti, TiN＼Al＼TiN 또는 Ti＼Al＼TiN 등의 구조를 갖는 금속막으로 형성한 다음, 포토 레지스트를 증착하고 패터닝 한다. 그런 다음, 사진식각 공정을 이용하여 식각하여 패턴된 하부 도전층을 형성한다.Referring to FIG. 2, a method of planarizing an insulating film 23 such as a CVD oxide film, spin on glass (SOG), or boro-phospho-silicate glass (BPSG) or the like on a semiconductor substrate 21 or on a multilayer wiring is described. To deposit. The planarization method used at this time includes a resin insulation method, anodization method, Al lift-off method, plasma planarization method and the like. Next, on the insulating film 23, the lower conductive layer 25 has a metal structure having a multilayer structure containing aluminum, that is, Ti＼TiN＼Al＼TiN, Al＼TiN, Al＼Ti, TiN＼Al＼TiN, or After forming a metal film having a structure such as Ti＼Al＼TiN, a photoresist is deposited and patterned. Then, the patterned lower conductive layer is formed by etching using a photolithography process.
제3도를 참조하면, 상기 형성된 하부 도전층(25) 상에 티타늄을 증착하고 도전층의 양 측벽에만 티타늄막(16)이 남아 있도록 하고 나머지 부분은 이방성 에칭법을 사용하여 식각한다. 이때, 도전층 양 측벽에 남아있는 티타늄막의 두께는 100Å~1000Å이 되도록 한다.Referring to FIG. 3, titanium is deposited on the formed lower conductive layer 25, and the titanium film 16 remains on both sidewalls of the conductive layer, and the remaining portions are etched using anisotropic etching. At this time, the thickness of the titanium film remaining on both sidewalls of the conductive layer is 100 kPa to 1000 kPa.
상기 도전층 측벽의 티타늄막은 SiOF 절연막에 의해 하부 도전층에 발생하는 스트레스 마이그레이션을 방지하여 배선의 저항 증가 및 단선을 예방하고 신뢰성을 향상시켜 준다.The titanium film on the sidewall of the conductive layer prevents stress migration generated in the lower conductive layer by the SiOF insulating layer, thereby preventing an increase in resistance and disconnection of the wiring and improving reliability.
제4도를 참조하면, 상기 도전층(25)상에 SiOF단일막 또는 SiOF를 함유하는 다층 구조의 층간절연막(27)을 평탄화 방법에 의해 증착한다. 평탄화 방법으로서는 CVD oxide＼SiOF＼CVD oxide, CVD oxide＼SiFO＼SOG＼CVD oxide 또는 SiOF＼etch back＼CVD oxide등이 사용된다. 또한 SiOF절연막은 CVD 또는 LPD( Liquid Phase Deposition)방법으로 형성한다. 다음에, 상기 절연막 상에 포토레지스트막을 형성한 후, 통상적인 사진식각공정에 의해 포토레지스트막을 패터닝하고 식각하여 상부 도전층과 하부 도전층을 연결하기 위한 비아 콘택홀(28)을 형성한다.Referring to FIG. 4, a single SiOF film or an interlayer insulating film 27 having a multilayer structure containing SiOF is deposited on the conductive layer 25 by a planarization method. As the planarization method, CVD oxide, SiOF, CVD oxide, CVD oxide, SiFO, SOG, CVD oxide, or SiOF etch back, CVD oxide are used. In addition, the SiOF insulating film is formed by CVD or Liquid Phase Deposition (LPD) method. Next, after the photoresist film is formed on the insulating film, the photoresist film is patterned and etched by a conventional photolithography process to form a via contact hole 28 for connecting the upper conductive layer and the lower conductive layer.
제5도를 참조하면, 상기 층간절연막(27) 및 비아 홀의 양 측면과 하단에 티타늄막(29)을 100Å~1000Å이 되도록 형성한다. 이 티타늄막의 역할은 후속 공정에서 행하는 열처리 과정에서 SiOF막의 강한 장력으로 말미암아 상부 도전층 및 비아 콘택홀에 발생하는 스트레스 마이그레이션을 방지하여 배선의 저항 및 콘택 저항 증가를 줄이는 것이다. 다음에, 상기 티타늄막 위에 금속막을 도포하여 상부 도전층(30)을 형성한다. 상부 도전층(30)은 알루미늄을 함유하는 다층 구조의 금속배선, 즉 Ti＼TiN＼Al＼TiN, Al＼TiN, Al＼Ti, TiN＼Al＼TiN 또는 Ti＼Al＼TiN등의 구조를 갖는 금속막으로 형성한다.Referring to FIG. 5, titanium films 29 are formed on both side surfaces and lower ends of the interlayer insulating film 27 and the via holes so as to be 100 μs to 1000 μs. The role of this titanium film is to prevent the stress migration occurring in the upper conductive layer and the via contact hole due to the strong tension of the SiOF film during the heat treatment performed in the subsequent process, thereby reducing the resistance of the wiring and the increase in contact resistance. Next, a metal film is coated on the titanium film to form an upper conductive layer 30. The upper conductive layer 30 has a metal structure having a multilayer structure containing aluminum, that is, a structure such as Ti＼TiN＼Al＼TiN, Al＼TiN, Al＼Ti, TiN＼Al＼TiN, or Ti＼Al＼TiN. It is formed of a metal film.
이상에서 설명한 바와 같이, 본 발명에 따른 반도체 장치의 다층배선 형성방법에 의하면, 티타늄막을 사용하여 SiOF 절연막으로부터 알루미늄으로 구성된 상하부 도전층을 격리시킴으로 상하부 도전층에 발생하는 스트레스 마이그레이션을 방지할 수 있어 배선의 저항 증가 및 단선을 줄이고 또한 반도체 장치의 수율 및 신뢰성을 향상시킬 수 있다.As described above, according to the method for forming a multilayer wiring of the semiconductor device according to the present invention, the stress migration occurring in the upper and lower conductive layers can be prevented by isolating the upper and lower conductive layers made of aluminum from the SiOF insulating film using a titanium film. Increasing the resistance and reducing the disconnection can also improve the yield and reliability of the semiconductor device.
이상, 본 발명은 상기 실시예를 통하여 구체적으로 설명하였지만 이에 한정되지 않으며, 많은 변형이 본 발명의 기술적 사상내에서 당 분야에서 통상의 지식을 가진 자에 의하여 가능함은 명백하다.As mentioned above, the present invention has been described in detail through the above embodiments, but the present invention is not limited thereto, and it is apparent that many modifications are possible by those skilled in the art within the technical idea of the present invention.
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