KR0150680B1 - Method of making gate electrode in rom - Google Patents
Method of making gate electrode in romInfo
- Publication number
- KR0150680B1 KR0150680B1 KR1019940035428A KR19940035428A KR0150680B1 KR 0150680 B1 KR0150680 B1 KR 0150680B1 KR 1019940035428 A KR1019940035428 A KR 1019940035428A KR 19940035428 A KR19940035428 A KR 19940035428A KR 0150680 B1 KR0150680 B1 KR 0150680B1
- Authority
- KR
- South Korea
- Prior art keywords
- gate electrode
- polysilicon layer
- rom
- ion
- conductive type
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 22
- 229920005591 polysilicon Polymers 0.000 claims abstract description 22
- 239000012535 impurity Substances 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 16
- 150000002500 ions Chemical class 0.000 claims description 10
- 238000005468 ion implantation Methods 0.000 claims description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 2
- 238000000926 separation method Methods 0.000 claims description 2
- 238000002955 isolation Methods 0.000 claims 3
- 230000010354 integration Effects 0.000 abstract description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 abstract 1
- 229910052804 chromium Inorganic materials 0.000 abstract 1
- 239000011651 chromium Substances 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 롬의 게이트 전극 제조방법에 관한 것으로, 게이트폴리실리콘층에 서로 다른 형의 불순물을 선택적으로 이온주입하여 P-N접합을 형성함으로써 상호 절연된 게이트 전극을 형성하는 것을 특징으로 함으로써 본 발명은 마스크롬 제조시 패턴간 간격을 줄임으로써 소자의 집적도를 증대시킬 수 있다.The present invention relates to a method for manufacturing a gate electrode of a ROM. The present invention is characterized by forming gate electrodes insulated from each other by selectively implanting impurities of different types into the gate polysilicon layer to form a PN junction. In the manufacture of chromium, the integration of devices can be increased by reducing the spacing between patterns.
Description
제1도는 낸드(NAND)형 마스크롬의 기본 회로도.1 is a basic circuit diagram of a NAND mask mask.
제2도는 종래방법에 따라 형성된 제1도의 마스크롬의 1스트링의 단면도.2 is a cross-sectional view of one string of mask rom of FIG. 1 formed according to a conventional method.
제3a도내지 제3c도는 본 발명에 따른 상기 제1도의 마스크롬의 1스트링 제조 공정 단면도.3a to 3c are cross-sectional views of a process for producing a single string of mask rom of FIG. 1 according to the present invention.
*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1,31 : 반도체 기판 3,33 : 폴리실리콘층1,31 semiconductor substrate 3,33 polysilicon layer
2,32 : 게이트 산화층 34 : 감광막 패턴2,32: gate oxide layer 34: photoresist pattern
35 : n형 폴리실리콘층 36 : p형 폴리실리콘층35: n-type polysilicon layer 36: p-type polysilicon layer
본 발명은 롬의 게이트 전극 제조방법에 관한 것으로, 특히 콘택형성 없이 워드라인 선택라인(W/L select line)과 롬코드라인(ROM code line)형성시 워드라인과 워드라인 사이 간격을 최소화하기 위한 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a gate electrode of a ROM, and in particular, to minimize the gap between a word line and a word line when forming a word line selection line and a ROM code line without forming a contact. It is about a method.
콘택-레스(contact-less) 마스크롬(MASKROM)은 콘택홀이 필요 없이 웨이퍼에 이온주입된 불순물의 확산에 의해 스트링이 형성되는 마스크롬을 일컫는다.The contact-less mask ROM refers to a mask ROM in which a string is formed by diffusion of impurities implanted into a wafer without requiring a contact hole.
제1도는 낸드(NAND)형 마스크롬의 기본 회로도로서, 비트라인은 콘택에 의해 메탈라인으로 구성되며, 롬코드(W/L0내지 W/L7) 및 워드라인 선택(W/L선택1,W/L선택2)은 폴리실리콘 라인으로 구성된다. 즉, 콘택-레스로 연결되어 있다.1 is a basic circuit diagram of a NAND type mask ROM, in which a bit line is composed of metal lines by contact, and ROM codes (W / L0 to W / L7) and word line selection (W / L selections 1 and W). / L selection2) consists of polysilicon lines. That is, contactless.
제2도는 종래방법에 따라 형성된 제1도의 마스크롬의 1스트링의 단면도로서, 이를 통하여 종래기술을 개략적으로 설명하면 다음과 같다.FIG. 2 is a cross-sectional view of one string of the mask rom of FIG. 1 formed according to the conventional method.
도시된 바와 같이 반도체 기판(1)위에 게이트 산화층(2), 폴리실리콘층(3)을 차례로 증착한 다음, 워드라인선택1,2(11 및 12)와 워드라인0 내지 워드라인7(21내지 28)의 폴리실리콘 라인은 포토리소그래피 공정에 의한 감광막 패턴을 식각마스크로 상기 폴리실리콘층(3), 게이트 산화층(2)을 차례로 선택식각함으로써 이루어진다.As shown, the gate oxide layer 2 and the polysilicon layer 3 are sequentially deposited on the semiconductor substrate 1, and then word line selection 1,2 and 11 and word lines 0 to wordlines 7 to 21 are formed. The polysilicon line of 28) is formed by selectively etching the polysilicon layer 3 and the gate oxide layer 2 sequentially using a photoresist pattern by a photolithography process as an etching mask.
그러나, 상기 종래방법은 노광기의 해상력을 고려할 때, 제2도에 도시한 바와 같이 워드라인과 워드라인 사이의 간격(A)을 0.5㎛내지 0.7㎛로 형성해야 하기 때문에 집적도 향상에 저해가 되는 문제점이 있다.However, in the conventional method, when considering the resolution of the exposure machine, as shown in FIG. 2, the distance A between the word line and the word line must be formed to be 0.5 µm to 0.7 µm, which hinders the improvement of the density. There is this.
상기와 같은 종래기술의 문제점을 해결하기 위하여 안출된 본 발명은 노광기의 해상력과는 무관하게 패턴간 간격을 최소화할 수 있는 롬의 게이트 전극 제조방법을 제공하는데 그 목적이 있다.The present invention devised to solve the problems of the prior art as described above is an object of the present invention to provide a method for manufacturing a gate electrode of a ROM that can minimize the gap between patterns irrespective of the resolution of the exposure machine.
상기 목적을 달성하기 위하여 본 발명은 롬의 게이트 전극 제조방법에 있어서, 폴리실리콘층 내에 제1 및 제2도전형의 불순물을 선택적으로 이온주입하여 접합을 형성함으로써, 제1도전형으로 이루어지는 게이트 전극 및 이웃하는 게이트 전극간을 분리시키는 제2도전형의 분리영역을 형성하는 것을 특징으로 하는 롬의 게이트 전극 제조 방법을 제공한다.In order to achieve the above object, the present invention provides a gate electrode made of a first conductive type by forming a junction by selectively implanting impurities of the first and second conductive types into a polysilicon layer. And forming a separation region of a second conductivity type to separate neighboring gate electrodes.
이하, 첨부된 도면을 참조하여 본 발명의 일실시예를 상술한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.
제3a도 내지 제3c도는 본 발명에 따른 상기 제1도의 마스크롬의 1스트링 제조 공정 단면도로서, 먼저, 제3a도에 도시된 바와 같이 반도체 기판(31)위에 게이트 산화층(32)을 형성하고, 도핑되지 않은 폴리실리콘층(33)을 2000Å내지 4000Å두께로 증착한 다음, 상기 폴리실리콘층(33)내에 p형 불순물인 붕소(B)를 108이온/cm2의 도즈량, 50KeV의 에너지로 이온주입 한다.3A to 3C are cross-sectional views illustrating a process of manufacturing a single string of the mask rom of FIG. 1 according to the present invention. First, as shown in FIG. 3A, a gate oxide layer 32 is formed on a semiconductor substrate 31. The undoped polysilicon layer 33 was deposited to a thickness of 2000 kPa to 4000 kPa. Then, the boron (B), a p-type impurity, was deposited in the polysilicon layer 33 with a dose of 10 8 ions / cm 2 and an energy of 50 KeV. Ion implantation.
이어서, 제3b도에 도시된 바와 같이 n형 불순물 이온주입용 마스크로 감광막 패턴(34)을 형성한 다음, n형 불순물인 인(P)을 상기 p형 불순물인 붕소(B)의 제곱배 정도의 도즈량(1016이온/cm2), 60KeV의 에너지로 이온주입 한다. 이때, 상기 감광막 패턴(34)은 게이트 적극 형성 영역 이외의 영역에 형성되며, 감광막 패턴(34)은 폭(B)은 0.5㎛로 형성되고, 상기 n형 불순물 이온주입 후 감광막 패턴(34)하부의 상기 폴리실리콘층(33)은 p형으로 남는다.Subsequently, as shown in FIG. 3B, the photosensitive film pattern 34 is formed using an n-type impurity ion implantation mask, and then phosphorus (P), which is an n-type impurity, is about square times of the boron (B), which is the p-type impurity. Dose amount (10 16 ions / cm 2 ) and ion implantation with energy of 60KeV. In this case, the photoresist pattern 34 is formed in a region other than the gate positive electrode formation region, and the photoresist pattern 34 has a width B of 0.5 μm, and the lower portion of the photoresist pattern 34 after implanting the n-type impurity ions. The polysilicon layer 33 of remains in p-type.
다음으로, 제3c도에 도시된 바와 같이 상기 감광막 패턴(34)을 제거한 다음, 열처리 공정을 실시한다.Next, as shown in FIG. 3C, the photoresist pattern 34 is removed, and then a heat treatment process is performed.
이와 같이 P-N접합을 형성하여 게이트 전극 간을 분리시킨다. 이때, 상기 고농도로 이온주입된 n형 불순물 인(P)의 확산에 의해 게이트 전극을 이루는 n형폴리실리콘층(35)은 그 폭이 확장되고, 상기 n형 폴리실리콘층(35)을 분리시키는 p형 폴리실리콘층(36)은 0.2㎛로 유지된다. 게이트 전극 간의 간격(A' )즉, p형 폴리실리콘층(35)의 폭이 작기 때문에 소스/드레인 없이도 마스크롬 동작에는 이상이 없다.In this way, a P-N junction is formed to separate the gate electrodes. At this time, the n-type polysilicon layer 35 forming the gate electrode is expanded by the diffusion of the n-type impurity phosphorus (P) implanted at a high concentration, thereby separating the n-type polysilicon layer 35. The p-type polysilicon layer 36 is kept at 0.2 mu m. Since the gap A 'between the gate electrodes, that is, the width of the p-type polysilicon layer 35 is small, there is no problem in the mask rom operation without the source / drain.
상기와 같이 이루어지는 본 발명은 마스크롬 제조시 패턴간 간격을 줄임으로써 소자의 집적도를 증대시킬 수 있다.According to the present invention made as described above it is possible to increase the degree of integration of the device by reducing the spacing between the patterns when manufacturing the mask rom.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
Claims (9)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940035428A KR0150680B1 (en) | 1994-12-20 | 1994-12-20 | Method of making gate electrode in rom |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940035428A KR0150680B1 (en) | 1994-12-20 | 1994-12-20 | Method of making gate electrode in rom |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960026886A KR960026886A (en) | 1996-07-22 |
| KR0150680B1 true KR0150680B1 (en) | 1998-10-01 |
Family
ID=19402521
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019940035428A KR0150680B1 (en) | 1994-12-20 | 1994-12-20 | Method of making gate electrode in rom |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0150680B1 (en) |
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1994
- 1994-12-20 KR KR1019940035428A patent/KR0150680B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR960026886A (en) | 1996-07-22 |
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