KR960026886A - Rom gate electrode manufacturing method - Google Patents

Rom gate electrode manufacturing method Download PDF

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Publication number
KR960026886A
KR960026886A KR1019940035428A KR19940035428A KR960026886A KR 960026886 A KR960026886 A KR 960026886A KR 1019940035428 A KR1019940035428 A KR 1019940035428A KR 19940035428 A KR19940035428 A KR 19940035428A KR 960026886 A KR960026886 A KR 960026886A
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KR
South Korea
Prior art keywords
impurity
gate electrode
rom
type
electrode manufacturing
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Application number
KR1019940035428A
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Korean (ko)
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KR0150680B1 (en
Inventor
황준
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940035428A priority Critical patent/KR0150680B1/en
Publication of KR960026886A publication Critical patent/KR960026886A/en
Application granted granted Critical
Publication of KR0150680B1 publication Critical patent/KR0150680B1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
    • H10B20/36—Gate programmed, e.g. different gate material or no gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 롬의 게이트전극 제조방법에 관한 것으로, 게이트폴리실리콘층에 서로 다른 형의 불순물을 선택적으로 이온주입하여 P-N 접합을 형성함으로써 상호 절연된 게이트전극을 형성하는 것을 특징으로 함으로써 본 발명은 마스크롬 제조시 패턴간 간격을 줄임으로써 소자의 집적도를 증대시킬 수 있다.The present invention relates to a method for manufacturing a gate electrode of a ROM, wherein the gate electrode is insulated from each other by selectively implanting impurities of different types into the gate polysilicon layer to form a PN junction. In the manufacture of chromium, the integration of devices can be increased by reducing the spacing between patterns.

Description

롬의 게이트전극 제조방법Rom gate electrode manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 낸드(NAND)형 마스크롬의 기본 회로도, 제3A도 내지 제3C도는 본 발명에 따른 상기 제1도의 마스크롬의 1스트링 제조과정을 나타내는 공정단면도.1 is a basic circuit diagram of a NAND type mask rom, and FIGS. 3A to 3C are process cross-sectional views illustrating a process of manufacturing one string of the mask rom of FIG. 1 according to the present invention.

Claims (7)

롬의 게이트전극 제조방법에 있어서, 게이트폴리실리콘층에 서로 다른 형의 불순물을 선택적으로 이온주입하여 P-N 접합을 형성함으로써 상호 절연된 게이트전극을 형성하는 것을 특징으로 하는 롬의 게이트전극 제조방법.A method of manufacturing a gate electrode of a ROM, wherein the gate electrode is insulated from each other by selectively implanting impurities of different types into the gate polysilicon layer to form a P-N junction. 제1항에 있어서, 상기 게이트폴리실리콘츠은 2000 내지 4000A 두께로 형성되는 것을 특징으로 하는 롬의 게이트전극 제조방법.The method of claim 1, wherein the gate polysilicon is formed to a thickness of 2000 to 4000A. 제1항에 있어서, 상기 P-N 접합은 제1불순물을 도핑하는 단계; 불순물 이온주입용 마스크를 형성하는 단계; 상기 제1불순물과 반대되는 형의제2불순물을 도즈량을 달리하여 도핑하는 단계를 포함하여 이루어지는 것을 특징으로 하는 마스크롬 제조방법.The method of claim 1, wherein the P-N junction comprises: doping a first impurity; Forming a mask for implanting impurity ions; And a step of doping the second impurity of the type opposite to the first impurity at different doses. 제3항에 있어서, 상기 제1불순물은 p형인 것을 특징으로 하는 마스크롬 제조방법.4. The method of claim 3, wherein the first impurity is p-type. 제4항에 있어서, 상기 p형 불순물은 붕소(B)인 것을 특징으로 하는 마스크롬 제조방법.The method of claim 4, wherein the p-type impurity is boron (B). 제5항에 있어서, 상기 붕소는 108이온/㎠의 도즈량, 50keV의 에너지로 이온주입 되는 것을 특징으로 하는 마스크롬 제조방법.The method of claim 5, wherein the boron is ion implanted with a dose of 10 8 ions / cm 2 and an energy of 50 keV. 제4항에 있어서, 상기 불순물 이온주입용 마스크는 포토리소그래피 공정에 의한 감광막 패턴인 것을 특징으로 하는 마스크롬 제조방법.The method of claim 4, wherein the impurity ion implantation mask is a photosensitive film pattern formed by a photolithography process. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940035428A 1994-12-20 1994-12-20 Method of making gate electrode in rom KR0150680B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940035428A KR0150680B1 (en) 1994-12-20 1994-12-20 Method of making gate electrode in rom

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940035428A KR0150680B1 (en) 1994-12-20 1994-12-20 Method of making gate electrode in rom

Publications (2)

Publication Number Publication Date
KR960026886A true KR960026886A (en) 1996-07-22
KR0150680B1 KR0150680B1 (en) 1998-10-01

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940035428A KR0150680B1 (en) 1994-12-20 1994-12-20 Method of making gate electrode in rom

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KR (1) KR0150680B1 (en)

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Publication number Publication date
KR0150680B1 (en) 1998-10-01

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