KR0145841B1 - Padless lead frame and plastic package using it - Google Patents
Padless lead frame and plastic package using itInfo
- Publication number
- KR0145841B1 KR0145841B1 KR1019950018927A KR19950018927A KR0145841B1 KR 0145841 B1 KR0145841 B1 KR 0145841B1 KR 1019950018927 A KR1019950018927 A KR 1019950018927A KR 19950018927 A KR19950018927 A KR 19950018927A KR 0145841 B1 KR0145841 B1 KR 0145841B1
- Authority
- KR
- South Korea
- Prior art keywords
- lead
- substrate
- chip
- pad
- dummy
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73207—Bump and wire connectors
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
본 발명은 더미리드가 기판과 리드프레임을 기계적으로 연결시키는 것을 특징으로 하는 패키지에 있어서, 특히 리드프레임 패드를 없애고 기판과 리드프레임을 기계적으로 연결할 수 있는 더미리드를 형성하고, 기판상에 더미범프 패드를 만들어, 리드 프레임과 기판을 접착시켜 접착제로 접착하는 다이접착공정을 없앰으로써, 패키지 공정을 단순화시키고 패드에서 발생하는 패키지 불량을 방지하여 신뢰성을 개선하는 것을 특징으로 한다.The present invention provides a package in which the dummy lead mechanically connects the substrate and the lead frame, and in particular, a dummy lead capable of removing the lead frame pad and mechanically connecting the substrate and the lead frame to form a dummy bump on the substrate. By making a pad, by eliminating the die-bonding process of adhering the lead frame and the substrate with an adhesive, it simplifies the packaging process and prevents package defects occurring in the pad, thereby improving reliability.
Description
제1도는 종래 기술에 따른 리드프레임의 평면도.1 is a plan view of a leadframe according to the prior art.
제2도는 본 발명에 따른 패드리스 리드프레임의 평면도.2 is a plan view of a padless leadframe according to the present invention.
제3도는 본 발명에 따른 제1실시예로써, 패드리스 리드프레임을 적용한 멀티칩 패키지의 사시도.3 is a perspective view of a multichip package to which a padless leadframe is applied according to a first embodiment of the present invention.
제4도는 제3도의 A-A' 계단단면도4 is a cross-sectional view taken along the line A-A 'of FIG.
제5도는 제4도 A부분의 확대도.5 is an enlarged view of a portion A of FIG.
제6도는 본 발명에 따른 멀티칩이 장착되는 기판의 평면도.6 is a plan view of a substrate on which a multichip according to the present invention is mounted.
제7도는 본 발명에 따른 제2실시예로써, 패드리스 리드프레임을 적용한 단일칩 패키지의 사시도.7 is a perspective view of a single chip package to which a padless lead frame is applied according to a second embodiment according to the present invention.
제8도는 제7도의 B-B' 계단단면도.8 is a cross-sectional view taken along line B-B 'of FIG.
제9도는 제8도 B부분의 확대도.9 is an enlarged view of a portion B of FIG. 8.
제10도는 본 발명에 따른 단일칩의 평면도10 is a plan view of a single chip according to the present invention
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 플립칩 10' : 칩10: flip chip 10 ': chip
11 : 납범프 12 : 납패드11: lead bump 12: lead pad
14 : 제1배선 패턴 16 : 제2배선 패턴14: first wiring pattern 16: second wiring pattern
18 : 댐바(dambar) 20 : 더미리드18: dambar 20: dummy lead
21 : 납범프 또는 금범프 22 : 납패드 또는 금패드21: lead bump or gold bump 22: lead pad or gold pad
23 : 제1 폴리머 테이프 25 : 납 도금막23: first polymer tape 25: lead plating film
30 : 리드 32 : 은 도금막30: lead 32: silver plating film
34 : 알루미늄 패드 40 : 와이어34: aluminum pad 40: wire
100 : 기판 100' : 기판면100: substrate 100 ': substrate surface
110 : 제2폴리머 테이프 120 : 인덱스 홀110: second polymer tape 120: index hole
200 : 패드리스 리드프레임200: padless leadframe
본 발명은 플라스틱 패키지에 있어서, 특히 다이접착 공정을 없애고, 칩 및 패드의 계면박리에 따른 패키지의 신뢰성을 개선하기 위한 패드리스 리드프레임과 이를 이용한 플라스틱 패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a padless lead frame and a plastic package using the same in a plastic package, in particular to eliminate die bonding processes and to improve the reliability of the package due to interfacing of chips and pads.
반도체 장치의 패키지 중에서 플라스틱 패키지는 제조공정이 간단하고, 제조비용이 저렴하여 가장 많이 사용되고 있다.Among the packages of the semiconductor device, the plastic package is most frequently used because of its simple manufacturing process and low manufacturing cost.
메모리 장치 분야에 있어서, 칩 크기의 증가에 대응하고 칩의 점유율을 높이면서 신뢰성을 개선하는 방안으로 리드프레임 패드를 갖지 않고, 리드를 폴리이미드 테이프으로 리드프레임을 칩의 상면에 접착한 리드 온 칩(Lead On Chip) 유형의 패키지가 개발되어 양산되고 있다. 그러나, 리드 온 칩 패키지를 멀티칩 패키지에 적용하기가 곤란하다. 그 이유는, 멀티칩 패키지의 기판위에는 칩들이 장착되어지고, 칩들간에 있어서 전기적으로 연결하여주는 패턴들이 있으므로, 리드를 기판위에 붙일 수 없기 때문이다.In the memory device field, a lead-on chip in which the lead frame is bonded to the upper surface of the chip without a lead frame pad in order to cope with an increase in the chip size and to improve the reliability while increasing the chip occupancy rate. Packages of the Lead On Chip type have been developed and are being produced. However, it is difficult to apply a lead-on chip package to a multichip package. The reason is that since the chips are mounted on the substrate of the multichip package and there are patterns for electrically connecting the chips, the lead cannot be attached to the substrate.
제1도는 종래 기술에 따른 리드프레임의 평면도이다. 제1도를 참조하면, 리드프레임(200')내에 형성된 기판면 또는 칩면(기판 상부 또는 칩의 상부를 도시하지 않은 부분)(100')에는 이격된 좌·우 위치에 가로방향으로 복수개의 리드(30)가 정렬·배치되어 있고, 상기 기판면 또는 칩면(100')의 이격된 상·하 위치에 세로방향으로 복수개의 리드가 정렬·배치되어 있고, 상기 복수개의 리드0는 제2폴리머 테이프(110)에 의해서 고정되어 있으며, 성형 공정에서 플래쉬(flash)의 발생을 방지하기 위한 댐바(18)가 형성되어 있다. 또한, 리드프레임(200')의 좌·우 말단에 복수개의 인덱스 홀(120)이 형성되어 있다.1 is a plan view of a lead frame according to the prior art. Referring to FIG. 1, a plurality of leads are disposed in a horizontal direction at left and right positions spaced apart from a substrate surface or a chip surface (a portion of the substrate or an upper portion of the chip) 100 ′ formed in the lead frame 200 ′. 30 are aligned and arranged, and a plurality of leads are aligned and arranged in the vertical direction at spaced up and down positions of the substrate surface or the chip surface 100 ', and the plurality of leads 0 is a second polymer tape. It is fixed by 110, and a dam bar 18 is formed to prevent the occurrence of flash in the molding process. In addition, a plurality of index holes 120 are formed at left and right ends of the lead frame 200 ′.
따라서 본 발명의 목적은 플라스틱 패키지에서 기판 크기의 증가에 대응하고, 기판의 점유율을 높이면서도 신뢰성을 개선시키는 패드리스 리드프레임 및 이를 이용한 플라스틱 패키지를 제공하는데 있다.Accordingly, an object of the present invention is to provide a padless lead frame and a plastic package using the same, which correspond to an increase in substrate size in a plastic package and improve reliability while increasing the occupancy of the substrate.
상기 목적을 달성하기 위하여, 기판 및 칩면의 어느 한 면에 이격된 좌·우 위치에 가로방향으로 복수개의 리드가 정렬·배치되고, 상기 기판면 및 칩면의 어느 한 면에 이격된 상·하 위치에 세로방향으로 복수개의 리드가 정렬·배치되고, 상기 복수개의 리드가 폴리이미드 테이프에 의해서 고정되고, 상기 리드의 기판쪽 말단에 은 도금막이 형성되고 : 좌·우측 말단에 복수개의 인덱스 홀이 형성된; 리드프레임에 있어서, 탑재되는 칩 및 기판중의 어느 하나를 기계적으로 고정하기 위해 그 기판면 및 칩면 중의 어느 하나의 각 모서리 부분에 정렬·배치된 더미리드(dummy lead)를 포함하는 것을 특징으로 하는 패드리스(padless) 리드프레임을 제공한다.In order to achieve the above object, a plurality of leads are arranged and arranged in the horizontal direction at left and right positions spaced apart from one surface of the substrate and the chip surface, and the upper and lower positions spaced apart from any one surface of the substrate surface and the chip surface. A plurality of leads are aligned and arranged in the longitudinal direction, and the plurality of leads are fixed by polyimide tape, and a silver plated film is formed at the substrate side ends of the leads, and a plurality of index holes are formed at the left and right ends. ; A lead frame, comprising: a dummy lead arranged and arranged at each corner portion of either the substrate surface or the chip surface to mechanically fix any one of the mounted chip and the substrate. Provide a padless leadframe.
또한, 상기 목적을 달성하기 위하여,In addition, in order to achieve the above object,
멀티칩을 적용한 플라스틱 패키지에 있어서,In the plastic package applying the multi-chip,
비활성화층과 유전층이 순차적층된 기판과;A substrate on which the passivation layer and the dielectric layer are sequentially stacked;
상기 기판 상면에 형성된 복수개의 알루미늄 패드와,A plurality of aluminum pads formed on an upper surface of the substrate,
복수개의 납패드와,A plurality of lead pads,
복수개의 납패드 또는 금패드와;A plurality of lead pads or gold pads;
상기 기관 상면에 형성된 복수개의 제 1배선 패턴 및 복수개의 제 2배선 패턴과;A plurality of first wiring patterns and a plurality of second wiring patterns formed on the upper surface of the engine;
상기 기판 상면에 정착된 복수개의 플립칩과;A plurality of flip chips fixed to an upper surface of the substrate;
상기 기판의 각면에 이격되어 정렬·배치된 복수개의 리드와; 상A plurality of leads arranged and spaced apart from each side of the substrate; Prize
기 칩들이 탑재된 기판을 기계적으로 고정하기 위해 그 기판의 각 모서리에 가로방향으로 정렬·배치된 더미리드(dummy lead)를 포함하는 것을 특징으로 하는 패드리스(padless) 리드프레임을 적용한 멀티칩 패키지를 제공한다.Multi-chip package with a padless leadframe comprising a dummy lead horizontally aligned and arranged at each corner of the substrate to mechanically fix the substrate on which the chips are mounted To provide.
또한, 상기 목적을 달성하기 위하여,In addition, in order to achieve the above object,
단일칩을 적용한 플라스틱 패키지에 있어서,In a plastic package with a single chip,
칩과;A chip;
상기 칩 상면에 형성된 복수개의 알루미늄 패드와,A plurality of aluminum pads formed on an upper surface of the chip;
복수개의 납패드 또는 금패드와;A plurality of lead pads or gold pads;
상기 칩의 각면에 이격되어 정렬·배치된 복수개의 리드와;A plurality of leads arranged and spaced apart from each side of the chip;
상기 칩을 기계적으로 고정하기 위해 그 칩의 각 모서리에 가로방향으로 정렬·배치된 더미리드(dummy lead)를 포함하는 것을 특징으로 하는 패드리스(padless) 리드프레임을 적용한 단일칩 패키지를 제공한다.In order to mechanically fix the chip, there is provided a single chip package to which a padless lead frame is applied, including a dummy lead horizontally aligned and arranged at each corner of the chip.
이하, 첨부 도면을 참조하여 본 발명을 보다 상세하게 설명하고자 한다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.
제2도는 본 발명에 따른 패드리스 리드프레임의 평면도이다. 제2도를 참조하면, 패드리스 리드프레임(200) 내에 형성된 기판면 또는 칩면(기판 상부 또는 칩의 상부를 도시하지 않은 부분)(100')에는 각 모서리 가로방향으로 더미리드(20)가 정렬·배치되어 있고, 상기 기판면 또는 칩면(100') 외부에 리드(30)는 상기 더미리드(20) 사이에 복수개 정렬·배치되어 있다. 또한, 상기 더미리드(20)과 상기 리드(30)는 제 2폴리며 테이프(110)에 의해 고정되어 있으며, 성형 공정에서 플래쉬(flash)의 발생을 방지하기 위한 댐바(18)가 형성되어 있다.2 is a plan view of a padless leadframe according to the present invention. Referring to FIG. 2, the dummy leads 20 are aligned on the substrate surface or the chip surface (part not shown in the upper substrate or the upper portion of the chip) 100 ′ formed in the padless lead frame 200 in the horizontal direction of each corner. Arranged, a plurality of leads 30 are arranged and arranged between the dummy leads 20 outside the substrate surface or the chip surface 100 '. In addition, the dummy lead 20 and the lead 30 are fixed by the second poly and tape 110, and a dam bar 18 is formed to prevent the occurrence of flash in the forming process. .
상기 기판면(100') 상·하부에는 세로방향으로 복수개의 리드(30)가 정렬·배치되고, 상기 리드(30)는 제 2폴리머 테이프(110)에 의해 고종되어 있다.A plurality of leads 30 are aligned and arranged in the vertical direction on the upper and lower portions of the substrate surface 100 ′, and the leads 30 are held by the second polymer tape 110.
상기 패드리스 리드프레임(200)의 좌·우 말단에는 복수개의 인덱스 홀(120)이 형성되어 있다.A plurality of index holes 120 are formed at left and right ends of the padless lead frame 200.
제3도는 본 발명에 따른 제1 실시예로써, 패드리스 리드프레임을 적용한 멀티칩 패키지의 사시도이다.3 is a perspective view of a multichip package to which a padless lead frame is applied according to a first embodiment according to the present invention.
제4도는 제3도의 A-A' 계단단면도이다.4 is a cross-sectional view taken along the line A-A 'of FIG.
제5도는 제4도 A부분의 확대도이다.FIG. 5 is an enlarged view of portion A of FIG. 4.
제6도는 본 발명에 따른 멀티칩이 장착되는 기판의 평면도이다. 제2도 내지 제6도를 참조하면, 비활성화층(SiO2 또는 포리머 테이프)(104)과 유전층(102)이 순차적층되어 있는 상기 기판(100) 상면은, 복수개의 납패드 또는 금패드(22), 복수개의 알루미늄 패드(34) 및 복수개의 납패드(12)가 형성되어 있고, 또한 복수개의 제1배선 패턴(14) 및 복수개의 제2배선 패턴(16)이 형성되어 있다.6 is a plan view of a substrate on which a multichip according to the present invention is mounted. 2 to 6, the top surface of the substrate 100 on which the passivation layer (SiO 2 or polymer tape) 104 and the dielectric layer 102 are sequentially stacked may include a plurality of lead pads or gold pads 22. A plurality of aluminum pads 34 and a plurality of lead pads 12 are formed, and a plurality of first wiring patterns 14 and a plurality of second wiring patterns 16 are formed.
상기 기판(100)의 각 모서리 가로방향으로 더미리드(20)가 정렬·배치되어 있고, 상기 기판(100) 외부에 리드(30)는 상기 더미리드(20) 사이에 복수개 정렬·배치되어 있다. 또한, 상기 더미리드(20)과 상기 리드(30)는 제2폴리머 테이프(110)에 의해 고정되어 있다. 상기 기판(100) 상·하부에는 세로방향으로 복수개의 리드(30)가 배치되고, 또한 상기 리드(30)는 제2폴리머 테이프(110)에 의해 고정되어 있다.The dummy leads 20 are aligned and arranged in the horizontal direction of each corner of the substrate 100, and a plurality of leads 30 are arranged and arranged between the dummy leads 20 outside the substrate 100. In addition, the dummy lead 20 and the lid 30 are fixed by the second polymer tape 110. A plurality of leads 30 are disposed in the vertical direction above and below the substrate 100, and the leads 30 are fixed by the second polymer tape 110.
플립칩(10)과 상기 기판(100)상에 형성된 복수개의 납패드(12)는 복수개의 납범프(11)에 의해서 연결되어 있고, 상기 납패드(12)와 다른 플립칩(10)에 연결된 납패드(12)는 상기 제1배선 패턴(14)에 의해서 전기적으로 연결되며, 상기 납패드(12)와 상기 알루미늄 패드(34)는 상기 제2배선 패턴(16)에 의해서 전기적으로 연결되어 있다.The flip chip 10 and the plurality of lead pads 12 formed on the substrate 100 are connected by a plurality of lead bumps 11 and are connected to the lead pad 12 and another flip chip 10. The lead pad 12 is electrically connected by the first wiring pattern 14, and the lead pad 12 and the aluminum pad 34 are electrically connected by the second wiring pattern 16. .
상기 더미리드(20)와 상기 납패드 또는 금범프(21)는 상기 납범프 또는 금패드(22)에 의해서 연결되어 있다. 상기 더미리드(20)는 기판쪽 말단 하부에 납 도금막(25)과 상기 납 도금막(25)의 기판 반대방향 일부 부분에 솔더링 공정에 있어서, 납이 리드를 따라 확산되는 것을 막는 제1폴리머 테이프(23)를 포함한다.The dummy lead 20 and the lead pad or gold bump 21 are connected by the lead bump or gold pad 22. The dummy lead 20 has a first polymer which prevents lead from being diffused along the lead in the soldering process in the lead plating film 25 and a portion of the lead plating film 25 opposite to the substrate at the lower end of the substrate side. Tape 23.
또한, 리드(30)와 상기 알루미늄 패드(34)는 와이어(40)에 의해 스티치 본딩되어 있다.In addition, the lead 30 and the aluminum pad 34 are stitch bonded by a wire 40.
제7도는 본 발명에 따른 제2실시예로써, 패드리스 리드프레임을 적용한 단일칩 패키지의 사시도이다.7 is a perspective view of a single chip package to which a padless lead frame is applied according to a second embodiment according to the present invention.
제8도는 제7도의 B-B' 계단단면도이다.8 is a cross-sectional view taken along the line B-B 'of FIG.
제9도는 제8도 B부분의 확대도이다.9 is an enlarged view of a portion B of FIG. 8.
제10도는 본 발명에 따른 단일칩의 평면도이다. 제7도 내지 제10도를 참조하면, 침(10') 상면은, 복수개의 납패드 또는 금패드(22), 복수개의 알루미늄 패드(34) 및 복수개의 납패드(12)가 형성되어 있다.10 is a plan view of a single chip according to the present invention. 7 to 10, a plurality of lead pads or gold pads 22, a plurality of aluminum pads 34, and a plurality of lead pads 12 are formed on the upper surface of the needle 10 ′.
상기 칩(10')의 각 모서리 가로방향으로 더미리드(20)가 배치되어 있고, 상기 폴립칩(10) 외부에 리드(30)는 상기 더미리드(20) 사이에 복수개 정렬·배치되어 있다. 또한, 상기 더미리드(20)과 상기 리드(30)는 제2폴리머 테이프(110)에 의해 고정되어 있다. 상기 칩(10') 상·하부에는 세로방향으로 복수개의 리드(30)가 배치되고, 상기 복수개의 리드(30)는 제2 폴리머 테이프(110)에 의해 고정되어 있다.The dummy leads 20 are arranged in the horizontal direction of each corner of the chip 10 ', and a plurality of leads 30 are arranged and arranged between the dummy leads 20 outside the polyp chip 10. In addition, the dummy lead 20 and the lid 30 are fixed by the second polymer tape 110. A plurality of leads 30 are arranged in the vertical direction above and below the chip 10 ', and the plurality of leads 30 are fixed by the second polymer tape 110.
상기 더미리드(20)와 상기 납패드 또는 금범프(21)는 상기 납범프 또는 금패드(22)에 의해서 연결되어 있다. 상기 더미리드(20)는 기판쪽 말단 하부에 납 도금막(25)과 상기 납 도금막(25)의 기판 반대쪽 일부 부분에 솔더링 공정에 있어서, 납이 리드를 따라 확산되는 것을 막는 제1폴리머 테이프(23)을 포함한다.The dummy lead 20 and the lead pad or gold bump 21 are connected by the lead bump or gold pad 22. The dummy lead 20 has a first polymer tape that prevents lead from being diffused along the lead in the soldering process on the lead plated film 25 and a portion of the lead plated film 25 opposite to the substrate at the lower end of the substrate side. And (23).
또한, 리드(30)와 상기 알루미늄 패드(34)는 와이어(40)에 의해 스티치 본딩되어 있다.In addition, the lead 30 and the aluminum pad 34 are stitch bonded by a wire 40.
또한, 본 발명에 있어서 더미리드의 위치나 갯수는 변형·실시가 가능하다.In addition, in this invention, the position and number of dummy leads can be modified and implemented.
전술한 본 발명에서, 패드리스 리드프레임을 이용함으로써 다음과 같은 단점이 제거할 수 있다.In the present invention described above, the following disadvantages can be eliminated by using a padless lead frame.
칩을 리드프레임에 접착제로 접착시켜 조립한 경우에 신뢰성을 확보하기가 어렵다. 그 이유는, 흡습에 의한 아이·알 리플로우(IR-REFLOW)될 때에 있어서, 은 엑폭시(Ag Epoxy)를 도팅한 부분과 기판 또는 칩, 즉 기판 또는 칩 및 리드프레임 패드 또는 리드프레임 패드의 배면 및 성형수지의 계면에서 패키지의 크랙이 발생되거나, 열을 주기적으로 가할 때(Thermal cycle)에 잔류응력의 집중에 의한 불량이 발생된다. 또한, 패키지에 실장되는 칩의 크기를 크게하거나, 또는 칩의 점유율이 증가할수록 더욱 심하게 된다.It is difficult to secure the reliability when the chip is assembled by bonding the adhesive to the lead frame. The reason for this is that in the case of IR-REFLOW due to moisture absorption, the portions doped with silver epoxy (Ag Epoxy) and the substrate or chip, that is, the substrate or chip, and the lead frame pad or lead frame pad Cracks in the package occur at the interface between the back and the molding resin, or defects due to concentration of residual stresses occur when heat is periodically applied (Thermal cycle). In addition, as the size of the chip mounted in the package is increased or the share of the chip increases, it becomes more severe.
따라서, 본 발명은 더미리드를 복수개 정착함으로써, 기판 또는 칩과 리드프레임을 기계적으로 견고히 고정할 수 있다.Therefore, in the present invention, by fixing a plurality of dummy leads, it is possible to mechanically fix the substrate or the chip and the lead frame.
또한, 다이접착 공정을 없앰으로써 작업의 단순화할 수 있어, 제조비용이 저렴하게 할 수 있다.In addition, the work can be simplified by eliminating the die bonding step, and the manufacturing cost can be made low.
본 발명에 의한 구조에 따르면, 리드프레임 패드를 없애고 리드에 기판과 리드프레임을 기계적으로 연결할 수 있는 더미리드를 갖고, 기판상에 더미범프 패드를 만들어, 리드프레임과 기판을 접착시켜 접착제로 접착하는 다이접착공정을 없앰으로써, 패키지 공정을 단순화시키고 리드프레임 패드에서 발생하는 패키지 불량을 방지하여 신뢰성을 개선하는 이점(利點)이 있다.According to the structure according to the present invention, the lead frame has a dummy lead to remove the lead frame pad and mechanically connect the substrate and the lead frame to the lead, to make a dummy bump pad on the substrate, to adhere the lead frame and the substrate by adhesive By eliminating the die bonding process, there is an advantage of improving the reliability by simplifying the packaging process and preventing package defects occurring in the leadframe pad.
Claims (30)
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