KR0140809B1 - Forming method of isosation film on semiconductor device - Google Patents
Forming method of isosation film on semiconductor deviceInfo
- Publication number
- KR0140809B1 KR0140809B1 KR1019940013034A KR19940013034A KR0140809B1 KR 0140809 B1 KR0140809 B1 KR 0140809B1 KR 1019940013034 A KR1019940013034 A KR 1019940013034A KR 19940013034 A KR19940013034 A KR 19940013034A KR 0140809 B1 KR0140809 B1 KR 0140809B1
- Authority
- KR
- South Korea
- Prior art keywords
- film
- oxide film
- forming
- semiconductor device
- polysilicon film
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 36
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 19
- 229920005591 polysilicon Polymers 0.000 claims abstract description 19
- 238000002955 isolation Methods 0.000 claims abstract description 13
- 150000004767 nitrides Chemical class 0.000 claims abstract description 11
- 238000001039 wet etching Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 230000001590 oxidative effect Effects 0.000 claims abstract description 3
- 238000009792 diffusion process Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003963 antioxidant agent Substances 0.000 description 1
- 230000003078 antioxidant effect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Element Separation (AREA)
- Local Oxidation Of Silicon (AREA)
Abstract
산화막/완충 폴리실리콘막/질화막의 3중막을 확산마스크층으로 사용하는 PBL구조를 갖는 반도체 소자의 분리막 형성방법에 있어서, 소자분리막 형성후 질화막을 제거하는 단계;활성영역의 상기 완충 폴리실리콘막을 산화시켜 습식 식각의 방법으로 제거하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 분리막 형성방법에 관한 것으로, 활성영역의 기판 손상이 작기 때문에 차후 공정에서 형성되는 게이트산화막의 특성이 향상되어 반도체 소자의 수율 및 수명 향상을 도모할 것으로 기대되며 또한 게이트산화막 형성공정 전에 진행되는 희생 산화막 공정에 본 발명의 방법이 포함되기 때문에 완충 폴리실리콘막 제거공정을 생략할 수 있어 1단계의 공정을 줄일 수 있을 뿐만 아니라 활성영역과 필드사이의 단차가 감소하여 패턴형ㅎ성공정이 쉬워지는 효과를 갖는다.A method of forming a separator of a semiconductor device having a PBL structure using a triple layer of an oxide film / buffered polysilicon film / nitride film as a diffusion mask layer, the method comprising: removing a nitride film after forming the device isolation film; oxidizing the buffer polysilicon film in an active region A method of forming a separator of a semiconductor device comprising the step of removing by a wet etching method, the characteristics of the gate oxide film formed in a subsequent process is improved because the damage of the substrate in the active region is small It is expected to improve the yield and lifespan, and the buffer polysilicon film removal process can be omitted because the method of the present invention is included in the sacrificial oxide process performed before the gate oxide film forming process, thereby reducing the one-step process. Rather, the pattern between the active area and the field is reduced. It has the effect of easy success.
Description
제1A도 내지 제1E도는 본 발명의 일실시예에 따른 소자 분리막 형성 공정 단면도.1A to 1E are cross-sectional views of a device isolation film forming process according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
1:실리콘 기판 2:패드 산화막1: Silicon substrate 2: Pad oxide film
3:완충 폴리실리콘막 4:질화막3: buffer polysilicon film 4: nitride film
5:필드 산화막 6:산화막5: Field oxide film 6: Oxide film
본 발명은 반도체 제조 분야에 관한 것으로, 특히 반도체 장치의 소자 분리 공정에 관한 것이며, 더 자세히는 완충 폴리실리콘막을 이용하는 PBL(Poly Buffered LOCOS) 공정에 관한 것이다.TECHNICAL FIELD The present invention relates to the field of semiconductor manufacturing, and more particularly, to a device isolation process of a semiconductor device, and more particularly, to a PBL (Poly Buffered LOCOS) process using a buffer polysilicon film.
PBL(Poly Buffered LOCOS) 공정은 패드 산화막/완충 폴리실리콘막/질화막의 3중막을 소자 분리 마스크로 사용하는 개선된 LOCOS 공정으로, 완충 폴리실리콘막에 의해 버즈 비크(bird's beak)를 크게 감소시킴으로써 활성 영역의 확보에 유리하기 때문에 일반화되어 널리 사용되고 있다.The PBL (Poly Buffered LOCOS) process is an improved LOCOS process that uses a triple layer of pad oxide / buffered polysilicon film / nitride as the device isolation mask. Since it is advantageous to secure an area, it is generalized and widely used.
종래에는 이러한 PBL 공정에서 소자 분리 마스크로 사용된 완충 폴리실리콘막을 플라즈마 식각 또는 습식 식각 등의 방법을 사용하여 제거하여 왔다.Conventionally, the buffer polysilicon film used as the device isolation mask in the PBL process has been removed using a method such as plasma etching or wet etching.
먼저, 플라즈마 방식을 사용하여 완충 폴리실리콘막을 식각하는 경우, 플라즈마가 활성 영역에 손상을 입히게 되고, 이에 따라 후속 공정에 의해 형성되는 게이트 산화막의 특성을 열화시키는 문제점이 있었다.First, when the buffer polysilicon film is etched using the plasma method, the plasma damages the active region, thereby degrading the characteristics of the gate oxide film formed by a subsequent process.
다음으로, 습식 식각의 방식을 사용하여 완충 폴리실리콘막을 식각하는 경우에는 폴리실리콘의 식각 속도가 느리고 식각 균일도가 불량하여 생산성을 저하시키는 문제점이 있었다.Next, when the buffered polysilicon film is etched using the wet etching method, the etching speed of the polysilicon is slow and the etching uniformity is poor, thereby lowering productivity.
상기 문제점을 해결하기 위하여 안출된 본 발명은 소자 분리 공정의 일부로서의 완충 폴리실리콘막 제거시 기판 손상을 최소화하며, 생산성을 향상시키는 소자 분리막 형성방법을 제공하는데 그 목적이 있다.The present invention devised to solve the above problems is to provide a device isolation film forming method for minimizing substrate damage and improving productivity when removing the buffer polysilicon film as part of the device isolation process.
상기 목적을 달성하기 위하여 본 발명의 반도체 장치의 소자 분리막 형성방법은 반도체 기판의 소정 부분에 패터닝 되어 차례로 적층된 패드 산화막, 완충 폴리실리콘막 및 질화막을 소자 분리 마스크로 하여 필드 산화막을 형성하는 단계;상기 질화막을 제거하는 단계;상기 완충 폴리실리콘막을 열산화시켜 산화막을 형성하는 단계;및 상기 산화막을 습식 식각하는 단계를 포함하여 이루어진다.In order to achieve the above object, the device isolation film forming method of the semiconductor device of the present invention comprises: forming a field oxide film using a pad oxide film, a buffer polysilicon film, and a nitride film sequentially patterned on a predetermined portion of a semiconductor substrate as a device isolation mask; Removing the nitride layer; thermally oxidizing the buffer polysilicon layer to form an oxide layer; and wet etching the oxide layer.
이하, 첨부된 도면 제1A도 내지 제1E도를 참조하여 본 발명의 일실시예를 상세히 설명한다.Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 1A to 1E.
먼저, 제1A도에 도시된 바와 같이 실리콘 기판(1) 상에 패드 산화막(2) 및 완충 폴리실리콘막(3)을 차례로 증착한다음, 그 상부에 산화 억제층으로서 질화막(4)을 증착한다.First, as shown in FIG. 1A, the pad oxide film 2 and the buffer polysilicon film 3 are sequentially deposited on the silicon substrate 1, and then the nitride film 4 is deposited as an oxidation inhibiting layer thereon. .
이어서, 제1B도에 도시된 바와 같이 질화막(4), 완충 폴리실리콘막(3) 및 패드 산화막(2)을 선택적으로 식각하여 소자 분리 영역 및 활성 영역을 정의하기 위한 산화 방지막 패턴을 형성한다.Subsequently, as shown in FIG. 1B, the nitride film 4, the buffer polysilicon film 3, and the pad oxide film 2 are selectively etched to form an antioxidant pattern for defining device isolation regions and active regions.
다음으로, 제1C도에 도시된 바와 같이 실리콘 기판(1)의 열산화 공정을 실시하여 필드 산화막(5)을 형성하고, 계속하여 질화막(4)을 제거한다.Next, as shown in FIG. 1C, a thermal oxidation process of the silicon substrate 1 is performed to form the field oxide film 5, and the nitride film 4 is subsequently removed.
그리고, 제1D도에 도시된 바와 같이 열산화 공정을 진행하여 완충 폴리실리콘막(3)을 산화시킴으로써 산화막(6)을 형성한다.Then, as shown in FIG. 1D, a thermal oxidation process is performed to oxidize the buffer polysilicon film 3 to form the oxide film 6.
끝으로, 제1E도에 도시된 바와 같이 산화막(6) 및 필드 산화막(5)을 통상적인 산화막 습식 식각 방식을 사용하여 식각한다. 이때, 산화막(6)은 완전한 제거가 이루어짐과 동시에 필드 산화막(6) 상부의 일부가 식각되는데, 이러한 필드 산화막(6)의 부분 식각은 후속 사진 공정을 어렵게 하는 소자 분리 영역과 활성 영역간의 단차를 완화하는 역할을 하게 된다. 또한, 산화막의 습식 식각 속도가 종래의 폴리실리콘막 습식 식각에 비해 빠른 장점을 가지고 있으며, 게이트 산화막 형성 전에 일반적으로 행해지는 희생 산화막 형성 및 제거공정을 생략할 수 있다.Finally, as shown in FIG. 1E, the oxide film 6 and the field oxide film 5 are etched using a conventional oxide wet etching method. At this time, the oxide film 6 is completely removed, and at the same time, a portion of the upper portion of the field oxide film 6 is etched. This partial etching of the field oxide film 6 provides a step between the device isolation region and the active region, which makes it difficult to perform a subsequent photographic process. It will play a mitigating role. In addition, the wet etching rate of the oxide film is faster than the conventional polysilicon wet etching process, and the sacrificial oxide film formation and removal process that is generally performed before the gate oxide film formation can be omitted.
상기와 같이 이루어지는 본 발명은 활성 영역의 기판 손상이 적기 때문에 후속공정에 의해 형성되는 게이트 산화막의 특성이 향상되어 반도체 장치의 수율 및 수명 향상을 도모할 것으로 기대되며, 후속 희생 산화막 공정을 생략할 수 있으며 활성 영역과 소자 분리 영역간의 단차를 감소시켜 후속 사진 공정을 용이하게 하므로 생산성 향상을기대할 수 있다.The present invention made as described above is expected to improve the yield and lifespan of the semiconductor device by improving the characteristics of the gate oxide film formed by the subsequent process because of less damage to the substrate in the active region, it is possible to omit the subsequent sacrificial oxide film process In addition, productivity improvements can be expected by reducing the step between the active and device isolation regions to facilitate subsequent photographic processes.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940013034A KR0140809B1 (en) | 1994-06-09 | 1994-06-09 | Forming method of isosation film on semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940013034A KR0140809B1 (en) | 1994-06-09 | 1994-06-09 | Forming method of isosation film on semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960002736A KR960002736A (en) | 1996-01-26 |
| KR0140809B1 true KR0140809B1 (en) | 1998-07-15 |
Family
ID=19385040
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019940013034A KR0140809B1 (en) | 1994-06-09 | 1994-06-09 | Forming method of isosation film on semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0140809B1 (en) |
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1994
- 1994-06-09 KR KR1019940013034A patent/KR0140809B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR960002736A (en) | 1996-01-26 |
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