KR0140304B1 - Apparatus for matching protocol analyzer - Google Patents

Abstract

The present invention relates to a protocol analyzer matching device for matching a protocol analyzer for monitoring or emulating a communication protocol between blocks performed through a time slot of a western highway to a corresponding block in an electronic switchboard. The present invention relates to a protocol analyzer matching device that performs a matching function between a corresponding slot of a related block and a chromatograph analyzer in which a western highway enters so that a protocol execution between related blocks can be performed properly. Therefore, the present invention plays an important role in system development and maintenance because the data is extracted from the subhighway or introduced into the west high by specifying an arbitrary time slot in the circuit pack for transmitting and receiving data through the west highway of the electronic switchboard. Can be done.

Description

Protocol Analyzer Matching Device

1 is a block diagram of a conventional protocol analyzer matching device

2 is a block diagram of a protocol analyzer matching device according to the present invention

3 is an operating state diagram of the loopback function selection unit of FIG.

4 is a detailed configuration diagram of the matching block selection unit of FIG.

FIG. 5 is a detailed configuration diagram of the time slot selection unit of FIG.

6 is a signal waveform diagram of each part of FIG.

7 is a detailed configuration diagram of the signal converter of FIG. 2

8 is a detailed block diagram of the clock generator of FIG.

* Explanation of symbols for the main parts of the drawings

201: Sub highway inlet block 202: Loopback function selector

203: Matching block selector 204: RS422 converter

205: time slot selector 206: signal converter

207: RS232C converter 208: clock generator

209: mode selector 210: protocol analyzer

301,302,303,304: Module 305,306,307,308: DIP switch

501: comparator 601, 603: shift register

602: latch 701: oscillator

702: Divider circuit 703,704: D-flop

705: inverter 706: and gate

The present invention relates to a protocol analyzer matching device for matching a protocol analyzer for monitoring or emulating a communication protocol between blocks executed in a sub-highway in an electronic switch in a corresponding block. The present invention relates to a protocol analyzer matching device that performs a matching function between a corresponding slot of a related block and a protocol analysis of a sub-HAI to be entered through a monitor and emulation to determine whether protocol execution between related blocks is performed properly.

1 is a block diagram of a conventional protocol analyzer matching device.

The conventional protocol analyzer matching device for matching the protocol analyzer to monitor the protocol being performed through the time slots of the sub-highway 101 of the electronic switchboard has a western highway matching unit (shown in FIG. 1). 102, a time slot matching section 103, a time slot designation section 107, an RS232C conversion section 104, and a protocol analyzer matching section 105 to perform a protocol performed only through the sub-highway. It is designed to monitor with).

However, the conventional crotocol analyzer matching device is not only available online because it cannot perform the emulation function that can be tested with the crotocol analyzer, and it is impossible to determine whether each block performs the correct protocol. In terms of efficiency, there was a problem.

Accordingly, an object of the present invention is to provide a crotocol analyzer matching device serving as an intermediary with a crotocol analyzer so as to monitor a communication protocol of each block that is performed through a sub highway on an online of an electronic switching system.

Another object of the present invention is to emulate, on-line, whether each block constituting the electronic switchboard normally performs port calls, so that each block can be used to test each block so that it can be operated in the whole system. A protocol analyzer matching device is provided.

It is still another object of the present invention to add a function of a device required for loopback testing of a PHCA PBA (Pack Handling Control Board Assembly) constituting an ISDN Electronic Switching System (TDX) -10) DML Packet Handling Module (PHN) block. To provide a protocol analyzer matching device that provides the test environment required for testing or pba testing.

A protocol analyzer matching device according to the present invention for achieving the above objects includes a matching block selection unit for selectively matching a sub-highway signal to the input block, a block, a frame synchronization signal, and a transmission data line during the PBA self loopback test. A loopback function selector for selectively providing a connection device for looping back to a receiving data line, an RD422 converter connected to the matching block selector to convert an RS422 type signal and a TTL level signal to each other, and a sub highway A time slot selector for extracting or inserting data of a corresponding time slot by designating one time slot among 32 time slots of the second time slot, and specifying 2Mbps data of a time slot selected from the time slot selector and outputted from the RS422 converter; Signal side converts to 2Mbps data for insertion into time slot An RS232C converter connected to the signal converter and the protocol analyzer to convert TTL level signals and RS232C signals to each other, a mode selection unit for selecting one of a monitor function and an emulation function of the protocol analyzer; And a clock generator configured to generate a clock and a frame synchronization signal required during an emulation function test performed offline under the control of the mode selector.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a protocol analyzer matching device according to the present invention.

The protocol analyzer matching device according to the present invention includes a time slot selector for converting data of a designated time slot into a signal that can be interpreted by a chromatograph analyzer, as shown in FIG. 205, a signal converter 206, an RS422 converter 204, and an RS232C converter 207, which can be implemented offline with the mode selector 209 to perform a protocol emulation function. There is a clock generator 208 for generating a frame synchronization signal, and a matching block selector 203 for selectively using an arbitrary block and a loopback function selector 202 for a PBA self-loopback test.

The clock, frame synchronization signal, and transmission / reception data of the sub highway of the electronic switching system are configured with different slots for each block. Accordingly, the matching block selector 203 can selectively match the block to which the sub highway signal is input.

The loopback function selector 202 selectively provides a connection device for looping back blocks, frame synchronization signals, and transmit data lines to the receive data lines during the self loopback test of the PHCA PCA test items of the PHM block of the electronic switch. will be. That is, as shown in FIG. 3, the clock and frame synchronization signals output from the clock generator 208 are transmitted through the RD422 converter 204 to transmit terminals TX (+) and TX (−) of the corresponding slots of the PHM block. In this case, the loopback function selector 202 connects the transmitting terminals TX (+) and Tx (-) to the corresponding receiving terminals Rx (+) and Rx (-) through a switching operation. .

The RS422 converter 204 is connected to the matching block selector 203 to convert the RS422 signal into a TTL level signal. That is, the RS422 signal of the sub highway is converted into the TTL level, and the TTL level signal output from the signal converter 206 is converted into the RS422 signal, which is implemented as a line driver and a receiver.

The timeslot selector 205 designates one timeslot among the 32 timeslots of the subhighway to extract or import data of the corresponding timeslot. The user selects an arbitrary timeslot by a combination of 5-bit history data. In this case, only data of the corresponding time slot can be extracted or data can be inserted into the corresponding time slot.

The signal converter 206 converts 2Mbps data of the time slot selected by the RS422 converter 204 and the time slot selector 205 into 64Kbps data and inserts 64Kbps data generated by the protocol analyzer into the designated time slot. To 2Mbps data.

The RS232C converter 207 is connected to the signal converter 206 and the protocol analyzer to convert the TTL level signal and the RD232C signal. That is, since the protocol analyzer realizes the interface with the outside through the RS232C method, it is necessary to change the signal level between the signal converter 206 and the interface. The TTL level signal output from 206) is converted into the RS232C signal, and the RS232C signal output from the protocol analyzer is converted into the TTL level.

The mode selector 209 selects one of a protocol analyzer's monitor function and an emulation function, and can be simply implemented with a jumper strap. When testing with the monitor function, the test should be done online so that the clock, frame sync signal and transmit / receive data are all provided from the sub highway. Therefore, the signal generated by the clock generator 208 has no meaning here. On the other hand, if you want to test with the emulation function, because the test must be done off-line, it is not possible to receive clock, frame sync signal, and transmit / receive data from the Sum highway. In this case, the clock generator 208 receives the clock and frame synchronization signal and implements the circuit using 64 Kbps data generated by the protocol analyzer as the transmission data and 2 Mbps data generated in the block to be tested as the received data. do.

As such, the mode is selected by connecting and disconnecting signal lines appropriately for two situations.

The clock generator 208 generates a clock and a flame synchronization signal required for the emulation function test performed offline according to the control of the mode selector 209.

The detailed structure of the protocol analyzer matching equipment comprised in this way is demonstrated.

As shown in FIG. 4, the matching block selector 203 includes four 8-bit DIP switches 305, 306, 307, and 308 connected to each slot of a block into which a sub highway signal is input. The 8-bit DIP male position consists of an 8-bit DIP switch for matching a PHM block. In addition, any block having an incoming sub-highway signal mapped to the same pin can be used. The time slot selector 205 compares the 5-bit data inputted by the user with the divided 128KHz clock, 64KHz clock, 32KHz clock, 16KHz clock and 8KHz clock in the same case as shown in FIG. And a comparator 501 for generating a slot enable signal.

The operation of the time slot selector 205 thus configured will be described with reference to FIG.

The user selects 32 values from 0 to 31 using the 5-bit DIP position and inputs them to the comparator 501, and also applies 64KHz clock, 32KHz clock, 16KHz clock and 8KHz clock. As shown in FIG. 6, the comparator 501 generates a time slot enable signal only when the values for each of 5 bits are the same, and accordingly extracts data of only a time slot selected by a user, or the time slot. User data can be inserted into.

The signal converter 206 is a shift register output from the RS422 converter 204 and converts 2 Mbps serial data of the time slot selected by the time slot selector 205 into 8-bit parallel data as shown in FIG. 601), a latch 602 for latching only data of the corresponding time slot among the data output from the shift register 601, and data output from the latch 602 are converted into 64 Kbs serial data to the RS232C conversion unit 207. The shift register 603 is configured to convert 2 Mbps data of the time slot selected by the time slot selector 205 into 64 Kbps data. Shift register to convert to 8-bit historical data, latched to insert 8-bit parallel data output from the shift register into the corresponding timeslot Converts the 8-bit parallel data output from the latch and latch data in series to the 2Mpbs it consists of a shift register for outputting a RS422 conversion unit 204. The Therefore, it consists of a circuit for introducing 64Mbps data generated by the protocol analyzer into 2Mbps data in a designated time slot. The serial data of the sub highway received at 2 Mbps is converted into 8-bit parallel data in the shift register 601 and then only the data of the corresponding time slot is latched in the latch 602. Subsequently, the shift register 603 converts the data into 64 Mbps serial data and outputs the RS232C converter 207.

Conversely, converting 64 kbps data into 2 Mbps data and inserting it into the corresponding timeslot may be performed by configuring a circuit in the reverse form. That is, the 64 Kbps serial data generated by the protocol analyzer and outputted from the RS232C conversion unit 207 is converted into 8-bit history data in the shift register, latched in the latch to be inserted into the corresponding timeslot, and 2MPS in the shift register again. The data is converted into serial data and output to the RS422 conversion unit 204.

The clock generator 208 divides the oscillator 701 generating a 4.096 MHz clock and the 4.096 MHz clock outputted from the oscillator 701 to generate a 2 MHz clock and an 8 MHz clock as shown in FIG. 702, a D flip-flop 703 whose 8MHz clock output from the frequency divider circuit 702 is a data input and a clock input of the 2 MHz clock, and a data output of the D flip-flop 703 as a data input The D flip-flop 704 having a clock as a clock input, the inverter 705 for inverting the signal output from the D flip-flop 704, and the AND signal output from the D flip-flop 703 and the inverter 705 And gate 706.

The 4.096 MHz clock generated by the oscillator 701 is divided into a 2 MHz clock and an 8 MHz through the division circuit 702 implemented as a counter and outputted.

The 8 MHz clock is inverted by the inverter 705 past the D flip flops 703 and 704 with a 2 MHz clock as the clock input and then logically multiplied at the AND gate 706 with the output of the D flip flop 703 to achieve the desired 8 MHz frame sync. It is output as a signal.

As described above, the present invention designates an arbitrary time slot in a circuit pack that transmits and receives data through sub-highway of the electronic switchboard, and extracts data from the sub-highway or inserts the data into the sub-highway. It has the effect of playing an important role.

Claims (6)

It provides a matching block selector for selectively matching the western highway signal to the input block, and a connection device for loopbacking the block, the frame synchronization signal and the transmission data line to the receiving data line during the PBA's own loopback test. A time slot of one of the 32 time slots of the RS422 converter and the sub-highway connected to the loopback function selector and the matching block selector for mutual conversion between RS422 type signals and TTL level signals; Time slot selector for extracting or importing data from the RS422 converter, and converts 2Mbps data of the time slot selected by the time slot selector into 64Kps data and inserts 64Kps data generated by the protocol analyzer into the designated time slot. A signal converter to convert 2Mbps data A mode selector and a mode selector configured to select one of a monitor function and an emulation function of an RS232C converter and a telecommunication protocol, which are connected to the signal converter and a protocol analyzer and convert between TTL level signals and RS232C signals. And a clock generator for generating a clock and frame synchronization signal required during an emulation function test performed offline. The protocol analyzer matching device of claim 1, wherein the matching block selector comprises four 8-bit DIP male positions connected to each slot of a block into which a sub highway signal is input. 3. The protocol analyzer matching device of claim 2, wherein the 8-bit DIP switch comprises an 8-bit DIP switch for matching PHM blocks, a DIP switch for matching FMXP blocks, and a DIP switch for matching TSL blocks. The time slot selector of claim 1, wherein the time slot selector compares 5-bit data input by a user with an applied divided 128KHZ clock, 64KHZ clock, 32KHZ clock, 16KHZ clock, and 8KHZ clock to generate a time slot enable signal. Protocol analyzer matching device composed of a comparator. The first shift register of claim 1, wherein the signal converter is output from the RS422 converter and is output from the first shift register and the first shift register for converting 2 Mbps serial data of a time slot selected by a time slot selector into 8-bit parallel data. The first latch latching only the data of the end time slot among the data, the second shift register for converting the data output from the first latch into 64 Kbps serial data and outputting the serial data to the RS232C converter, and the RS232C converter generated by the protocol analyzer. A third shift register for converting 64 Kbps serial data output from the 8-bit parallel data, and a second latch for latching 8-bit parallel data output from the third shift register to the corresponding timeslot and the second latch. 8-bit parallel data output as 2Mbps serial data Ring fourth protocol analyzer matching device consisting of a shift register for output to the RS422 conversion The clock generator of claim 1, wherein the clock generator divides the 4.096MHZ clock, the 4.096MHZ clock output from the oscillator to generate a 2MHZ clock and an 8KHZ clock, and an 8KHZ clock output from the frequency divider circuit. 1D flip-flop with data input and 2KHZ clock as clock input and 2D flip-flop with 2MHZ clock as input and signal output from 2D flip-flop as data input A protocol analyzer matching device comprising an inverter for inverting a signal and an AND gate for ANDing the signal output from the first flip-flop and the inverter