KR0145926B1 - Apparatus for extracting the monitoring data of packet link in the full electronic switching system between keyphones - Google Patents

Abstract

This data extracting device extracts data of packet data monitoring point for protocol analyzer to monitor on-line of electronic switchboard with packet handling function. To this end, the apparatus includes a signal matching unit for matching N data applied from a monitoring point determined on a packet link to a TTL level; For each of the data output from the signal matching unit according to the port selection control signal and the time slot selection control signal applied by the user, a time slot in which data to be transmitted is present is selected, and data transmitted through the selected time slot is predetermined. A speed conversion and time slot selection unit for converting and outputting the speed; A monitor point extracting unit which extracts data of at least four monitor points among data output from the speed converting and time slot selecting unit by a port selection control signal and an enable control signal applied by a user; It consists of a protocol analyzer matching unit that matches the data output from the monitor point extractor to a signal that can be analyzed by the protocol analyzer.

Description

Packet link monitoring data extraction device of all electronic switch

Figure 1 shows the packet data link structure in the premise exchanger,

2 is a block diagram of an apparatus for extracting monitoring data according to the present invention in an electronic switch having a packet data link structure as shown in FIG.

3 is a detailed circuit diagram of the signal matching unit shown in FIG.

FIG. 4 is a schematic circuit diagram of the AMI matching unit shown in FIG.

FIG. 5 is a detailed circuit diagram of the speed conversion and time slot selection unit shown in FIG.

FIG. 6 is a detailed circuit diagram of the first and second point converters shown in FIG.

7 is an operation timing diagram of FIG.

FIG. 8 is a detailed circuit diagram of the 7,8,9,10 point converter shown in FIG.

9 is an operation timing diagram of FIG.

10 is a timing diagram for a load signal provided to the shift register shown in FIG. 8;

FIG. 11 is a detailed circuit diagram of the monitor point extracting unit shown in FIG.

12 is a detailed circuit diagram of the protocol analyzer matching unit shown in FIG.

* Explanation of symbols for main parts of the drawings

201: signal matching unit 202: speed conversion and time slot selection unit

203: monitor point extracting unit 204: status display unit

205: protocol analyzer matching unit 206: protocol analyzer

The present invention relates to an apparatus for extracting monitoring data of an electronic switching system. In particular, in an electronic switching system providing a service on a packet basis, a protocol analyzer (eg For example, the present invention relates to a data extraction device for extracting data of a monitoring point on a packet data link for monitoring via PT500).

The electronic switch is electronicized to the control unit and the telephone line, and is provided with a subscriber station (Isdn Packet Data Terminal Equipment (IPDTE), 101, hereinafter referred to as IPDTE), and a subscriber interface circuit (BSI) to provide services on a packet basis. Interface, 102, hereinafter referred to as BSI), Time Switch (TSL (Time Switch Link), 103, 107 and below TSL), Packet Handling Module (PHM (Packet Handling Module), 105, hereinafter referred to as PHL), Central Data Link Packet data link structure as shown in FIG. 1 with functional blocks such as (CDL (Central Data Link), 106, hereinafter referred to as CDL), and Space Division Switch (SSW) (Space Switch, 104, hereinafter referred to as SSW). Has In the packet data link structure, the electronic switch has 10 monitoring points (or monitoring points) as shown in Table 1 below.

[Table 1] Electrical specification and connection diagram for 10 monitoring points.

In Table 1, TSIA (Time Slot Interchange Board Assembly) and TLIA (Time Switch Link Interface Board Assembly) are check data for TSL 103 shown in FIG. There are two cases where the data transfer rate is converted from 2.048MHz to 3.192MHz or changed from 8.192MHz to 2.048MHz. The checkpoints are divided to check them separately. TSIA transmits data at the aforementioned speed change. In this case, TLIA is a case of transmitting data at a speed change described later. IBBB stands for ISDN Basic Subscriber Backboard, PHBB stands for Packet Handling Backboard, TSBB stands for Time Switch Backboard, SMBB stands for Space Matrix Switch Backboard, and DLBB stands for Data Link Unit Backboard.

If an abnormal condition occurs during the packet service using the all-electronic switching system having such a checkpoint (monitoring point), the protocol analyzer must check the abnormality of the checkpoint shown in [Table 1] to accurately identify the error occurrence part. have. However, the protocol analyzer PT500 currently used has a limited interface port and a constant data input speed, so that it is impossible to analyze data of checkpoints on packet links having different specifications as shown in [Table 1]. There was this. As a result, it was difficult to monitor the performance of the packet protocol in the electronic switchboard, which made it difficult to maintain the system.

Accordingly, an object of the present invention is to provide a data extraction apparatus for extracting data of a monitoring point on a packet data link so that a protocol analyzer can monitor the on-line of an electronic switch having a packet handling function.

In order to achieve the above object, an apparatus according to the present invention comprises a switching system having a protocol analyzer for analyzing protocols of an all-electronic exchange and an all-electronic exchange that form a packet link between each function block to accommodate a packet handling function. An apparatus for extracting data to monitor whether a failure occurs on a packet link through a protocol analyzer in the signal analysis unit, Signal matching unit for matching the N data applied from the monitoring point specified on the packet link to the TTL level; For each of the N data output from the signal matching unit by the port selection control signal and the timeslot selection control signal applied by the user, the time slot in which the data to be transmitted exists is selected, and the data transmitted through the selected timeslot is selected. A speed conversion and time slot selection unit for converting and outputting at a predetermined speed; A monitor point extracting unit for extracting data of at least four monitor points from the N data output from the speed converting and time slot selecting unit by the port selection control signal and the enable control signal applied by the user; And a protocol analyzer matching unit for matching data output from the monitor point extractor to a signal that can be analyzed by the protocol analyzer.

Next, embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of an apparatus for extracting data of a checkpoint on a packet data link for monitoring by a protocol analyzer in an electronic switch which forms a packet data link between functional blocks online. 201, a speed conversion and time slot selection unit 202, a monitor point extraction unit 203, a status display unit 204, a protocol analyzer matching unit 205, and a protocol analyzer 206.

When data is applied from ten checkpoints as shown in Table 1, the data is transmitted to the signal matching unit 201. As shown in FIG. 3, the signal matching unit 201 includes an S-line port 301, a BSI port 302, a PHM port 303, a first TSL port 304 and 305, an SSW port 306, and a CDL. It consists of port 307, FP / CP port 308, AMI matching section 309 and a plurality of RS422 matching sections 310 to 316, respectively. .

That is, checkpoints 1 and 2 for checking between the IPDTE 101 and the BSI 102 are connected to the S-line port 301 because the connection method is S-line. Checkpoints 3 and 4 for checking between the BSI 102 and the TSL 103 are connected to the BSI port 302 because the connection method is connected through the ISDN basic subscriber backboard (IBBB). Checkpoints 5 and 6 for checking between the TSL 103 and the PHM 105 are connected via a packet handling back board (PHBB) 1 module to connect to the PHM port 303. In addition, checkpoint 7 is connected to the first TSL port 304 and checkpoint 8 is connected to the second TSL port 305 when checking between TLIA and TSIA classified according to the transmission rate conversion method in the TSL 103. do. When checking between the CDL 106 and the SSW 104, the checkpoint 9 is connected to the SSW port 306, and the checkpoint 10 is connected to the CDL port 307. And FP (Frame Pulse) and CP (Clock Pulse) generated during data transmission is connected to receive through the FP, CP port 308.

When data is applied through the ports connected in this way, the data is transmitted to the AMI matching unit 309 and the RS422 matching unit 310 provided in the next stage.

As shown in FIG. 4, the AMI matching unit 309 is composed of a transmission and reception matching unit 401 and 402 to independently transmit (TX) data and receive (RX) data for data applied through an S-line. Match with and print. In this case, the transmission / reception matching units 401 and 402 may be implemented with PEB2080, a chip dedicated to the S-line interface driven by 7.68 MHz. The matched 256Kbps data (SDO), the frame synchronization signal (FSC, 8KHz, hereinafter referred to as FSC), and the data clock signal (DCLK, 512KHz, hereinafter referred to as DCLK) output from the transmission matching unit 402 will be described later. The SDO, FSC, and DCLK of 256 Kbps matched to the point converting unit 501 and output from the receiving matching unit 401 are transmitted to the second point converting unit 502 described later.

Since the data through the remaining ports 302 to 308 except for the S-line port 301 is made of a differential signal of RS422 or RS485, it can be simply implemented using a differential line receiver. However, 96175 or 26LS32 is used for signals from the BSI (102), PHM (105), TSL (103), SSW (104), and CDL (106) functional blocks in order to inter-communicate with the line driving chip at the checkpoint point. In the NES block (not shown), the FP2 and CP2 signals provided through the FP and CP ports 308 are implemented using a 41LF line receiver.

As described in Table 1, when the matching is provided for the signals provided from the designated points, it is transmitted to the speed conversion and timeslot selection unit 202.

As shown in FIG. 5, the speed converting and timeslot selecting section 202 includes a first to ten point converting section 501 to 510, a time slot selecting control signal buffer 511, and a port selection control signal buffer 512. And a decoder 513, which converts and outputs 2.048 Mbps serial data and 8.192 Mbps parallel data applied from the matching units 309 to 315 of the signal matching unit 201 into 64 Kbps serial data.

That is, when the timeslot selection control signal and the port selection control signal are applied by the user, they are transmitted to the timeslot selection control signal buffer 511 and the port selection control signal buffer 512, respectively, and the timeslot selection control signal buffer 511. ) Is temporarily stored and then transmitted to the timeslot selection control terminal SEL of the first to ten-point conversion units 501 to 510. At this time, the timeslot selection control signal applied by the user is represented by 10 bits. Only the least significant bit (LSB) is transmitted to the first and second point converters 501 and 502, and the third to sixth point converters 503 to 507. Only the lower 5 bits are transmitted. The seventh to tenth point converters 508 to 510 transmit all 10 bits.

In addition, the port selection control signal applied by the user is temporarily stored in the buffer 512 for the port selection control signal, decoded by the decoder 513, and then the enable terminal (1 to 10) of the first to ten point converters 501 to 510. SEL_EN). At this time, the port selection control signal applied by the user is represented by 4 bits, and the decoder 513 is implemented as a 4 * 10 bit decoder.

As shown in FIG. 6, the first and second point converters 501 to 510 of FIG. 5 include a first latch 601, a divider 602, a serial / parallel (S / P) converter 603, The second latch 604 and the parallel-to-serial conversion unit 605 convert the data applied from the AMI matching unit 309 into 64 Kbps for output.

That is, when the FSC (8KHz) and the 525KHz DCLK having the period as shown in FIG. 7 are applied from the AMI matcher 309, it is transmitted to the divider 602, and is applied from the AMI matcher 309. SDO data of 256 Kbps is applied to the serial-to-parallel converter 603. The time slot selection control signal SEL applied from the time slot selection control signal buffer 511 and the port selection control signal SEL_EN applied from the decoder 513 are connected to the input signal of the first latch 601. Each is applied as an enable signal.

Accordingly, when the first latch 601 is enabled by the signal SEL_EN applied from the decoder 513, the first latch 601 transmits the timeslot selection control signal SEL to the enable terminal of the frequency divider 602. When the period 602 is enabled by the signal applied from the first latch 601, the clock signal 525KHz applied in synchronization with the applied FSC is divided to divide the clock signal of 256KHz and the channel enable signal CHEN, CHEN) and 64KHz and STLD load signals are output.

The output 256KHz is transmitted to the serial-to-parallel converter 603, and the serial-to-parallel converter 603 converts the applied SDO data in parallel in synchronization with the applied 256KHz clock signal and outputs the same. The output parallel data is transmitted to the second latch 604. The second latch 604 outputs only data transmitted through the corresponding channel when the CHEN signal is applied to the channel select terminal SEL at the same period as the seventh degree from the divider 602. In FIG. 7, the CHEN signal is transmitted to select the B1 channel, so that data transmitted through the B1 channel is output. In this case, since the second latch 604 stores 8 bits of data through one time slot, when one time slot is transmitted at a transmission rate of 64 Kbps, it takes 125 us. Therefore, the second latch 604 latches data of the same time slot of the next frame. Implemented to print.

The data output from the second latch 604 is transmitted to the parallel to serial converter 605. The parallel-to-serial conversion unit 605 performs parallel data applied from the second latch 604 by the STLD signal outputted from the divider 602 at the same period as the seventh degree, to provide 64KHz of the parallel data. It is loaded in synchronization with the clock signal and outputted in serial form.

The third, fourth, fifth, and sixth point converters 503 to 506 interface the BSI 102 and the PHM 105 with the TSL 103 functional block through the subhighway, that is, the CLK (4.096 MHz) and the FSC. 4 signals (8KHz), RX (2.048mbps), TX (2.048MBPS) and time slot selection control signal (CHEN) and enable signal (STLD) to select one time slot among 32 time slots on subhighway It is controlled by the 64Kbps serial data converted to output, the internal configuration is implemented in a form similar to the first and second point conversion unit 501,502 shown in FIG.

As shown in FIG. 8, the seventh, eighth, ninth, and tenth point converters 507 to 510 include a 10-bit counter 810, first to third latches 802, 803, 804, comparators 803, and a load generator 806. And the shift register 807 and convert the 8.192 Mbps parallel data provided by the TSL 103, SSW 104, and CDL 106 into 64 Kbps serial data.

That is, as shown in FIG. 9, the periods of the FP3 and CP3 data provided from the TSL 103 function block are passed through the FP and CP ports 308 and the RS422 matching unit 316, as shown in FIG. Is applied to the 10-bit counter 801. The 10-bit counter 801 counts CP3 in synchronization with FP3 and transmits the counted values Q [A ... J] to the comparator 803. When the 10 bit data SEL [0..9] applied from the time slot select control signal buffer 511 and the port select control signal SEL_EN transmitted from the decoder 513 are applied, the first latch ( 802.

The first latch 802 outputs the currently applied SEL [0..9] data when enabled by the SEL-EN signal, and when disabled, the SEL [0..9] data previously latched. Outputs The output signal is sent to the comparator 803.

The comparator 803 compares two signals applied from the 10-bit counter 801 and the first latch 802, and outputs an TS_EN signal, which is an output signal, in an active state if it matches. The TS-EN signal, which is an output signal of the comparator 803, is transmitted to the third latch 805 and the load generator 806.

The second latch 804 synchronizes data DATA [0 / ... 7] applied from the matching units 312 to 315 to the latch clock signal Latch_clk provided from the RS422 matching unit 316. After latching, the data is transmitted to the third latch 805. The third latch 805 outputs data currently transmitted from the second latch 804 when enabled by the TS_EN signal provided from the comparator 803, and outputs data previously latched when disabled. . The output data is transferred to the shift register 807. The shift register 807 outputs the data transmitted from the third latch 805 in serial form in synchronization with a 64 KHz clock signal generated by dividing the latch clock signal LATCH_CLK provided from the RS422 matching unit 316. do. At this time, an STLD signal is generated from the load generator 806 which uses CP3 as an input clock signal and a TS-EN signal as a load signal. The generated STLD signal is generated by a timing diagram as shown in FIG. do. That is, the CP3 applied in synchronization with the applied TS-EN signal is counted in an internal not shown octal counter, and when the STLD signal is output in an active state by the applied TS-EN, the counter is provided in the aforementioned counter. As shown in FIG. 10 by the / RCO signal, the STLD signal is preset.

As described above, the seventh to tenth point converters 507 to 510 for converting the type of data transmitted from the matching unit have data provided at each point in terms of channel number and timing as shown in the timing diagram of FIG. Since the data is transmitted slightly differently, the time for latching valid data in the same configuration as that of FIG. 8 is set differently.

In this way, the 10 signals converted into 64 Kbps by the first to ten point converters 501 to 510 are transmitted to the monitor point extractor 203. The monitor point extracting unit 203 is composed of four multiplexers 1107 to 1110, four latches 1103 to 1106, a port select register 1101 and a decoder 1102 as shown in FIG. The point data is extracted so that up to four points can be monitored among the ten data lines of 64 Kbps output from the converters 501 to 510.

That is, if 4-bit data is applied from the port selection control signal buffer 512 of Fig. 5, it is applied to the port selection register 1101. The port selection register 1101 temporarily stores the applied data, and then simultaneously transmits them to the fourth to seventh latches 1103 to 1106. At this time, the enable states of the fourth to seventh latches 1103 to 1106 are controlled by the signal applied from the decoder 1102 which decodes the 2-bit signal applied by the user, and is provided from the port selection register 1101. Data is output as a selection control signal of the first to fourth multiplexers 1107 to 1110. At this time, the fourth to seventh latches 1103 to 1106 have a 4-bit latch and enable signal inputs thereof to enable monitoring of up to four points simultaneously so that the output of the multiplexer selected once is maintained. Is designed. The first to fourth multiplexers 1107 to 1110 select and output one of ten points input by the selection control signal provided from the fourth to seventh latches 1103 to 1106. The output signal is output to the protocol analyzer matching unit 205 and the status display unit 204.

The status display unit 204 displays the LED of the currently selected point among the 10 points so that the user can recognize the selected port. The 10 to 10 Kbps outputted from the first to the ten point converting units 501 to 510 are displayed. It is configured to check the data output status of the currently selected point by connecting the data line to the LED.

The protocol analyzer matching unit 205 converts the signal output from the monitor point extractor 203 to RS232C level so that the maximum 4 signals output from the monitor point extractor 203 can be interfaced to the protocol analyzer 206. Play a role. To this end, the protocol analyzer matching unit 205 includes a strap jumper 1201, a level converting unit 1202, and an RS232C connector 1203 as shown in FIG. 12, and a monitor point extracting unit 203. If data for 4 points is applied, the control unit transmits the strap jumper 1201. The strap jumper 1201 is configured to interface with two data sets corresponding to the RS232C port of the PT500, which is the protocol analyzer 206, for transmission (TX) and reception (RX). For two clock signals, two data corresponding to reception and transmission and two clock signals corresponding thereto are output. The signal thus output is applied to the level converting unit 1202 to convert the TTL level to the RS232C level and to transmit it to the RS232C connector 1203. The RS232C connector 1203 transmits the data transmitted from the level converter 1202 to the protocol analyzer 206 in synchronization with the 64 Kbps signal. This allows the protocol analyzer 206 to simultaneously monitor four points.

As described above, the present invention designates 10 monitoring points on the packet link so that the protocol analyzer can check the packet link in the event of a failure of the electronic switch that accommodates the packet handling function, and the data of the designated point is assigned to the protocol analyzer. By extracting in the form that can be checked in, it is possible not only to accurately check the fault site through the protocol analyzer, but there is also a significant advantage in terms of maintenance of the system because it does not need to have a separate protocol analysis equipment.

Claims (8)

A failure occurs on the packet link through the protocol analyzer in an exchange system including an all-electronic exchange that forms a packet link between each functional block and a protocol analyzer for analyzing the protocol of the all-electronic exchange to accommodate a packet handling function. An apparatus for extracting data to monitor whether or not; A signal matching unit for matching N data applied from a monitoring point determined on the packet link to a TTL level; By using the port selection control signal and the time slot selection control signal applied by the user, a time slot including data to be transmitted is selected for each of the N data output from the signal matching unit, and the data transmitted through the selected time slot. A speed conversion and time slot selector for converting the output to a predetermined speed and outputting the same; A monitor point extracting unit for extracting data of at least four monitor points from among N pieces of data output from the speed converting and time slot selecting unit by the port selection control signal and the enable control signal applied by a user; And a protocol analyzer matching unit for matching the data output from the monitor point extractor to a signal that can be analyzed by the protocol analyzer. 2. The apparatus of claim 1, wherein the speed conversion and time slot selection unit decodes a port selection control signal applied by the user, a time slot selection control signal buffer for buffering the time slot selection control signal, and the decoder's time slot. Packet link monitoring of an all-electronic switch comprising N data converters controlled by a signal applied from a buffer for a selection control signal to convert timeslot selection and speed for data applied from the signal matching unit. Data Extractor. 3. The data transmission circuit of claim 2, wherein the data converter is configured to determine whether to transmit the timeslot selection control signal based on the port selection control signal, and data applied from the signal matching unit based on an output signal of the first latch. And a second latch for selecting a time slot of data to be transmitted, and means for outputting a signal output from the second latch as serial data having the predetermined speed. Link monitoring data extractor. The apparatus of claim 1, wherein the monitor point extracting unit comprises: a latch controlled by an enable control signal of the user to latch the port selection control signal; And a multiplexer for extracting only the data to be monitored from the N data output from the speed conversion and time slot selector by using the signal output from the latch as a selection control signal. Monitoring data extraction device. 5. The apparatus of claim 4, wherein the monitor point extracting unit comprises a latch and a multiplexer corresponding to the number of monitor points to be extracted. The apparatus of claim 1, wherein the protocol analyzer matching unit comprises: a strap jumper for transmitting two data corresponding to transmission and reception and a clock signal corresponding thereto when data is applied from the monitor point extracting unit; A level converter for converting the signal output from the strap jumper to an RS232C level; And a connector for transmitting the signal output from the level converter to the protocol analyzer in synchronization with the predetermined speed. 2. The packet link monitoring apparatus of claim 1, wherein the packet link monitoring data extracting apparatus further comprises a status display unit for displaying a state of the point extracted by the monitor point extracting unit so that a user can recognize it. Monitoring data extraction device. 2. The apparatus of claim 1, wherein the data outputted from the speed conversion and time slot selection unit is data converted at a speed of 64 KHz.