KR0131527B1 - Data ling device in exchanger - Google Patents

Abstract

This inspection device is for easily checking the IPC data path of the data link device in the electronic switchboard. To this end, the apparatus includes a clock divider for distributing and outputting a clock signal applied from a local data link device to a predetermined region in the inspection apparatus; A frame signal generator for generating a frame signal according to a clock signal applied from a clock divider; An irregular data generation unit initialized by a frame signal to generate irregular data including a frame recognition signal of a predetermined pattern; A memory unit for storing generated irregular data; A data receiving and frame extracting unit for receiving irregular data transmitted from a local data link device and extracting a frame signal of the received data; A transmission data comparison unit for detecting an error by comparing the received irregular data with the irregular data read from the memory unit; And it is envisioned to include a display driver for driving to display the comparison result of the transmission and reception data comparison unit.

Description

Communication data path checking device of data link device in all electronic switch

1 schematically shows a relationship between a local part and a central part in an electronic exchange,

2 is a conceptual diagram for checking an IPC data path of a data link device of a local part and a central part according to the present invention;

3 is a detailed block diagram of the IPC data path checking apparatus shown in FIG.

4 is an operation timing diagram of FIG.

* Explanation of symbols for main parts of the drawings

104: local data link device 111: central data link device

200: IPC data path check device 301: irregular data generator

302: frame recognition signal insertion unit 303: transmission timing signal generation unit

304: first serial / parallel conversion unit 305: memory unit

306: data receiving and frame extracting unit 307: receiving timing signal generating unit

308: second serial / parallel conversion unit 309: transmission / reception data comparison unit

310: display driver 311: clock distribution unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IPC (Inter Processing Communication, IPC) data path checking apparatus of a Data Link apparatus in an electronic switching system.

The electronic switch exchanges communication messages between the processors mounted in the local access (ASS) and the central network (INS), respectively, through the data link device. That is, as shown in FIG. 1, the IPC data transmitted from the processors 101 and 102 in the local part to the central part are collected by the first IPC processing device 103 and sent to the local data link device 104. FIG. Then, it is sent to the central data link device 111 in the center through the optical cable, and again to the second IPC processing device 112 is distributed to each of the processors (113, 114).

When an abnormal condition occurs on the communication (IPC) data path between the local part and the central part processor in the all-electric exchanger configured as described above, in order to track the abnormal path, a conventional test pattern of the local part first IPC processing apparatus ( 103) and the second IPC processing unit 112 in the center. However, this method only determines the normal / abnormal state of the transmission path, but it was impossible to know in which section the abnormal operation occurred. In particular, the path tracking of the data link itself was impossible.

Accordingly, an object of the present invention is to provide an IPC data path checking device that can easily check the IPC data path of the data link device in the electronic switching system.

In order to achieve the above object, an apparatus according to the present invention is a device for checking the inter-processor communication data path of the data link devices in the electronic switchboard having a local data link device and a central data link device connected using an optical cable. A clock distribution unit comprising: a clock distribution unit for distributing and outputting a clock signal applied from a local data link device to a predetermined region in a check device; Frame signal generation unit for generating a frame signal according to the clock signal applied from the clock distribution unit: Irregular data generation unit including a frame recognition signal of a predetermined pattern initialized by the frame signal generated by the frame signal generation unit: Irregular data generation A memory unit for storing the irregular datum generated in the unit; Data receiving and frame extracting unit for receiving irregular data transmitted from the local data link device and extracting a frame signal of the data received by the frame recognition signal: Received irregular data and memory transmitted through the data receiving and frame extracting unit Transmitting and receiving data comparison unit for detecting an error by comparing the irregular data read from the unit: and a display driver for driving to display the comparison results of the transmission and reception data comparison unit.

Next, embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a conceptual diagram of checking the IPC data path of the data link apparatus according to the present invention in the electronic switching system. FIG. 2 shows a connection between the first IPC processing apparatus 103 and the local data link apparatus 104 shown in FIG. The inspection device 200 for checking the IPC data path while cutting the connection between the second IPC processing apparatus 112 and the central data linking device 111, which was also cut and connected to the central portion as shown in FIG. The local data link device 104 is connected in both directions, and the central data link device 111 is configured to be connected to its own input terminal by feeding back the output terminal. The IPC data path checking device 200 and the local data linking device 104 are connected by cables to the inspector, and the central data link device 111 also artificially forms a feedback loop for the output terminal by the inspector.

3 is a detailed block diagram of the IPC data path checking apparatus shown in FIG. 2, which includes a clock divider 311, an irregular data generator 301, a frame recognition signal inserter 302, and a transmission timing signal generator 303. FIG. ), The first serial / parallel conversion unit 304, the memory unit 305, the reception timing signal generator 307, the data reception and frame extraction unit 306, and the second serial / parallel conversion unit 308 The reception data comparator 309 and the display driver 310 are provided.

4 is an operation timing diagram of FIG.

Next, the operation of the IPC data path checking apparatus configured as shown in FIG. 3 will be described with reference to FIG.

First, the clock distribution unit 311 distributes and outputs the clock signal applied from the local data link device 104 as shown in the fourth (b) to be used for generating various timing signals in the path check device.

The frame signal generator 302 generates a frame signal having the same period as that of the fourth (a) by the clock signal output from the clock divider 311. The generated frame signal is transmitted to the irregular data generator 301.

The irregular data generator 301 generates, as the fourth (c), irregular data in which the frame recognition data is inserted by the frame signal provided by the frame signal generator 302 as shown in the fourth (a) diagram. The frame recognition data is a signal provided to recognize the beginning of the frame at the receiving end. The frame recognition data is stored in the irregular data generator 301 and then initialized by the frame signal provided by the frame signal generator 302. It is inserted and output. In this example, an arbitrary bit pattern capable of recognizing a frame signal is inserted and output in the first 16-bit area after initialization, and the irregular data generator 301 uses an 8-bit shift register. The shift register initialized periodically by frame signal is initialized by 1msec unit when IPC transmit / receive frequency is 8.19Mbps, 2msec unit by 4.096Mbps, 4msec unit by 2.048Mbps, and 8msec unit by 1.024Mbps. Is done.

Irregular data generated in series as shown in FIG. 4 (c) is transmitted to the first serial / parallel conversion unit 304 and the local data link device 104.

The first serial / parallel converter 304 synchronizes irregular data applied in a serial form to a clock signal provided from the transmission timing signal generator 303 as shown in FIG. Output by converting bits in parallel. Here, the transmission timing signal generator 303 divides the clock signal provided from the clock divider 311 into eight divisions as shown in FIG. 4 (d). The output parallel data in units of 8 bits is transmitted to the memory unit 305.

The memory unit 305 stores 8-bit parallel data applied by the address generated as shown in the fourth (f) by the eight-division clock signal provided from the transmission timing signal generator 303. That is, data of 0 to 7 bits generated by the irregular data generator 301 is stored in the write address 0, and data corresponding to 8 to 15 bits are stored in the address 1.

On the other hand, the irregular data generated by the local data link device 104 in the irregular data generating unit 301 is the same as before, the irregular data generated by the local data link device 104 is the local data link device in the same manner as before. After output through the 104 and the central data link device 111, it is received by the feedback loop from the central data link device 111 to the IPC data path checking device 200 via the local data link device 104.

The received irregular data is applied to the data receiving and frame extracting unit 306. The data receiving and frame extracting unit 306 extracts a frame signal with respect to received data applied as shown in FIG. 4 (g). To this end, the data receiving and frame extracting unit 306 stores the same frame recognition signal as that of the irregular data generating unit 301. When data is received, the data receiving and frame extracting unit 306 compares the received data with the stored frame recognition signal. i) Extract the frame start designation as shown. The extracted frame signal is transmitted to the reception timing signal generator 307, and the received irregular data including the frame recognition signal is transmitted to the second serial / parallel converter 308.

The reception timing signal generator 307 generates a read address of the memory 305 as shown in FIG. 4 (l) according to the applied frame signal.

Meanwhile, the second serial / parallel conversion unit 308 converts the irregular data of the serial form, which is controlled and applied to the reception timing signal generation unit 307, into 8-bit parallel as shown in FIG. 4 (k) and then output. The output data is transmitted to the transmission / reception data comparison unit 309.

The transmission / reception data comparing unit 309 is configured to read data (see also fourth (l)) and a second serial / parallel conversion unit (read) by the read address supplied from the memory unit 305 as shown in FIG. 4 (l). The received data applied from 308 is sequentially compared to determine whether an error occurs in the IPC data path.

As a result of the comparison, when the data do not coincide with each other, the data counter (not shown) provided therein is increased. In this case, six hexadecimal counters (increment from 0 to 2 ⁴ 1) can be connected to increase to 2 ²⁴ 1. The data counter result value is transmitted to the display driver 310. In addition, the transmit / receive data comparison unit 309 increases the counter, which is not shown, every time 10 ⁶ bytes of data are compared (the amount of data to be compared may vary depending on the IPC transmission / reception frequency). The value is transmitted to the display driver 310 as described above. At this time, three hexadecimal counters can be connected to increase the time up to 2 ¹² 1.

The display driver 310 is for driving a light emitting diode (LED). The data counter result is assigned to 24 bits and the 12 bit is assigned to the time counter result. Each value will be displayed to inform the operator. The operator can determine the error occurrence rate by the number of errors and the measurement time generated by the data displayed on the display driver 310.

As described above, the present invention uses a check device using irregular data to check whether the IPC data path of the data link device is normal in the electronic switchboard, so that it can be easily determined without additional measurement equipment. In addition, there is an advantage that can be used without a separate power cable and power terminal because it uses the DC power provided by the electronic exchange.

Claims (6)

An apparatus for checking an interprocessor communication data path of data link devices in an electronic switch having a local data link device and a central data link device connected using an optical cable; A clock divider for distributing and outputting a clock signal applied from the local data link device to a predetermined region in the inspection apparatus; A frame signal generator for generating a frame signal by the clock signal applied from the clock divider; An irregular data generator for initializing the frame signal generated by the frame signal generator and generating irregular data including a frame recognition signal of a predetermined pattern and transmitting the random data to the local data link device; A memory unit for storing irregular data generated by the irregular data generator; A data receiving and frame extracting unit for receiving irregular data transmitted from the local data link device and extracting a frame signal of the data received by the frame recognition signal; Transmitting and receiving data comparing unit for detecting an error by comparing the irregular data received through the data receiving and frame extraction unit with the irregular data read from the memory unit; And a display driver for driving the display unit to display the comparison result of the transmission / reception data comparison unit. The apparatus of claim 1, wherein the inter-processor communication data path checking apparatus comprises: a first serial / parallel conversion unit for converting data generated in the irregular data generation unit into a parallel form so that the data generated in the random data generation unit can be stored in the memory unit; A second serial / parallel converter for converting irregular data output from the data receiving and frame extracting unit into a parallel form so as to be compared with data read from the memory; A first timing signal generator for converting the first serial-to-parallel converter and providing a write address of the memory unit according to a clock signal obtained by dividing the clock signal provided by the clock distribution; And a second timing signal generator for converting the second serial-to-parallel converter and providing a read address of the memory by the frame signal extracted from the data receiver and the frame extractor. An interprocessor communication data path checking device of a data link device. The apparatus of claim 1, wherein the transmission / reception data comparison unit comprises a data counter for counting the number of times that the data read from the memory unit and the irregular data output from the data and frame extraction unit do not match, and a time counter for checking the check time. An inter-processor communication data path checking device of a data link device in an all-electronic exchange. 4. The interprocessor communication data path checking apparatus of claim 3, wherein the display driver is driven to display the data counter result value and the time counter result value, respectively. The inter-processor communication data of the data link device according to claim 1 or 2, wherein the irregular data generation unit is configured to hold a frame recognition signal of the predetermined pattern and to be generated every time it is initialized. Route check device. According to claim 1 or 2, wherein the data receiving and frame extracting unit is configured to hold the frame recognition signal of the predetermined pattern, and to compare the received irregular data and the frame recognition signal that is retained is configured to extract the frame signal An interprocessor communication data path checking device of a data link device in an all-electronic exchange.