KR100197903B1 - Data transmission speed transferring apparatus - Google Patents

Abstract

The present invention relates to an apparatus for converting a data rate, wherein a data string received from an exchange is rearranged and output, while a 1.024 Mbps data is inserted into a 1.024 Mbps data sequence to be transmitted to the exchange and rearranged and then transmitted to the exchange. The matching unit and the 1.024 Mbps data string inputted from the 1.024 Mbps data matching unit are stored and rearranged so as to be 2.048 Mbps, while the 2.048 Mbps data string to be transmitted to the exchange is temporarily stored. The data storage unit realigns the data string to be 1.024 Mbps and inputs the data stream to the 1.024 Mbps data matching unit, inserts and rearranges a synchronization signal to the 2.048 Mbps data string input from the data storage unit, and transmits the data to the relay station. Rearrange the data stream received from the inter-station relay device and then And a 2.048 Mbps data matching unit inputted to the data storage unit, converting 1.024 Mbps data stream multiplexed and transmitted from the exchange into a 2.048 Mbps data stream, and transmitting the data stream to the inter-station relay device having a communication speed of 2.048 Mbps. The 2.048 Mbps data stream transmitted from the inter-station relay at 2.048 Mbps can be converted into a 1.024 Mbps data stream and transmitted to a switch with a communication speed of 1.024 Mbps.

Description

Data transfer rate converter

The present invention relates to an apparatus for converting a transmission rate of data, and more particularly, to an apparatus for matching a communication speed of a multi-transmission communication speed of an exchanger and a relay device between stations.

Currently, inter-station relays are commercially available for inter-station relays with a communication speed of 2.048 Mbps, while exchangers are still mixed with a switch with a multi-transmission communication speed of 1.024 Mbps and a switch with 2.048 Mbps.

Therefore, when the exchange having a multi-transmission communication speed of 1.024 Mbps is connected to other exchanges through an inter-station relay having a communication speed of 2.048 Mbps, the communication speed of the switch and the relay is different from each other. A switch having a transmission communication speed has a problem in that it cannot communicate with another switch through an inter-station relay device having a communication speed of 2.048 Mbps.

The main object of the present invention is to convert a 1.024 Mbps data stream multiplexed and transmitted from a switch having a multi-transmission communication speed of 1.024 Mbps into a data stream of 2.048 Mbps, and transmit it to an inter-station relay device having a communication speed of 2.048 Mbps. 1.048 Mbps switch and 2.048 Mbps relay between each other by providing a device that transfers a 2.048 Mbps data string transmitted from a 2.048 Mbps inter-station relay device to a 1.024 Mbps data string to a switch with a multi-transmission communication speed of 1.024 Mbps. It is to be able to build a smooth communication network by matching.

In addition, another object of the invention is to check whether there is an abnormality in the communication line by looping back the data stream to the inter-station relay unit or the exchange side, and in particular, to check the synchronization status between the exchange and the relay station to improve the reliability and accuracy of the communication network. It is.

The data transmission rate conversion apparatus according to the present invention for achieving the object of the present invention as described above, while rearranging and outputting the data string received from the exchange, and inserts a synchronization signal into the 1.024 Mbps data string to be transmitted to the exchange A 1.024 Mbps data matching unit for reordering and transmitting to the exchange; The 1.024 Mbps data matching unit stores the 1.024 Mbps data stream and rearranges the data stream to be 2.048 Mbps, while temporarily storing the 2.048 Mbps data stream to be transmitted to the exchange. A data storage unit arranged to be in a row and input to the 1.024 Mbps data matching unit; Inserting and rearranging the synchronization signal into the 2.048 Mbps data stream input from the data storage unit and transmitting the synchronization signal to the inter-station relay device, while realigning the data string received from the inter-station relay device and inputting the data to the data storage unit. It is configured to include a unit, not only can convert 2.048Mbps data stream to 1.024Mbps data stream, but also can convert 1.024Mbps data stream to 2.048Mbps data stream.

In addition, the 1.024 Mbps data matching unit and the 2.048 Mbps data matching unit include a loopback driving unit for outputting a loopback driving signal for a local station or a large station, and a synchronization state display unit for visually indicating whether the synchronization state of the received data string is normal. By looping back the data stream to the relay unit or exchange side, it is possible to check the communication line for abnormality, and to check the synchronization status of the relay unit between the exchange and the station.

1 is a schematic schematic diagram of a multi-communication network to which a data rate conversion apparatus of the present invention is applied;

2 is an overall block diagram of a data transmission rate conversion apparatus according to the present invention;

3 is a detailed block diagram of a 1.024 Mbps data matching unit shown in FIG. 2;

4 is a detailed block diagram of a 2.048 Mbps data matching unit shown in FIG. 2;

FIG. 5 is a detailed block diagram of the data storage unit shown in FIG. 2; FIG.

FIG. 6 is a detailed block diagram illustrating the signal and clock generator shown in FIG.

Explanation of symbols on the main parts of the drawings

1a, 1b: subscribers 2a, 2b: exchanges

3a, 3b: data transmission rate conversion device 4a, 4b: inter-station relay device

6: 1.024 Mbps data matching unit 7: data storage unit

8: 2.048Mbps data matching section 9: signal and clock generating section

10: power supply unit 11a, 11b: over-voltage and over-current blocking unit

12: 1.024 Mbps line matching unit 13: 1.024 Mbps frame synchronizer

14 loopback driver 15 clock extraction and synchronization selector

16: clock generator 17: input signal display unit

18: synchronization status display unit 19: 2.048Mbps line matching unit

20: 2.048Mbps frame synchronizer 21: Loopback driver

22: clock extraction and synchronization selector 23: clock generator

24: input signal display unit 25: synchronization status display unit

A: 1.024Mbps / 2.048Mbps Converter

B: 2.048Mbps / 1.024Mbps Converter

26: serial / parallel converter 27: synchronizer

28 memory unit 29 parallel / serial conversion unit

30: serial / parallel converter 31: synchronizer

32: memory unit 33: parallel / serial conversion unit

C: sync state detector D: first signal and clock generator

E: second signal and clock generator 34: shifter

35: synchronization monitoring unit 36: pulse generator

37: 7-bit counter 38: latch portion

39: 4-bit counter 39a: Combination unit

40: 3-bit counter 40a: Combination unit

41: 8-bit counter 42: latch portion

43: 4-bit counter 43a: Combination unit

44: 3-bit counter 44a: Combination unit

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic schematic diagram of a multi-communication network to which a data rate conversion apparatus of the present invention is applied, and converts a 1.024 Mbps data string into a 2.048 Mbp data string without damage or a 2.048 Mbps data string into a 1.024 Mbps data string without damage. The data transmission rate converting apparatus 3 of the present invention is provided between the exchanger 2 and the relay station 4 between stations.

In this case, the data transmission rate conversion device (3) is located in the middle of the switchboard (2) and the relay station between the station 4, the switchboard (2) is fixed in consideration of the point that can be used for movement if necessary Since it should be installed close to the inter-station relay unit 4, mount up to 8 data transfer rate converters 3 by card type using the empty space in the maintenance section of PCM-32T, a 2.048 Mbps single station unit. It is.

The data transmission rate converters 3a and 3b of the present invention have a 1.024 Mbps data matching section 6, a data storage section 7, a 2.048 Mbps data matching section 8, and a signal as shown in FIG. And a clock generator 9 and a power supply unit 10.

The signal and clock generator 9 generates and provides a signal and a clock required by the 1.024 Mbps data matching unit 6, the data storage unit 7, and the 2.048 Mbps data matching unit 8. have.

The 1.024 Mbps data matching unit 6 checks the communication speed and the frame of the data string received from the switch 2 through the receiving terminal (ring), and notifies the alarm state if it does not match the data string of 1.024 Mbps. The data rows are rearranged and then input to the data storage unit 7.

Further, the 1.024 Mbps data matching section 6 inserts and rearranges the synchronization signals in the 1.024 Mbps data stream inputted from the data storage section 7 and then applies the signals and clocks provided by the signal and clock generator 9. Therefore, it transmits to the exchange 2 via a transmission terminal (tip).

The data storage unit 7 stores a 1.024 Mbps data stream rearranged and input by the 1.024 Mbps data matching unit 6 according to the signal and clock provided by the signal and clock generator 9, and then stores the data stream of 2.048 Mbps. The data is rearranged so as to be a data string and input to the 2.048 Mbps data matching section 8.

In addition, the data storage unit 7 temporarily stores a 2.048 Mbps data stream rearranged and input by the 2.048 Mbps data matching unit 8 according to the signals and clocks provided by the signal and clock generator 9. The data is rearranged so as to be a 1.024 Mbps data string and input to the 1.024 Mbps data matching section 6.

The 2.048 Mbps data matching section 8 inserts and rearranges the synchronization signals in the 2.048 Mbps data stream inputted from the data storage section 7 and then inter-stations according to the signals and clocks provided by the signal and clock generation section 9. It is supposed to transmit to the relay device 4.

In addition, the 2.048 Mbps data matching unit 8 checks the data rate received from the inter-station relay device 4 and checks the communication speed and the frame and notifies the alarm state if it does not match the data stream of 2.048 Mbps. Are rearranged and then input to the data storage unit 7.

In addition, the power supply unit 10 is to stabilize the power of the DC + 5V input from the outside, and then to supply to each component of the data transmission rate converter (3).

At this time, the power supply unit 10 is a main component to prevent the malfunction of the power transmission data (not shown) to determine whether the input power is normal, and the data transmission rate converter 3 when the input power is less than DC + 4V. A reset driving circuit (not shown) is provided to stop the operation.

As shown in FIG. 3, the 1.024 Mbps data matching unit 6 of the data rate converter 3 configured as described above includes the overvoltage and overcurrent blocking units 11a and 11b and the 1.024 Mbps line matching unit 12. ), A 1.024 Mbps frame synchronizer 13, a loopback driver 14, a clock extraction and synchronization selector 15, a clock generator 16, an input signal display 17, and a synchronization status display 18. Consists of.

The overvoltage and overcurrent blocking unit 11a blocks overvoltage and overcurrent introduced by lightning or other short circuits, and passes only the pure data string transmitted from the exchanger 2 to the 1.024Mbps line matching unit 12. It is supposed to.

The 1.024 Mbps line matching unit 12 matches the line impedance with the switch 2 and compensates for the data string in which distortion or weakening is made through the line, regenerates the normal data string, and inputs it to the 1.024 Mbps frame synchronizer 13. On the other hand, a clock (approximately 1.024 MHz) extracted first from the 1.024 Mbps data string transmitted from the switch 2 is inputted to the clock extraction and synchronization selector 15.

In addition, the 1.024 Mbps line matching unit 12 always monitors the input data stream and visually sends a signal to the input signal display unit 17 if there is no received data due to disconnection of the line and failure of the switch 2. On the other hand, the loopback drive unit 14 receives the own station or the power station loopback drive signal to perform the loopback function.

The 1.024 Mbps line matching unit 12 converts the TTL-level data output from the 1.024 Mbps frame synchronizer 13 into a bipolar signal and then switches through an overvoltage and overcurrent blocking unit 11b. (2).

The 1.024 Mbps frame synchronizer 13 synchronizes the data strings input from the 1.024 Mbps line matcher 12 according to the synchronization signal of the data strings input from the 1.024 Mbps line matcher 12, and then rearranges the data. While inputting to the storage unit 7, the synchronization signal is inputted to the signal and clock generator 9.

In addition, the 1.024 Mbps frame synchronizer 13 receives a string of data input from the data storage unit 7 to align the frame and input the same to the 1.024 Mbps line matching unit 12.

The clock extracting and synchronizing selector 15 uses a 16.384 MHz clock generated by the clock generator 16 as a main clock to compare phase with a primary extraction clock input from the 1.024 Mbps line matching unit 12. In synchronization, a clock of 1.024 MHz is input to the frame synchronizer 13 and the signal and clock generator 9.

In addition, the clock extracting and synchronizing selector 15 may output a 1.024 MHz clock generated by itself to the frame synchronizer 13 regardless of the clock extracted first by the 1.024 Mbps line matching unit 12 according to the purpose of use. ) And to the signal and clock generator 9.

The synchronization state display unit 18 is configured to receive the signal from the signal and clock generator 9 and display whether the synchronization state is normal.

As shown in FIG. 4, the 2.048Mbps data matching unit 8 shown in FIG. 2 includes a 2.048Mbps line matching unit 19, a 2.048Mbps frame synchronizer 20, a loopback driver 21, and a clock. The extraction and synchronization selection unit 22, the clock generator 23, the input signal display unit 24, and the synchronization state display unit 25 are configured.

The 2.048 Mbps line matching unit 19 matches the line impedance with the inter-station relay device 4 and compensates the 2.048 Mbps data string that is distorted or weakened through the line to make a normal data string to form a normal data stream. 20), the clock extracted first from the 2.048 Mbps data stream inputted from the inter-station relay 4 is inputted to the clock extraction and synchronization selector 22.

In addition, the data stream inputted from the inter-station relay 4 is always monitored, and if there is no received data due to disconnection of the line and failure of the inter-station relay 4, a signal is sent to the input signal display unit 24 for visual display. On the other hand, the loopback driver 21 receives the own station or the power station loopback drive signal to perform the loopback function.

The 2.048Mbps line matching section 19 converts the TTL level data input from the 2.048Mbps frame synchronization section 20 into a bipolar signal for transmission to the inter-station relay 4. .

The 2.048 Mbps frame synchronizer 20 synchronizes the data string input from the 2.048 Mbps line matcher 19 according to the synchronization signal of the data string input from the 2.048 Mbps line matcher 19, and then rearranges the data. While inputting to the data storage unit 7, the synchronization signal is inputted to the signal and clock generation unit 9.

The 2.048Mbps frame synchronizer 20 determines whether the synchronization state is normal and inputs a signal indicating whether the synchronization state is normal to the synchronization state display unit 25.

In addition, the data received from the data storage unit 7 is input to the line matching unit 19 to align the frame after receiving the data stream.

The clock extracting and synchronizing selector 22 uses a 16.384 MHz clock generated by the clock generator 23 as a main clock to compare phases with the first extracted clock inputted from the 2.048 Mbps line matching unit 20. They are inputted in synchronization to the 2.048 Mbps frame synchronizer 20 and the signal and clock generator 9, respectively.

In addition, the clock extracting and synchronizing selector 22 converts a 2.048 MHz clock generated by itself into a 2.048 Mbps frame synchronizer 20 and a signal and clock generator 9 regardless of the primary extraction clock. You can also enter

The synchronization state display unit 25 is configured to visually display the synchronization state normality signal from the 2.048 Mbps frame synchronization unit 20.

As shown in FIG. 5, the data storage unit 7 shown in FIG. 2 receives and stores a 1.024 Mbps data string and outputs a 2.048 Mbps data string to the 1.024 Mbps / 2.048 Mbps converter A. As shown in FIG. And a 2.048 Mbps / 1.024 Mbps conversion section (B) that receives and stores a 2.048 Mbps data stream and outputs it as a 1.024 Mbps data stream, while the 1.024 Mbps / 2.048 Mbps conversion section (A) performs serial / parallel conversion. A unit 26, a synchronization unit 27, a memory unit 28, and a parallel / serial conversion unit 29 are configured, and the 2.048 Mbps / 1.024 Mbps conversion unit B includes serial / parallel conversion. The unit 30 includes a synchronization unit 31, a memory unit 32, and a parallel / serial conversion unit 33.

The serial / parallel conversion section 26 of the 1.024 Mbps / 2.048 Mbps conversion section A receives the serial data of 1.024 Mbps from the 1.024 Mbps data matching section 6 and provides 128 KHz provided from the signal and clock generation section 9. The clock is converted into an 8-bit parallel data string and input to the synchronizer 27.

The synchronizer 27 synchronizes an 8-bit parallel data string input from the serial / parallel converter 26 according to a 128 kHz clock provided by the signal and clock generator 9 and inputs the same to the memory 28. It is supposed to.

The memory unit 28 transfers the 8-bit parallel data string input from the synchronizer 27 at a rate of 128 KHz, which is 8 divisions of 1.024 Mbps according to the memory write clock provided by the signal and clock generator 9. Simultaneously with storing, the data stored in accordance with the memory read clock provided by the signal and clock generator 9 are outputted at a speed of 128 KHz and inputted to the parallel / serial converter 29.

At this time, the memory unit 28 is composed of a first-in, first-out (FIFO buffer) to output sequentially from the first stored data.

The parallel / serial converter 29 converts an 8-bit parallel data stream output from the memory unit 28 into a serial data stream according to a clock of 256 KHz provided from the signal and clock generator 9 and converts it to 2.048 Mbps. Is input to the 2.048 Mbps data matching section 8.

In addition, the serial / parallel conversion unit 30 of the 2.048 Mbps / 1.024 Mbps conversion unit B receives 2.048 Mbps serial data from the 2.048 Mbps data matching unit 8 and 256 KHz provided from the signal and clock generation unit 9. The clock is converted into an 8-bit parallel data sequence by the clock, and inputted to the synchronizer 31.

The synchronizer 31 synchronizes an 8-bit parallel data string input from the serial / parallel converter 30 according to a 256 kHz clock provided by the signal and clock generator 9 to the memory 32. It is supposed to be entered.

The memory 32 stores at a rate of 256 KHz, which is 8 divisions of 2.048 MHz according to the memory write clock provided by the signal and clock generator 9, and simultaneously stores the memory lead provided by the signal and clock generator 9. READ) The data stored in accordance with the clock is output at a rate of 256 KHz and input to the parallel / serial converter 33.

At this time, the memory unit 32 is composed of a first-in first-out (FIFO buffer) to output sequentially from the data stored first.

The parallel / serial conversion section 33 converts the parallel data stream output from the memory section 32 into a 1.024 MHz serial data stream according to a 256 KHz clock provided by the signal and clock generation section 9 to match 1.024 Mbps data. It is supposed to input to the subfield 6.

As shown in FIG. 6, the signal and clock generator 9 shown in FIG. 2 determines whether the synchronization state of the data string output from the 1.024Mbps line matching unit 12 is normal to determine whether the synchronization state is normal. A first signal and clock for receiving a signal and a clock generated by the 1.024 Mbps data matching unit 6 and generating a signal and a clock required to process 1.024 Mbps of data; Generation of the second signal and the clock to generate and output a signal and a clock necessary for processing the data of 2.048 Mbps by receiving the signal and the clock generated by the generator D and the 2.048 Mbps data matching unit 8. It consists of part (E).

The synchronization state detecting unit C is configured to include a shift unit 34, a synchronization monitoring unit 35, and a pulse generator 36. The bit counter 37, the latch part 38, the 4-bit counter 39, the combining part 39a, the 3-bit counter 40, and the combining part 40a are comprised.

The second signal and clock generator E includes an 8-bit counter 41, a latch unit 42, a 4-bit counter 43, a combination unit 43a, a 3-bit counter 44, and a combination thereof. It is comprised including the part 44a.

In the synchronization state detecting unit C, the shift unit 34 is input from the 1.024 Mbps line matching unit 12 of the 1.024 Mbps data matching unit 6 according to the pulse input from the pulse generator 36. The received 1.024 Mbps received data stream is shifted and input to the synchronization monitoring unit 35.

The synchronization monitoring unit 35 finds a series of synchronization bits from the data string input from the shift unit 34, and if a series of synchronization bits is found, the synchronization acquisition display signal outputs a synchronization acquisition indication signal to the pulse generator 36 and 1.024 Mbps data. The synchronization status display section 18 of the matching section 6 is input to the synchronization status display section 18, and if a series of synchronization bits are not found, the synchronization loss display signal of the pulse generating section 36 and the 1.024Mbps data matching section 6 18) to input each.

The pulse generator 36 does not generate a pulse when the sync capture display signal is input, and generates a pulse and inputs it to the shift unit 34 when the sync loss display signal is input.

In the first signal and clock generator D, the 7-bit counter 37 receives the 1.024 MHz signal input from the clock extraction and synchronization selector 15 of the 1.024 Mbps data matching unit 6. The clock is counted to generate an 8KHz clock divided by 128, and then outputted to the latch unit 38. The latch unit 38 is input to the 1.024Mbps data matching unit 6 in synchronization with the 8KHz clock. .

The 4-bit counter 39 counts the 8KHz clock inputted from the 1.024 Mbps frame synchronizer 13 of the 1.024 MHz received clock and the 1.024 Mbps data matcher 6 and outputs the clock to the combiner 39a. The combiner 39a combines the clock output from the 4-bit counter 39 to input a 64 kHz clock to the 1.024 Mbps data matcher 6.

In addition, the 3-bit counter 40 counts the 1.024 Mbps transmission clock input from the 1.024 Mbps frame synchronizer 13 of the 1.024 Mbps data matching unit 6 and outputs the counted clock to the combining unit 40a. The unit 40a combines the clock generated by the three-bit counter 40 to input a clock of 128 kHz to the 1.024 Mbps data matching unit 6.

In the second signal and clock generator E, the 8-bit counter 41 receives a 2.048 MHz received clock from the clock extraction and synchronization selector 22 of the 2.048 Mbps data matching unit 8. A 256K divided clock of 8KHz is generated and outputted to the latch unit 42. The latch unit 42 is input to the 2.048Mbps data matching unit 8 in synchronization with the 8KHz clock.

The 4-bit counter 43 counts the 8KHz received synchronization signal input from the 2.048Mbps frame synchronizer 20 of the 2.048Mbps data matching unit 8 and the 2.048MHz received clock and outputs the counted signal to the combiner 43a. The combiner 43a combines the clock output from the 4-bit counter 43 to input a 128 kHz clock to the data storage 7.

The 3-bit counter 44 counts an 8KHz transmission synchronization signal and a 2.048MHz transmission clock inputted from the 2.048Mbps frame synchronization unit 20 of the 2.048Mbps data matching unit 8, and then combines the 4444. The combination unit 44a combines the clock generated by the 3-bit counter 44 to input a clock of 256 kHz to the data storage unit 7.

The operation of the apparatus for converting data rates according to the present invention configured as described above will be described in detail with reference to FIGS. 1 to 6.

In the multiple communication network shown in Fig. 1, when each subscriber 1a transmits signals and information to the switch 2a, the switch 2a in which the subscriber 1a is accommodated receives the signals and the signals of the respective subscribers 1a. The information is multiplexed into a data string having a communication speed of 1.024 Mbps, and transmitted to a receiving terminal (ring) of the data transmission rate conversion device 3a of the present invention through a transmission terminal (tip), and the data transmission rate conversion device 3a ) Converts the 1.024 Mbps data string received through the receiving terminal (ring) into a 2.048 Mbp data string without damage and transmits it to the receiving terminal (ring) of the inter-station relay device 4a through the transmitting terminal (tip).

The inter-station relay device 4a transmits the data stream of 2.048 Mbps received through the receiving terminal (ring) to the inter-station relay device 4b of another station through the transmitting terminal (tip).

At this time, the inter-station relay device 4a amplifies the data string to compensate for the attenuation of the signal magnitude by the long line, and then transmits it to the inter-station relay device 4b of another station.

Then, the inter-station relay device 4b of the other station receives the data string transmitted from the inter-station relay device 4a through the receiving terminal (ring), reproduces the data string, and then transmits the data string through the transmitting terminal (tip). The data transmission rate conversion device 3b of the present invention transmits a data rate of 2.048 Mbps to a data stream of 1.024 Mbps and then exchanges the data rate with the exchange terminal (ring). 2b).

The exchange 2b receives the input, demultiplexes it, and transmits the same to the subscriber 1b to form a call path.

In the data rate converters 3a and 3b as described above, the multiplexed data string having a communication speed of 1.024 Mbps input from the switching center 2a to the receiving terminal (ring) is 1.024, as shown in FIG. The 1.024 Mbps data matching unit 6 is inputted to the Mbps data matching unit 6, and the 1.024 Mbps data matching unit 6 checks the communication speed and the frame of the received data sequence and notifies the alarm state if it does not match, and if it matches, realigns the received data and then the data storage unit. Send to (7).

The data storage unit 7 stores the received data sequence rearranged and received by the 1.024 Mbps data matching unit 6 according to the signal and clock provided by the signal and clock generation unit 9, and then stores 2.048 megabits of data. The data is extracted and rearranged so as to be a data string, and then output to the 2.048 Mbps data matching unit 8.

The 2.048 Mbps data matching section 8 inserts and rearranges the synchronization signals in the 2.048 Mbps data stream inputted from the data storage section 7, and then inter-stations according to the signals and clocks received from the signal and clock generation section 9. By transmitting to the relay device 4a, the communication speed is changed.

In addition, the 2.048 Mbps data matching unit 8 receives a data string having a communication speed of 2.048 Mbps received from the inter-station relay device 4a and checks the communication speed and the frame. The received data is rearranged and sent to the data storage 7.

The data storage unit 7 temporarily stores the received data sequence rearranged and inputted by the 2.048 Mbps data matching unit 8 according to the signal and clock provided by the signal and clock generator 9, and then stores the data at 1.024 Mbps. The heat is removed, rearranged, and sent to the 1.024 Mbps data matching unit 6.

Then, the 1.024 Mbps data matching unit 6 rearranges the 1.024 Mbps data stream coming from the data storage unit 7 and then repeats the inter-station relay device according to the signal and clock received from the signal and clock generator 9 ( By sending to 4a), the communication speed is converted.

At this time, in the 1.024 Mbps data matching section 6 as shown in FIG. 3, the 1.024 Mbps data string received at the exchanger 2a is connected to the lightning or other line at the overvoltage and overcurrent blocking section 11a. The overvoltage and overcurrent introduced by the short circuit are blocked so that only the pure data string is input to the 1.024Mbps line matching unit 12.

The 1.024 Mbps line matching unit 12 matches the line impedance with the switch 2a and compensates for the data string in which distortion or weakening is made through the line to make a normal data string and input it into the 1.024 Mbps frame synchronizer 13. On the other hand, the clock extracted first from the 1.024 Mbps data stream input from the exchanger 2a is sent to the clock extraction and synchronization selector 15.

In addition, the 1.024 Mbps line matching unit 12 constantly monitors the input data string and sends a signal to the input signal display unit 17 to visually display if there is no received data due to disconnection of the line and failure of the switch 2a. The loopback drive unit 14 receives the own station or large loopback drive signal from the loopback driver 14 to perform a loopback function.

The 1.024 Mbps frame synchronizer 13 synchronizes with the data string input from the 1.024 Mbps line matcher 12 and then rearranges the data to the data storage unit 7 to send the synchronized clock signal and clock generation. To part (9).

In addition, the clock extracting and synchronizing selector 15 uses a clock of 16.384 megahertz generated from the clock generator 16 as a main clock, and compares the phase with the first extraction clock received from the line matching unit 12. According to the purpose of use, a clock of 1.024 MHz generated by itself may be transferred to the frame synchronizer 13 and the signal and clock generator 9 regardless of the clock extracted from the line matching unit 12. send.

Meanwhile, the data stream received from the data storage unit 7 receives the data stream and the frame is matched by the 1.024 Mbps frame synchronizer 13, and then sent to the 1.024 Mbps line matching unit 12. TTL) level data is converted into a bipolar signal, and then a data string is transmitted to the switching center 2a.

In the 2.048 Mbps data matching section 8 shown in Fig. 4, the 1.024 Mbps data string received by the inter-station relay 4a is input to the receiving terminal of the 2.048 Mbps line matching section 19.

The 2.048Mbps line matching unit 19 matches the line impedance with the inter-station relay device 4a and compensates the 2.048 Mbps data string, which has become distorted or weakened through the line, to make a normal data string to form a normal data stream. 20), and the clock extracted first from the 2.048 Mbps data stream inputted from the inter-station relay device 4a is sent to the clock extraction and synchronization selector 22.

In addition, the data stream inputted from the inter-station relay device 4a is always monitored, and if there is no received data due to the disconnection of the line and the failure of the inter-station relay device 4, the signal is sent to the input signal display unit 24 for visual display. The loopback drive unit 21 receives the own station or large loopback drive signal from the loopback driver 21 to perform a loopback function.

The 2.048 Mbps frame synchronizer 20 synchronizes data streams input from the 2.048 Mbps line matcher 19, then rearranges the data to the data storage unit 7, and sends the synchronized clock signal and clock generation. Input to part (9).

The clock extracting and synchronizing selector 22 uses a clock of 16.384 MHz generated from the clock generator 23 as a main clock to compare phases with the primary extraction clock input from the 2.048 Mbps line matching unit 19. Depending on the purpose of use, the 2.048 MHz clock generated by itself is input to the 2.048 Mbps frame synchronizer 20 and the signal and clock generator 9 independently of the primary extraction clock.

The synchronization state display unit 25 visually displays the synchronization state normal signal from the 2.048 Mbps frame synchronization unit 20.

In addition, the 2.048 Mbps frame synchronizer 20 aligns the frame of the data string input from the data storage unit 7 and inputs the same to the 2.048 Mbps line matcher 19. TTL) level data is converted into a bipolar signal, and a 2.048 Mbps data stream is transmitted to the inter-station relay 4.

In the data storage unit 7 shown in Fig. 5, the serial / parallel conversion unit 26 receives the 1.024 Mbps serial data from the 1.024 Mbps data matching unit 6 from the signal and clock generator 9; According to the generated clock (126KHz), it is converted into an 8-bit parallel data string and then input to the synchronizer 27.

The synchronization unit 27 receives a clock (128KHz) for synchronization from the signal and clock generation unit 9, synchronizes an 8-bit parallel data string, and inputs the same to the memory unit 28.

The memory unit 28 is composed of a first-in first-out (FIFO buffer), a memory write (WRITE) clock input from the signal and clock generator 9 to the 8-bit parallel data string input from the synchronization unit 27 According to the memory division, the data is stored at 128 KHz, which is 8 divisions of 1.024 Mbps, and at the same time, the data string stored in the memory is read from the signal and clock generator 9 at 128 KHz according to the memory read clock. Enter (29).

The parallel / serial converter 29 receives a 256 kHz clock from the signal and clock generator 9 and inputs the 2.048 Mbps data matching unit 8 with a 2.048 Mbps data string.

Meanwhile, the serial / parallel converter 30 receives a 2.048 Mbps serial data sequence from the 2.048 Mbps data matching unit 8 and uses 8 bits by a clock (256 KHz) generated from the signal and clock generator 9. Are converted into parallel data streams and input to the synchronization unit 31.

The synchronizing unit 31 receives a clock 256K for synchronizing from the signal and clock generating unit 9 and synchronously adjusts the 8-bit parallel data string and inputs the same to the memory unit 32.

The memory unit 32 is composed of the same first-in, first-out buffer as the memory unit 28, and stores the signal from the signal and clock generator 9 at 256KHz, which is 8 divisions of 2.048 MHz according to the memory write clock. At the same time, data stored at a rate of 256 KHz is read from the signal and clock generator 9 in accordance with the memory read clock and input to the parallel / serial converter 33.

The parallel / serial conversion section 33 converts the parallel data stream into a serial data stream at a rate of 1.024 MHz according to a clock of 126 KHz input from the signal and clock generator 9 and inputs it to the 1.024 Mbps data matching section 6. do.

In the signal and clock generator 9 shown in FIG. 6, if the synchronization is not synchronized by a signal indicating whether the synchronization monitoring unit 35 is synchronized, the pulse generator 36 generates a pulse according to the pulse. The shift unit 34 shifts the received data stream of 1.024 Mbps and inputs it to the synchronization monitoring unit 35.

The synchronization monitoring unit 35 finds a series of synchronization bits from the received data string latched by the shift unit 34, and if a series of synchronization bits are found, the synchronization acquisition indication signal is converted into a 1.024Mbps data matching unit ( 6 is inputted to the synchronization state display unit 18, and the pulse generator 36 does not generate a pulse, so that the shift unit 34 does not shift the received data sequence without changing the received data sequence. ).

If a series of synchronization bits are not found, a synchronization loss indication signal is input to the synchronization state display unit 18, and the pulse generator 36 generates a pulse to drive the shift unit 34 as the shift unit 34 is driven. In the section 34, the data string shifted by one bit in the current continuous data string is input to the synchronization monitoring unit 35.

As a result, the shift section 34 continuously shifts the received data string by one bit by the pulse generated by the pulse generator 36 until the synchronization is captured, and sends it to the synchronization monitoring section 35. When it is captured, the shift section 34 stops, accepts a series of sync bits, and sends a sync acquisition display signal to the sync status display unit 18.

On the other hand, the 7-bit counter 37 receives an input clock of 1.024 MHz, generates an 8-KHz clock divided into 128 and inputs it to the latch unit 38. The latch 38 synchronizes the clock of the 8-KHz clocked in synchronization. Input to 1.024 Mbps data matching section (6).

In addition, by combining the clock generated by the 4-bit counter 39 by the receiving synchronization signal of 8KHz and the receiving clock of 1.024MHz by the combining unit 39a, a 64KHz clock is input to the 1.024Mbps data matching unit 6, The clock generated from the 3-bit counter 40 is combined by the combiner 40a by the 1.024 MHz transmit clock, and the 128 kHz clock is input to the 1.024 Mbps data matching unit 6.

On the other hand, the 8-bit counter 41 receives the 2.048 MHz received clock from the clock extracting and synchronizing selector 22 of the 2.048 Mbps data matching section 8 to generate an 8-KHz clock divided by 256 to the latch section 42. The latch unit 42 latches the 8 KHz clock in synchronization, and inputs the same to the 2.048 Mbps data matching unit 8.

In addition, the combiner 43a combines the clock generated from the 4-bit counter 43 by the 8 KHz receive synchronization signal input from the 2.048 Mbps frame synchronizer 20 of the 2.048 Mbps data matching unit 8 and the receive clock of 2.048 MHz. ) And outputs a 128KHz clock to the data storage unit 7.

Then, the clock of 256KHz is combined by combining the clock generated from the 3-bit counter 44 by the 8KHz transmission synchronization signal input from the 2.048Mbps frame synchronization unit 20 and the 2.048MHz transmission clock by the combination unit 44a. To the data storage 7.

As described above, the signal and clock generator 9 generates an overall signal and a clock so that the data rate converter 3 can perform a data rate conversion function.

On the other hand, since the power supply of the data transmission rate conversion device 3 operating as described above is a voltage of DC + 5V, the power supply unit 10 receives a DC + 5V input power and outputs a stable DC + 5V.

The power supply unit 10 has a built-in power monitoring circuit for determining whether the input power is normal. If the input power is less than DC + 4V, the reset driving circuit is operated to stop the operation of the main parts, thereby converting the data transfer rate. The malfunction of (3) can be prevented.

In addition, since the data rate converter 3 is composed of a low-power transistor-transistor logic (TRANSISTOR-TRANSISTOR LOGIC), there are various advantages such as high stability, real time service, and low power consumption. Has

In addition, although the data transmission rate converter 3 is located in the middle of the relay station 4 between the switching station 2 and the station 4 in consideration of the schematic diagram of the multiple communication network of FIG. 1, the switching station 2 is used for movement if necessary. It is necessary to install the data transmission rate converter 3 in the PCM-32T, which is a 2.048Mbps single station device, since it should be installed in close proximity with the inter-station relay device 4 for fixed installation. Up to eight transfer rate converters 3 are mounted in a card form using an empty space in the department.

Therefore, it is advantageous in terms of installation and maintenance because it eliminates a separate installation space by using an unused empty space and can use the power used by a 2.048Mbps single station device as it is.

As described above, according to the present invention, a 1.024 Mbps data stream multiplexed and transmitted from an exchange having a multi-transmission communication speed of 1.024 Mbps is converted into a data stream of 2.048 Mbps, and then transmitted to a relay station between 2.048 Mbps. By providing a device for transmitting a 2.048 Mbps data stream transmitted from the inter-station relay device having a 2.048 Mbps transmission rate to a 1.024 Mbps data stream for transmission to an exchange having a multi-transmission communication rate of 1.024 Mbps, a 1.024 Mbps exchange between a 2.048 Mbps station The relay devices can be matched with each other to build a smooth communication network.

In addition, it is possible to check whether there is an abnormality in the communication line by looping back the data stream to the inter-station relay unit or the exchange side, and in particular, it is possible to improve the reliability and accuracy of the communication network by checking the synchronization status between the relay and the station.

In addition, the power supply unit 10 has a power monitoring circuit for determining whether the input power supply is normal. If the input power is less than DC + 4V, the reset driving circuit is operated to stop the operation of the main parts, thereby converting the data transmission speed. The malfunction of the apparatus 3 can be prevented.

In addition, the data transmission rate converting apparatus 3 is composed of a low power TTL, which provides high stability, real time service, and low power consumption.

In addition, the data transfer rate converter 3 is mounted separately by installing a maximum of eight transfer rate converters 3 by card type using the empty space in the maintenance unit in the PCM-32T which is a 2.048 Mbps single station device. Not only does it require space, but the power supply is also easy to install and maintain, as it uses the same power as the 2.048Mbps station.

Claims (20)

A 1.024 Mbps data matching unit for rearranging and outputting the data string received from the exchange, inserting and rearranging a synchronization signal in the 1.024 Mbps data string to be transmitted to the exchange, and then transmitting the synchronous signal to the exchange; The 1.024 Mbps data matching unit stores the 1.024 Mbps data stream and rearranges the data stream to be 2.048 Mbps, while temporarily storing the 2.048 Mbps data stream to be transmitted to the exchange. A data storage for rearranging the data to be inputted to the 1.024 Mbps data matching unit; Inserting and rearranging the synchronization signal into the 2.048 Mbps data stream input from the data storage unit and transmitting the synchronization signal to the inter-station relay device, while realigning the data string received from the inter-station relay device and inputting the data to the data storage unit. part; The 1.024 Mbps data matching unit, the data storage unit, and 2.048 are generated by generating a signal and a clock required to convert a 1.024 Mbps data string to a 2.048 Mbps data string, and a clock required to convert a 2.048 Mbps data string to a 1.024 Mbps data string. A signal and clock generation unit provided to the Mbps data matching unit; And a power supply unit supplying power to the 1.024 Mbps data matching unit, the data storage unit, the 2.048 Mbps data matching unit, and the signal generator. The power supply monitoring circuit of claim 1, wherein the power supply unit determines whether the input power supply is normal, and when the voltage of the input power supply is lower than or equal to a predetermined voltage, the 1.024Mbps data matching unit, the data storage unit, the 2.048Mbps data matching unit, And a reset driving circuit for stopping the operation of the signal and clock generator. 2. The first overvoltage and overcurrent blocking unit of claim 1, wherein the 1.024 Mbps data matching unit blocks the overvoltage and overcurrent introduced by lightning or other short circuits, and passes only the pure data stream transmitted from the exchanger; 4. The apparatus of claim 3, wherein the first clock extractor and the synchronization selector generate a 1.024 MHz clock independently of the clock extracted from the 1.024 Mbps line matching unit. And a data transmission rate converting apparatus, which is inputted to a generator. 4. The apparatus of claim 3, further comprising a first input signal display unit for visually indicating that there is no data received from the exchange, and a first loopback driver for outputting a local or large loopback drive signal. It always monitors the input data stream and sends a signal to the first input signal display unit to visually indicate that there is no data received due to disconnection of the line or failure of the switch, and outputs from the first loopback driver. And a loopback drive signal inputted to the slave station or the power station to perform loopback. The 1.024 Mbps / 2.048 Mbps conversion according to claim 1, wherein the data storage unit stores a 1.024 Mbps data string input from the 1.024 Mbps data matching unit, converts the data string into a 2.048 Mbps data string, and inputs it to the 2.048 Mbps data matching unit. And a 2.048 Mbps / 1.024 Mbps converter that stores a 2.048 Mbps data stream input from the 2.048 Mbps data matcher and converts the data stream into a 1.024 Mbps data stream and inputs the 1.024 Mbps data matcher. Data transfer rate converter. 7. The apparatus of claim 6, wherein the 1.024 Mbps / 2.048 Mbps converter comprises: a first serial / parallel converter for converting a 1.024 Mbps serial data string input from the 1.024 Mbps data matching unit into an 8-bit parallel data string; A first synchronizer configured to synchronously adjust and output an 8-bit parallel data string input from the first serial / parallel converter; A first memory unit for storing an 8-bit parallel data string input from the first synchronization unit at a 128 KHz speed and outputting the stored data at a 128 KHz speed; And a first parallel / serial converter for converting an 8-bit parallel data string input from the first memory unit into a 2.048 Mbps serial data string and inputting the same to the 2.048 Mbps data matching unit. . 8. The apparatus of claim 7, wherein the first memory unit comprises a first-in first-out buffer to sequentially output data from first stored data. 7. The apparatus of claim 6, wherein the 2.048 Mbps / 1.024 Mbps converter comprises: a second serial / parallel converter for converting 2.048 Mbps serial data input from the 2.048 Mbps data matcher into an 8-bit parallel data string; A second synchronizer configured to synchronously adjust and output an 8-bit parallel data string input from the second serial / parallel converter; A second memory unit for storing the 8-bit parallel data string input from the second synchronization unit at 256KHz and outputting the stored data at 256KHz; And a second parallel / serial converter for converting the 8-bit parallel data string output from the second memory unit into a 1.024 MHz serial data string and inputting the same to the 1.024 Mbps data matching unit. . 10. The apparatus of claim 9, wherein the second memory unit is configured as a first-in first-out buffer to sequentially output data from first stored data. The data linking apparatus of claim 1, wherein the 2.048 Mbps data matching unit matches the line impedance with the inter-station relay device and compensates the 2.048 Mbps data string that is distorted or weakened through the line and outputs the normal data string. The clock is extracted from the 2.048 Mbps data stream inputted from the relay device firstly and output, while the T48 (TTL) level 2.048 Mbps data stream to be transmitted to the inter-station repeater is converted into a bipolar signal and transmitted to the inter-station repeater. A 2.048Mbps line matching unit; While synchronizing the data strings input from the 2.048 Mbps line matching unit, the data is realigned and input to the data storage unit, and a synchronization signal for synchronizing the data strings is input to the signal and clock generation unit. A 2.048 Mbps frame synchronizer for matching frames of the 2.048 Mbps data stream inputted from the input unit and inputting the frames to the 2.048 Mbps line matching unit; A second clock generator for generating a clock of 16.384 MHz; A second clock extraction and synchronization selection for synchronizing phases with the first extracted clock inputted from the 2.048 Mbps line matching unit using the 16.384 MHz as the main clock and inputting the 2.048 Mbps frame synchronizer and the signal and clock generator, respectively. And a data transmission rate converting apparatus comprising a unit. 12. The line matching unit according to claim 11, further comprising a second synchronization state display unit for visually indicating whether the synchronization state of the data string output from the 2.048Mbps line matching unit is normal, while the 2.048Mbps frame synchronization unit And detecting the synchronous state of the data string output from the control unit so as to input the synchronous state normal signal to the second synchronous state display unit to control the second synchronous state display unit to display the synchronous state. . 12. The apparatus of claim 11, further comprising a second input signal display unit for visually displaying a data string input from the inter-station relay device, and a second loopback driver for outputting a local station or a power station loopback drive signal. The 2.048 Mbps line matching unit always monitors the data stream input from the inter-station relay, and transmits a signal to the second input signal display unit to visually display if there is no received data due to disconnection of the line or failure of the inter-station relay. And a loopback drive signal from the own station or the large station to perform the loopback function. 12. The apparatus of claim 11, wherein the second clock extracting and synchronizing selector generates a 2.048 MHz clock on its own regardless of the clock extracted first from the 2.048 Mbps line matching unit. A data transmission rate converter, which is characterized in that it is input to a generator. 4. The apparatus of claim 3, wherein the signal and clock generation unit comprises: a synchronization state detector for outputting a synchronization state normal signal by determining whether a synchronization state of a data string output from the 1.024Mbps line matching unit is normal; A first signal and clock generator for receiving a signal and a clock generated first by the 1.024 Mbps line matching unit and generating a signal and a clock required to process 1.024 Mbps data; And a second signal and clock generator configured to receive a signal and a clock generated by the 2.048 Mbps data matching unit and generate and output a signal and a clock required to process 2.048 Mbps data. Speed converter. 16. The data transmission method of claim 15, wherein the 1.024 Mbps data matching unit further comprises a first synchronization state display unit for visually displaying the synchronization state according to the synchronization state normality signal input from the synchronization state detection unit. Speed converter. 17. The apparatus of claim 16, wherein the synchronization state sensing unit comprises: a shift unit for shifting and outputting a 1.024 Mbps data string input from the 1.024 Mbps line matching unit according to the input pulse; A series of sync bits are found from the data string input by the shift unit. If a series of sync bits is found, a sync acquisition display signal is input to the sync state display unit. If a series of sync bits is not found, a sync loss display signal is found. A synchronization monitoring unit which inputs a to the synchronization status display unit; And a pulse generator for generating a pulse and inputting the pulse to the shift unit when the synchronization loss display signal is input, but not generating a pulse. 16. The apparatus of claim 15, wherein the first signal and clock extractor comprises: a 7-bit counter that counts a 1.024 MHz received clock input from the first clock extractor and synchronization selector to generate and output an 8KHz clock divided by 128; ; A first latch unit for synchronizing and outputting the 8KHz clock output from the 7-bit counter; A first 4-bit counter for counting and outputting the 8 KHz clock inputted from the 1.024 MHz receive clock and the 1.024 Mbps frame synchronizer; A first combination unit configured to combine a clock output from the first 4 bit counter and output a clock of 64 KHz; A first 3-bit counter for counting and outputting a 1.024 Mbps transmit clock input from the 1.024 Mbps frame synchronizer; And a second combination unit configured to combine a clock input from the first 3 bit counter to output a 128 kHz clock. 16. The apparatus of claim 15, wherein the second signal and clock generator comprises: an 8-bit counter configured to receive and receive a 2.048 MHz received clock from the 2.048 Mbps data matching unit to generate and output an 8-KHz clock divided by 256; A second latch unit for synchronizing and outputting the 8KHz clock; A second 4-bit counter for counting and outputting an 8KHz reception synchronization signal and the 2.048MHz reception clock inputted from the 2.048Mbps data matching unit; A third combining unit for combining a clock output from the second 4 bit counter to output a 128 kHz clock; A second 3 bit counter for counting and outputting an 8 kHz transmission synchronization signal and a 2.048 MHz transmission clock input from the 2.048 Mbps data matching unit; And a fourth combination unit configured to combine a clock output from the second 3 bit counter and output a clock of 256 kHz. A 1.024 Mbps data matching unit for rearranging and outputting the data string received from the exchange, inserting and rearranging a synchronization signal in the 1.024 Mbps data string to be transmitted to the exchange, and then transmitting the synchronous signal to the exchange; The 1.024 Mbps data matching unit stores the 1.024 Mbps data stream and rearranges the data stream to be 2.048 Mbps, while temporarily storing the 2.048 Mbps data stream to be transmitted to the exchange. A data storage for rearranging the data to be inputted to the 1.024 Mbps data matching unit; Inserting and rearranging the synchronization signal into the 2.048 Mbps data stream input from the data storage unit and transmitting the synchronization signal to the inter-station relay device, while realigning the data string received from the inter-station relay device and inputting the data to the data storage unit. part; The 1.024 Mbps data matching unit, the data storage unit, and 2.048 are generated by generating a signal and a clock required to convert a 1.024 Mbps data string to a 2.048 Mbps data string, and a clock required to convert a 2.048 Mbps data string to a 1.024 Mbps data string. A signal and clock generation unit provided to the Mbps data matching unit; A data transfer rate conversion device including the 1.024 Mbps data matching unit, a data storage unit, a 2.048 Mbps data matching unit, and a power supply unit for supplying power to a signal generating unit is a maintenance unit of the PCM-32T which is a 2.048 Mbps single station unit. A mounting structure of a data transfer rate conversion device, characterized in that it is mounted in a card type.