KR0135888Y1 - Clamp apparatus of wire bonder - Google Patents
Clamp apparatus of wire bonder Download PDFInfo
- Publication number
- KR0135888Y1 KR0135888Y1 KR2019950034105U KR19950034105U KR0135888Y1 KR 0135888 Y1 KR0135888 Y1 KR 0135888Y1 KR 2019950034105 U KR2019950034105 U KR 2019950034105U KR 19950034105 U KR19950034105 U KR 19950034105U KR 0135888 Y1 KR0135888 Y1 KR 0135888Y1
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- heat block
- clamping
- chip
- lead frame
- lead
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/786—Means for supplying the connector to be connected in the bonding apparatus
- H01L2224/78621—Holding means, e.g. wire clampers
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
본 고안은 와이어본딩 장치 중 리드온 칩형 반도체를 클램핑하는 클램핑 장치에 관한 것으로, 특히 칩의 파손을 방지하기 위해 히트블럭을 슬롯홈으로 제작하고, 리드프레임의 탄성력으로 인한 불량을 제거하기 위해 2점 진공 흡착 방식의 클램핑 수단을 제작하며, 히트블럭에 진공 흡착홀을 다수개 형성함으로써 클램핑 장치를 단일 공용화하여 세팅 시간을 줄이는 것을 특징으로 하는 와이어본더의 클램핑 장치에 관한 것이다.The present invention relates to a clamping device for clamping a lead-on chip type semiconductor among wire bonding devices. In particular, the heat block is made of slot grooves to prevent chip breakage, and two points for removing defects caused by elastic force of the lead frame. The present invention relates to a clamping device of a wire bonder, which manufactures a clamping means of a vacuum adsorption method and forms a plurality of vacuum adsorption holes in a heat block to reduce a setting time by using a single clamping device.
Description
제 1 도는 종래 윈도우 클램핑의 문제점을 설명하기 위한 개략도.1 is a schematic diagram illustrating a problem of conventional window clamping.
제 2 도 a는 종래의 히트블럭 개략도.2 is a schematic view of a conventional heat block.
b는 제 2 도의 a-a' 단면도.b is a-a 'sectional drawing of FIG.
제 3 도는 본 고안의 윈도우 클램프.3 is a window clamp of the present invention.
제 4 도는 본 고안의 윈도우 클램프와 히트블럭으로 리드프레임을 클램핑했을 때의 단면도.4 is a cross-sectional view when the lead frame is clamped with the window clamp and heat block of the present invention.
제 5 도 a는 히트블럭과 다이인덱싱 위치도.5 is a heat block and die indexing position diagram.
b는 제 5 도 a의 우측면도이다.b is a right side view of FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 리드프레임 2 : 접착테이프1: lead frame 2: adhesive tape
3 : 칩 4 : 히트블럭3: chip 4: heat block
5 : 윈도우 클램프 6 : 버큠홀5: window clamp 6: holding hole
7 : 클램핑 조절볼트 8 : 슬릿홈7: clamping adjustment bolt 8: slit groove
본 고안은 와이어본딩 장치 중 리드온 칩형 반도체를 클램핑하는 클램핑 장치에 관한 것으로, 특히 칩의 파손을 방지하기 위해 히트블럭을 슬롯홈으로 제작하고, 리드프레임의 탄성력으로 인한 불량을 제거하기 위해 2점 진공 흡착 방식의 클램핑 수단을 제작하며, 히트블럭에 진공 흡착홀을 다수개 형성함으로써 클램핑 장치를 단일 공용화하여 세팅 시간을 줄이는 것을 특징으로 하는 와이어본더의 클램핑장치에 관한 것이다.The present invention relates to a clamping device for clamping a lead-on chip type semiconductor among wire bonding devices. In particular, the heat block is made of slot grooves to prevent chip breakage, and two points for removing defects caused by elastic force of the lead frame. The present invention relates to a clamping device of a wire bonder, which manufactures a clamping means of a vacuum adsorption method and forms a plurality of vacuum adsorption holes in a heat block to reduce a setting time by using a single clamping device.
일반적으로 리드온 칩형 반도체 패키지는 제 1 도에 도시한 바와 같이, 리드프레임(1) 밑에 접착테이프(2)를 붙이고 칩(3)을 접착한 형태의 반도체 패키지이다.In general, as shown in FIG. 1, a lead-on chip type semiconductor package is a semiconductor package in which an adhesive tape 2 is attached to the lead frame 1 and the chips 3 are bonded to each other.
이러한 리드온 칩형 반도체 패키지는 와이어본딩 위치로 리드프레임이 이송되어 오면 윈도우 클램프(5)와 중앙에 버큠홀(6)이 형성된 히트블럭(4)으로 이루어진 클램프 수단으로 리드프레임을 고정시킨 후 와이어본딩.In the lead-on chip type semiconductor package, when the lead frame is transferred to the wire bonding position, the lead frame is fixed by a clamp means consisting of a window clamp 5 and a heat block 4 having a vent hole 6 formed at the center thereof. .
그러나, 이러한 리드온 칩 반도체 패키지의 히트블럭은 제 2 도(a, b)에 도시한 바와 같이, 오목형(LHx WHx HD)이고, 칩(3)은 리드프레임(1) 밑에 칩이 위치하므로, 오목형 히트블럭(4)에 인덱싱이 잘 안된 상태에서 칩을 클램핑하였을 경우에는 칩(3)이 히트블럭(4)에 부딪쳐 크랙이 생기거나 파손되어 불량이 발생한다.However, the heat block of such a lead-on chip semiconductor package is concave (L H x W H x H D ) as shown in FIGS. 2A and 2B, and the chip 3 is the lead frame 1. Since the chip is located underneath, when the chip is clamped in a state in which the concave heat block 4 is poorly indexed, the chip 3 hits the heat block 4 and cracks or breaks, thereby causing a defect.
또한, 윈도우 클램프(5)로 리드온 칩의 리드프레임 및 칩을 클램핑할 때 칩 주위으 리드프레임 전체를 클램핑 함으로써 제 1 도와 같이 클램핑방향 FW1, FW2의 반대방향으로 탄성력 FE1, FE2가 발생되어 클램핑력을 저하시키고 실제 와이어본딩시 루프 형성에 에러를 유발시키거나 품질을 저하시킨다. 또한, 리드온 칩 종류가 여러가지일 때 칩의 종류에 따른 윈도우 클램프, 히트블럭을 각각 따로사용해야 하며, 디바이스별로 복수개의 클램핑툴을 준비해야 하는 단점이 있으며 디바이스 교체 및 와이어본딩 셋업시 시간이 많이 걸려서 생산성을 저하시킨다.In addition, when clamping the lead frame of the lead-on chip and the chip with the window clamp 5, the entire lead frame is clamped around the chip so that the elastic forces F E1 and F E2 are opposite to the clamping directions F W1 and F W2 as shown in the first diagram. To reduce the clamping force and cause errors in loop formation during actual wirebonding or deterioration of the quality. In addition, when there are various types of lead-on chips, window clamps and heat blocks according to the chip types must be used separately, and a plurality of clamping tools must be prepared for each device, and the device replacement and wire bonding setup takes a lot of time. Decrease productivity.
본 고안은 상기와 같은 문제를 해결코자 하는 것으로, 다양한 종류의 리드프레임을 인덱싱시 다이의 파손을 막고 복수개의 히트블럭 및 클램핑 수단을 준비하지 않아도 되도록 클램핑 수단 및 히트블럭을 새로운 형태로 재구성토록 함을 특징으로 한다.The present invention is to solve the above problems, to prevent the breakage of the die when indexing various types of leadframe and to reconfigure the clamping means and the heat block in a new form so that it is not necessary to prepare a plurality of heat blocks and clamping means. It is characterized by.
즉, 리드프레임 인덱싱시 칩이 히트블럭에 부딪쳐 크랙이 생기거나 파손되는 것을 해결하기 위해 오목형 히트블럭을 슬롯형으로 제작하고, 리드프레임을 클램핑시 유기되는 탄성력의 발생을 줄일 수 있도록 리드프레임을 누르는 부분을 2점면 접촉형으로 제작하며, 또한 히트블럭에 다수개의 진공홀을 구비토록하여 리드온 칩 종류에 관계없이 복수개의 히트블럭 및 클램프 수단을 준비하지 않아도 되도록 장치를 구성한다.That is, in order to solve the cracks or breakage due to the chip hitting the heat block during the indexing of the lead frame, the concave heat block is manufactured in the slot type, and the lead frame is reduced to reduce the generation of elastic force induced when clamping the lead frame The apparatus is constructed so that the pressing portion is made of a two-point contact type, and a plurality of vacuum holes are provided in the heat block so that a plurality of heat blocks and clamp means do not need to be prepared regardless of the lead-on chip type.
이하 도면을 참조로 상세히 설명하면 다음과 같다.Hereinafter, described in detail with reference to the drawings.
제 3, 4 도는 본 고안을 설명하기 위한 클램프의 평면도 및 단면도로써, 여기서 윈도우 클램프 Wc x Lc의 영역을 가지고 2점 클램핑점 C1(W x T1x H)과 C2(W x T2x H)을 형성하고, C1의 클램프힘 FW1과 C2의 클램핑힘 FW2의 균형을 조절해주는 클램핑 조절볼트(7)가 구비되어 있다. 또한, 칩(3) 밑에는 진공 흡착력 FV로 칩이 충분히 흡착될 수 있도록 진공 흡착홀(6)을 다수개 형성하며, 히트블럭(4)은 제 5 도에 도시한 바와 같이, 리드프레임 인덱싱시 인덱싱 방향으로 칩이 전혀 간섭을 받지 않도록(크랙이나 파손되지 않도록) LHx HD의 슬롯홈(8) 형태로 형성한다. 여기서 9 는 본딩영역, 즉 윈도우 클램프 영역에 놓인 칩이고, 10 은 인덱싱할 때 히트블럭에 위치한 칩을 나타낸다.3 and 4 are plan and cross-sectional views of the clamp for explaining the present invention, where the two-point clamping points C 1 (W x T 1 x H) and C 2 (W x T 2 with the area of the window clamp Wc x Lc); forming an x H) and has a clamping control bolt (7 which controls the clamp force of the C 1 and C 2 F W1 W2 clamping force F of the balance) is provided. In addition, a plurality of vacuum suction holes 6 are formed under the chip 3 so that the chips can be sufficiently sucked by the vacuum suction force F V , and the heat block 4 has lead frame indexing as shown in FIG. In the indexing direction, the chip is formed in the shape of the slot groove 8 of L H x H D so that the chip does not interfere at all (not crack or break). Where 9 is a chip placed in the bonding area, that is, the window clamp area, and 10 is a chip located in the heat block when indexing.
상기와 같이 구성하는 본 고안은 와이어본딩을 위해 리드프레임(1)이 가이드레일의 안내에 따라 1피치씩 이송되어 와이어본딩 위치에 도착하면, 클램핑 장치인 윈도우 클램프(5)의 하강동작과 히트블럭(4)의 상승동작으로 리드프레임(1)의 클램프 동작이 이루어진다. 하강동작을 하는 윈도우 클램프(5)는 WCx LC의 영역을 가지고 리드프레임(1)을 누르는 부분을 2점 클램핑점 C1(W x T1x H)과 C2(W x T2x H) 그리고 C1의 클램핑힘 FW1과 C2의 클램핑힘 FW2의 균형을 조절해 주는 밸런스포스 FB로 윈도우 클램핑을 하고, 칩(3) 밑에서는 본 고안의 히트블럭(4)이 위치하며, 칩에 정해진 온도로 열을 가해주면서 동시에 진공 흡착홀을 복수개를 가지고 칩을 진공 흡착시켜 고정시킨다. 또한, 히트블럭(4)은 인덱싱 방향으로 칩이 전혀 간섭받지 않도록(크랙이나 파손되지 않도록) LHx HD의 홈을 파준다. N개의 진공홀이 있는 히트블럭의 경우 진공 흡착력 FV= FV1= FV2= FV3+ ..... FN이다.According to the present invention configured as described above, when the lead frame 1 is moved by one pitch according to the guide rail guide and arrives at the wire bonding position for wire bonding, the lowering operation and the heat block of the window clamp 5 which is a clamping device. The clamping operation of the lead frame 1 is performed by the raising operation of (4). The lower window clamp (5) has an area of W C x L C and presses the lead frame (1) to the two-point clamping points C 1 (W x T 1 x H) and C 2 (W x T 2). x H) and the heat block of a C 1 clamping force F W1 and C 2 clamping force F to balance force window clamped to F B which adjusts the balance of W2, and the chip 3 from the bottom, the present design of the 4 a Located at the same time, heat is applied to the chip at a predetermined temperature, and at the same time, the chip is vacuum-adsorbed and fixed with a plurality of vacuum suction holes. In addition, the heat block 4 digs the groove of L H x H D so that the chip is not interfered at all (not cracked or broken) in the indexing direction. For a heat block with N vacuum holes, the vacuum suction force F V = F V1 = F V2 = F V3 + ..... F N.
이 때, 클램핑력의 클램핑포스 FC= FW1+ FW2+ FV이며 (종래에는 FC= FW1+ FW2+ FV- FE1- FE2), 여기서 FW1, FW2는 FV에 의한 보조포스로서 리드프레임이 좌우 방향으로 흔들리지 않도록 해주는 힘이고, FE1, FE2는 와이어본딩시 리드프레임 윗쪽으로 반발하는 힘이다. 또한, 클램핑점 C1, C2가 리드프레임에 두 점이 닿으므로써 종래 리드프레임 전체 원둘레면을 닿는 것보다 훨신 안정감있게 리드프레임을 클램핑할 수 있다.At this time, the clamping force of the clamping force F C = F W1 + F W2 + F V (in the past, F C = F W1 + F W2 + F V -F E1 -F E2 ), where F W1 , F W2 is F As a sub force by V , the lead frame does not move in the left and right directions, and F E1 and F E2 are the forces that repulse upward on the lead frame during wire bonding. In addition, since two points of the clamping points C 1 and C 2 are in contact with the lead frame, the lead frame can be clamped with much more stability than touching the entire circumferential surface of the conventional lead frame.
한편 와이어본딩이 완료되면 언클램핑 동작(윈도우 클램프 상승동작과 히트블럭 하강동작)을 하게되는데 이 때 진공 흡착 FV는 오프된다.On the other hand, when wire bonding is completed, an unclamping operation (window clamp raising operation and heat block lowering operation) is performed. At this time, vacuum adsorption F V is turned off.
상술한 바와 같이 본 고안은 히트블럭을 슬롯홈으로 제작하여 칩의 파손을 방지하고, 2점 진공 흡착방식의 클램핑 수단을 이용하여 리드프레임 탄성력으로 인한 불량르 제거하여 와이어본딩의 품질을 향상시키며, 히트블럭에 진공 흡착홀을 다수개 형성함으로써 클램핑 장치를 단일 공용화하여 세팅 시간을 줄일 수 있다.As described above, the present invention improves the quality of wire bonding by fabricating a heat block as a slot groove to prevent chip breakage and removing defects caused by lead frame elasticity by using a two-point vacuum adsorption clamping means. By forming a plurality of vacuum suction holes in the heat block, the clamping device can be shared by a single unit, thereby reducing the setting time.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019950034105U KR0135888Y1 (en) | 1995-11-17 | 1995-11-17 | Clamp apparatus of wire bonder |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019950034105U KR0135888Y1 (en) | 1995-11-17 | 1995-11-17 | Clamp apparatus of wire bonder |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970025821U KR970025821U (en) | 1997-06-20 |
| KR0135888Y1 true KR0135888Y1 (en) | 1999-03-20 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019950034105U KR0135888Y1 (en) | 1995-11-17 | 1995-11-17 | Clamp apparatus of wire bonder |
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| Country | Link |
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| KR (1) | KR0135888Y1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101113847B1 (en) * | 2005-06-30 | 2012-02-29 | 삼성테크윈 주식회사 | Wire bonder for preventing electrical over-stress damage |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100345680B1 (en) * | 1999-10-20 | 2002-07-27 | 주식회사 하이닉스반도체 | Apparatus for fixing a lead on chip package in wire bonder |
| KR100377469B1 (en) * | 1999-12-10 | 2003-03-26 | 앰코 테크놀로지 코리아 주식회사 | Clamp for Bonding Wire of Ball Grid Array Semiconductor Packages and Method for Checking the Bonding Wire Using the same |
-
1995
- 1995-11-17 KR KR2019950034105U patent/KR0135888Y1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101113847B1 (en) * | 2005-06-30 | 2012-02-29 | 삼성테크윈 주식회사 | Wire bonder for preventing electrical over-stress damage |
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| Publication number | Publication date |
|---|---|
| KR970025821U (en) | 1997-06-20 |
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