KR0133956B1 - Mask-rom semiconductor device and manufacturing method thereof - Google Patents

Abstract

The gate electrode is formed on the main surface of the P-type semiconductor substrate with a gate insulating film.

The low concentration impurity region is formed using a gate electrode as a mask.

Then, a spacer is formed on the sidewall of the gate electrode, and a high concentration impurity region is formed using the spacer as a mask.

After removing the spacer of the intended transistor, the n-type impurity is implanted by low energy forming a punch through the implanted layer using the gate electrode and the spacer as a mask.

As a result, a mask ROM having high reliability is formed in a short production period without using an expensive device.

Description

Mask ROM Semiconductor Device and Manufacturing Method Thereof

1 is a cross-sectional view of a mask ROM of an embodiment of the present invention.

2 is a cross-sectional view showing a cross section orthogonal to the cross section shown in FIG. 1 as a cross-sectional view of the mask ROM of the embodiment of the present invention.

FIG. 3A is a partially enlarged cross-sectional view of a transistor serving as a memory device in a mask ROM according to an embodiment of the present invention, and FIG.

4A is a partially enlarged cross-sectional view showing the shape of a transistor serving as a memory element in the mask ROM of the embodiment of the present invention, and FIG. 4B is a cross-sectional view showing a concentration distribution of impurity regions of the transistor.

5 through 16 are cross-sectional views showing the first to twelfth steps of the manufacturing process of the mask ROM according to the embodiment of the present invention.

17 to 28 are sectional views showing the first to twelfth steps of the manufacturing process of the mask ROM of the embodiment of the present invention corresponding to the sectional view shown in FIG.

Fig. 29 is a sectional view showing another method of manufacturing the mask ROM according to the embodiment of the present invention.

30 is a sectional view of a mask ROM of another embodiment of the present invention.

31 through 38 are cross-sectional views showing the first to eighth steps of the manufacturing process of the mask ROM according to another embodiment of the present invention.

Fig. 39 is a sectional view showing a mask ROM of another embodiment of the present invention.

FIG. 40A is a partially enlarged cross-sectional view of the transistor in which the ROM data shown in FIG. 39 is written, and FIG. 40B is a view showing the concentration distribution of impurity regions of the transistor shown in FIG. 40A.

41 to 47 are sectional views showing the first to seventh steps of the manufacturing process of the mask ROM according to still another embodiment of the present invention.

FIG. 48 is a cross-sectional view showing another method of manufacturing the mask ROM shown in FIG. 39, showing a state in which ROM data is recorded by an oblique rotation ion implantation method.

FIG. 49 is a cross-sectional view showing another method of manufacturing the mask ROM shown in FIG. 39, showing a state in which ROM data is written using a resist as a mask. FIG.

50 is a cross-sectional view showing a mask ROM of yet another embodiment of the present invention.

51 to 58 are sectional views showing the first to eighth steps of the manufacturing process of the mask ROM according to still another embodiment of the present invention.

Fig. 59 is a sectional view showing a mask ROM of still another embodiment of the present invention.

60 to 65 are cross-sectional views showing a first step of a manufacturing process of a mask ROM according to still another embodiment of the present invention.

FIG. 66 is a cross-sectional view showing another method of manufacturing the mask ROM shown in FIG. 59, showing a state in which ROM data is written using a register as a mask. FIG.

67 is a cross-sectional view showing a mask ROM of yet another embodiment of the present invention.

68 to 75 are cross-sectional views showing the first to eighth steps of the manufacturing process of the mask ROM according to yet another embodiment of the present invention.

76 is an equivalent circuit diagram schematically showing a NAND type mask ROM.

77 is an equivalent circuit diagram schematically showing a NOR type mask ROM.

78 is a plan view showing an example of a NAND type mask ROM in the prior art.

FIG. 79 is an equivalent circuit diagram of the NAND type mask ROM shown in FIG. 78;

80 is a cross-sectional view taken along the line A-A of FIG. 78;

FIG. 81 is a cross sectional view along line B-B of FIG. 78;

82 to 92 are sectional views showing the first to eleventh steps of the manufacturing process of the NAND mask ROM of the prior art corresponding to the sectional view of FIG.

93 to 103 are sectional views showing the first to eleventh steps of the manufacturing process of the NAND mask ROM of the prior art corresponding to the sectional view of FIG.

104 is a plan view showing an example of a prior art NOR mask ROM.

105 is an equivalent circuit diagram of the NOR mask ROM shown in FIG. 104;

106 through 114 are cross-sectional views showing the first to ninth steps of the manufacturing process of the NOR mask ROM of the prior art.

115A and 115A are sectional views showing a state in which ROM data is written by high energy ion implantation so as to penetrate the gate electrode of a conventional NAND type mask ROM.

116a and b are cross sectional views showing a state in which ROM data is written by high energy ion implantation so as to penetrate the gate electrode of a conventional NOR type mask ROM.

* Explanation of symbols for main parts of the drawings

1, 20, 40, 100, 130: p-type semiconductor substrate 2, 102: oxide film

3, 103, 133: device isolation oxide film

6, 26, 46, 106, 136: gate insulating film

7, 7a, 7b, 7c, 27, 27a, 27b, 47, 47a, 107, 137: gate electrode

8, 28, 48, 108, 138: low concentration impurity regions 9, 29, 49, 109, 139: CVD film

10, 30, 50, 110, 140: Space

11, 31, 51, 111, 141: high concentration impurity region

12, 32, 52, 112, 142: interlayer insulating film

13, 33, 53, 113, 143: contact hole

14, 34, 54, 114, 144: wiring layers 15, 35, 55, 115: protective film

16, 17, 38, 39, 56, 57, 104, 134, 116, 146: register pattern

36: n-type impurity layer 60: punch-through injection layer

60a: p-type impurity region 61: impurity introduction layer

61a: p-type impurity layer 63, 132: channel cut injection layer

101, 131: stress buffer film 105: deflection injection layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mask ROM (Read Only Memory) semiconductor device, and more particularly, to a mask ROM semiconductor device and a method for manufacturing a mask ROM semiconductor device capable of recording ROM data by ion implantation with relatively low energy and shortening a delivery time. .

In recent years, semiconductor devices such as semiconductor memories have been widely used in various electronic devices, including calculator systems and measurement systems.

As described above, a semiconductor device capable of being a semiconductor memory includes a semiconductor device (hereinafter referred to as a mask ROM) called a mask ROM semiconductor device. This mask ROM has a feature that can record information in advance during the manufacturing process, and can store data having different contents depending on the presence or absence of a field oxide film, the presence or absence of a contact hole, and the ion implantation into a channel region. Semiconductor device.

In recent mask ROMs, high integration is easy, and the lead time from data writing to completion of the semiconductor device can be relatively short, so that data is often stored with or without ion implantation into the channel region.

This mask ROM includes a NOR mask ROM and a NAND mask ROM. Here, the NOR-type mask ROM and the NAND-type mask ROM will be briefly described with reference to FIGS. 76 and 77. FIG.

FIG. 76 is an equivalent circuit diagram schematically showing an example of a NAND type mask ROM, and FIG. 77 is an equivalent circuit diagram schematically showing an example of a NOR type mask ROM.

In general, since a NAND type mask ROM can be configured with a plurality of transistors (for example, eight or sixteen) selected for one bit line, it can be said that one contact hole can be configured for a plurality of transistors. Can be.

Referring to FIG. 76, bit lines BL1 and BL2 are formed, and are connected to the transistor rows 1a and 1b through bit line contacts BC1 and BC2, respectively.

In this case, the transistor column 1a is composed of four transistors, and these four transistors are connected in series, and both ends thereof are connected to the bit line BL1 and the source line SL1, respectively.

In the same manner, four transistors are connected in series to form transistor column 1b, one end of transistor column 1b is connected to bit line BL2 through bit line contact BC2, and the appropriate is connected to source line SL2. Word lines WL1 to WL4 are formed in the direction orthogonal to the bit lines BL1 and BL2.

Impurities are ion-implanted in the diagonally-transistor transistor in the figure, and the threshold voltage of the transistor is adjusted.

In this case, the threshold suppression of the oblique transistor is adjusted to a value (almost ground potential) lower than the threshold voltage of the non oblique transistor.

The operation of the NAND type mask ROM will be described below. Referring to FIG. 76, for example, to select the transistor 70 surrounded by circles in the figure, a predetermined voltage is applied to the bit line BL1.

The word line WL3 of the transistor 70 is set to the ground potential, and a predetermined potential is applied to the other word lines WL1, WL2, and WL4, respectively.

At this time, since the threshold voltage is adjusted so that the threshold voltage is almost at the ground low, current flows through the transistor 70 even though the word line WL3 is maintained at the ground potential.

At this time, the source lines SL1 and SL2 are held at the ground potential, and in this case, ROM data is selected in the transistor (in this case, the transistor 70) selected according to whether a current flows between the bit line BL1 and the source line SL1. It is determined whether is recorded.

In the above-described NAND mask ROM, the transistor in which the ROM data is written maintains the deflection state, and in particular, the impurity is formed so as to have a threshold voltage Vth lower than the threshold voltage Vth of the transistor in which the ROM data is not written. It is regulated by introduction.

This reason is demonstrated below.

In addition, in the following description, as the impurity is introduced into the channel region as described above, the transistor whose threshold voltage Vth is adjusted is referred to as a transistor in which ROM data is written.

In the NAND type mask ROM, since a plurality of transistors constitute a transistor row, it is judged whether or not the ROM data is written by whether or not current flows in the transistor row. Therefore, it is necessary to select one transistor in the transistor column and determine whether or not the ROM data is written in the transistor based on whether or not a current flows in the transistor. There must be current flowing through it.

In this case, when the threshold voltage Vth of the transistor on which the ROM data is written is higher than the threshold voltage Vth of the transistor on which the ROM data is not written, the current in the transistor column is blocked by the transistor, so that the ROM data The threshold voltage Vth of the transistor on which is written is adjusted so as to have a threshold voltage Vth lower than the transistor threshold voltage Vth on which ROM data is not written.

In other words, the transistor on which the ROM data is written needs to be a deflection transistor by introducing impurities.

Next, referring to FIG. 77, the NOR type mask ROM type will be described. The NOR type mask ROM selects one word line and one bit line, and since one transistor can be selected, one contact hole is formed for one or two transistors.

In other words, one or two contact holes are formed for the two transistors.

Referring to FIG. 77, bit lines BL1 and BL2 are formed in parallel with each other, and word lines WL1 to WL4 are formed in a direction orthogonal to these bit lines BL1 and BL2.

In this case, bit line contacts BC1 to BC4 are formed for the two transistors, respectively.

At this time, the source lines SL1 to SL6 are maintained at ground potentials, respectively. In the figure, the oblique transistors are transistors in which ROM data is written, and the threshold voltages Vth of these transistors are adjusted to be higher than the threshold voltage Vth of transistors in which ROM data is not written.

The operation of the NOR type mask ROM will be described below.

Referring to FIG. 77, the case where the transistor 71 surrounded by circles is selected in the figure will be described.

In this case, a high voltage is applied to the bit line BL2, and a high voltage is also applied to the word line WL2 of the transistor 71 to be selected.

At this time, the voltages applied to the bit lines BL2 and WL2 are lower than the threshold voltage Vth of the transistor in which the ROM data is written and greater than the threshold voltage Vth of the transistor in which the ROM data is not written.

The other word lines WL1, WL3, and WL4 are applied with a voltage lower than the threshold voltage Vth of the transistor in which ROM data is not written.

As a result, when ROM data is written into the transistor 71, no current flows between the bit line BL2 and the source line SL5, and when no ROM data is written into the transistor 71, the bit line BL2 and the source line SL5. Current flows in between.

As a result, it is determined whether or not the ROM data is recorded in the transistor 71.

In this case, since ROM data is not written to the transistor 71, a current flows in the transistor 71.

As described above, the threshold voltage of the transistor in which the ROM data is written in the NOR type mask ROM is higher than the threshold voltage of the transistor in which the ROM data is not written for the following reason.

Referring to the NOR mask ROM shown in FIG. 77 by way of example, for example, when a high potential is applied to the bit line BL2 and a high potential is applied to the word line WL2, that is, when the transistor 71 is selected, the same bit is used. The high potential is also applied to the drain region of the transistor 72 adjacent to the transistor 71 through the line contact BC3.

The threshold voltage Vth must be adjusted so that a current does not flow through this transistor 72.

In other words, by writing ROM data such as a deflection transistor in the NAND mask ROM, a transistor of a type lower than the threshold voltage Vth of a transistor in which ROM data is not written cannot be obtained.

Thus, the threshold voltage Vth of the transistor in which the ROM data is written must be adjusted to be higher than the threshold voltage Vth of the transistor in which the ROM data is not written.

Although the NAND type mask ROM and the NOR type mask ROM have been described in outline above, each will be described in more detail below.

First, as an example of a conventional example of a NAND type mask ROM, a case of a 16-stage NAND type deflection ROM will be described as an example.

78 is a plan view of the 16-stage NAND type deflection ROM.

Referring to FIG. 78, in the NAND type deflection ROM, an element isolation oxide film 103 formed by, for example, an oxide film by LOCOS (Local Oxidation of Silicon) method is formed in parallel with each other.

A plurality of gate electrodes 107 are formed so as to be orthogonal to the element isolation oxide film 103.

The gate electrode 107 is formed on a semiconductor substrate via a gate insulating film, and is formed of, for example, a multilayer film of polycrystalline silicon and a high melting point metal silicide.

Among the gate electrodes 107 formed of a plurality (16 in this case) may function as the selection gates S0 and S1 or as the word lines Wo to Wf.

On the semiconductor substrate and the gate electrode 7, for example, bit lines B0 to B3 and source lines in a direction orthogonal to the gate electrode 107 through an interlayer insulating film made of, for example, a BPSG (Boro Silicate Glass) film deposited by CVD. SL0 and SL1 are formed.

The bit lines B0 to B3 and the source lines SLO and SL1 are made of, for example, an aluminum alloy.

The bit lines B0 to B3 and the net line contact lines BC0 to BC3 are connected to the impurity diffusion region (drain region) formed in the semiconductor substrate. The source lines SL0 and SL1 are connected to an impurity diffusion region (source region) formed in the semiconductor substrate through the source line contacts SC0 and SC1.

A protective film (not shown) is formed on the bit lines B0 to B3 and the source lines SL0 and SL1.

This protective film is, for example, a cut film formed by plasma CVD.

FIG. 79 shows an equivalent circuit diagram of the 16-stage NAND type large operation ROM having the above structure.

Referring to FIG. 79, transistor columns 0a to 4a, 0b to 3b, 0c to 4c, and 0d to 3d in which a plurality of transistors are connected in series with each other are formed in parallel with each other.

One end of each transistor string is connected to the bit lines B0 to B4 through the bit line contacts BC0 to BC4. The other ends of the transistor rows 0a to 4a and 0b to 3b are connected to the source lines SL0 to SL2 through the source line contacts SC0 to SC2.

The select gates S0, S1, and the word lines Wo-Wf are formed in the direction orthogonal to the bit lines B0 to B4 and the source lines SL0 to SL2.

The diagonal transistor in the figure is a transistor in which ROM data is written. In this case, a transistor having a low threshold voltage is adjusted by ion implantation for writing ROM data.

Hereinafter, the structure of the 16-stage NAND type deflection ROM will be described in more detail with reference to FIGS. 80 and 81. FIG. 80 shows a cross-sectional view taken along the line A-A of FIG. 78, and FIG. 81 shows a cross-sectional view taken along the line B-B of FIG. Referring to FIG. 80, an n-type low concentration impurity region 108 is formed on the main surface of the p-type semiconductor substrate 100 at predetermined intervals.

Gate electrodes 107 (S0, S1, W0, We, Wf) are formed on the channel region defined by the low concentration impurity region 108 through the gate insulating film 106.

An n-type high concentration impurity region 111 is formed, which has an end portion at a position farther from the gate electrode 107 than the end portion of the low concentration impurity region 108, and extends away from the gate electrode 107.

Spacers 110 are formed on the sidewalls of the respective gate electrodes 107. An n-type impurity diffusion layer (hereinafter referred to as a deflection injection layer) 105 is formed in the channel region under the predetermined gate electrode 107 (S0 and Wf).

By this deflation injection layer 105, in this case, the threshold voltage Vth of the transistor including the gate electrodes S0 and Wf is changed into a deep deflection state at a value of about 0 to 1V.

An interlayer insulating film 112 made of a BPSG film or the like is formed on each gate electrode 107, the spacer 110, and the p-type semiconductor substrate 100.

On the interlayer insulating film 112, a wiring layer 114 made of, for example, aluminum alloy is formed.

In this case, this wiring layer 114 corresponds to bit line B1 in FIG.

At a predetermined position of the interlayer insulating film 112, a contact hole 113 for connecting the impurity region formed in the p-type semiconductor substrate 100 and the wiring layer 114 is formed. In this case, the contact hole 113 corresponds to the bit line contact hole BC1 in FIG. On the wiring layer 114, a protective film 115 made of a nitride film is formed.

Referring to FIG. 81, an isolation layer 103 is formed on the main surface of the p-type semiconductor substrate 100 at intervals.

The deflection injection layer 105 is formed between the predetermined isolation oxide layer 103.

A gate insulating film 106 is formed on the surface of the p-type semiconductor substrate 100 positioned between the device isolation oxide film 103, and the gate electrode 107 is formed on the gate insulating film 106 and the device isolation oxide film 103. Is formed.

Since the interlayer insulating film 112 is formed on the gate electrode 107, the wiring layer 114 (B0, B1, SL1) is formed in a predetermined region on the interlayer insulating film 112.

In this case, as shown in the figure, the wiring layer 114 corresponds to the bit lines B0, B1 and the source line SL1 in FIG.

A protective film 115 made of a nitride film or the like is formed on the wiring layer 114 and the interlayer insulating film 112.

In the case of a NAND type mask ROM, as shown in Figs. 78 and 79, it is common to have the selection gates SO and Sl.

In this case, as shown in FIG. 79, the deflection injection layer 105 is formed in the channel region of either of the selection gates S0 and S1 in the same transistor row.

The transistor in which the deflection injection layer 105 is formed corresponds to the deflection transistor.

The deflection injection layer 105 is formed in the channel region of the desired word line in accordance with the data contents to be stored in the word lines W0 to Wf.

Therefore, a deflection transistor according to the data content is formed in memory.

Next, referring to FIG. 79, the operation of the NAND type deflection ROM will be described.

Referring to FIG. 79, a deflection injection layer 105 is formed on one of the transistors formed by the selection gates S0 and S1 of each transistor inverse (hereinafter referred to as NAND column).

In addition, a deflection transistor is not formed at the same time as the NAND columns (for example, columns 1a and 1b) of the same select gate.

In other words, the deflection transistors are arranged in a zigzag shape in the selection gates S0 and S1.

Four NAND columns, in this case columns 1a to 1d, are connected to one bit line contact, for example, the bit line contact BC1.

When reading, one of the NAND columns is selected by the selection gates S0 and S1.

For example, in order to select the column 1b, a high potential, in this case, about 2 to 5 V is applied to the bit line B1 connected to the bit line contact BC1, so that the selection gate S0 is high potential, in this case the selection gate. A voltage equal to or higher than the threshold voltage Vth of the transistor formed by S0 is applied to make the selection gate S1 low (ground level).

The source lines SL0 to SL2 and the other select gates are all set to the ground level, not shown.

At this time, since the high potential is applied to the bit line B1, the high potential is applied to the NAND columns 1a to 1d through the bit line contact BC1.

However, for the NAND columns 1c and 1d, either of the select gates becomes a low potential (ground level), so no current flows in the columns 1c and 1d.

On the other hand, since the high potential is applied to the selection gate S0, no current flows through the transistor formed by the selection gate S0 in the columns 1a and 1b.

However, since the selection gate S1 is at a low potential (ground level), current flows through the deflection transistor formed by the selection gate S1 in the column 1b, but no current flows through the transistor formed by the selection gate S1 in the column 1a. Do not.

By this, the column 1b is selected.

Next, after the NAND column 1b is selected as described above, whether ROM data is recorded in the transistors of the NAND column, that is, when a transistor is selected, the deflection injection layer 105 is formed in the transistor. A case of judging whether or not there is a description will be described.

After selecting column 1b as described above, in this case, the word line Wd is set to the low potential (ground level), and the other word lines W0 to Wc, We, and Wf are not formed with the high potential (diffusion injection layer 105). The voltage is equal to or higher than the threshold voltage Vth of the transistor.

As a result, the transistors having word lines other than the word lines Wd in the column 1b as the gate electrodes are in a conductive state regardless of the presence or absence of the deflection injection layer 105.

Whether or not current flows between the bit line B1 and the source line SL1 is determined by whether or not current flows through the transistor having the word line Wd as the gate electrode.

In this case, as shown in FIG. 79, a deflection injection layer 105 is formed in this transistor so that a current flows.

If the deflection injection layer 15 is not formed in this transistor, no current flows.

By detecting the current flowing in the bit line B1 in this manner, it is possible to determine whether or not the deflection injection layer 105 is formed in the channel region of the selected transistor.

That is, the presence or absence of the deflection injection layer 105 makes it possible to store data 0 and 1.

Next, a method of manufacturing the 16-stage NAND type deflection ROM will be described.

82 to 92 are sectional views showing a part of the main cross section taken along the line A-A in FIG. 78, and correspond to FIG.

93 to 103 show part of a cross section taken along line B-B in FIG. 78, and correspond to FIG.

82 to 92 correspond to FIGS. 93 to 103 and show the same steps in the manufacturing process.

Hereinafter, a method for manufacturing a 16-stage NAND type deflection ROM will be described with reference to FIGS. 82 to 103. FIG.

First, referring to FIGS. 82 and 93, for example, a stress buffer film 101 such as a thermal oxide film is formed on the p-type semiconductor substrate 100 to buffer stress when forming the device isolation oxide film 103. do.

At this time, the p-type semiconductor substrate 100 introduces p-type impurities, such as boron (B), into the semiconductor substrate using ion implantation as needed, and forms p wells by thermal diffusion.

In the peripheral circuit portion, n-type impurities such as phosphorus (P) are introduced by ion implantation and thermally diffused to form n wells.

On the stress buffer film 101, an oxide film 102, such as a nitride film, is formed by CVD.

Next, the oxidation resistant film 102 is patterned using known photolithography and etching techniques. By thermal oxidation using the patterned inner oxide film 102 as a mask, an element isolation oxide film 103 is formed as shown in FIG.

In this state, under the device isolation oxide film 103, in order to increase the threshold voltage Vth of the parasitic transistor by the gate electrode 107 formed over the device isolation oxide film 103 to a sufficiently high value, the boron ( P type impurities such as B) are often introduced.

Subsequently, as shown in FIG. 83 and FIG. 94, the oxide film 102 is removed, and if necessary, a portion corresponding to the memory cell array region or the channel region of the surrounding p-type channel and n-type transistor is provided. The p-type and n-type impurities are introduced by a method such as an ion implantation method to adjust the threshold voltage Vth of each transistor.

Next, as shown in FIGS. 84 and 95, a resist pattern 104 is formed so as to expose a portion corresponding to a channel region of a desired transistor among the transistors formed by the selection gate and the word line.

Then, by using an ion implantation method using the resist pattern 104 as a mask, an n-type impurity such as phosphorus (P) is introduced into a portion corresponding to the channel region to form a deflection injection layer 105.

Subsequently, as shown in FIG. 85 and FIG. 96, the stress buffer film 101 is removed and a gate insulating film 106 made of an oxide film is formed by thermal oxidation.

The gate electrode material is deposited on the gate insulating film 106 by CVD, sputtering, or the like.

The gate electrode 107 is formed by patterning the deposited gate electrode material using known photolithography and etching techniques.

At this time, high melting point silicides based on polycrystalline silicon or polycrystalline silicon are commonly used as gate electrode materials.

Next, as shown in FIG. 86, n-type impurities such as phosphorus (P) and arsenic (As) are ion-implanted into portions corresponding to the source / drain regions of the n-type transistor using the gate electrode 107 as a mask. To form a low concentration impurity region 108 having a concentration of 10 ¹⁷ to 10 ¹⁹ cm ^-3 .

The low concentration impurity region 108 is formed to suppress the deterioration of transistor characteristics by weakening the electric field near the drain region.

Then, as shown in FIG. 87 and FIG. 98, on the gate insulating film 106 and the gate electrode 107 using the CVD method, an oxide film, a nitride film, a polycrystalline silicon film, or the like using the CVD method. The CVD film 109 is deposited.

As shown in FIG. 88, etching is performed until the CVD film 109 of the flat portion is completely removed by anisotropic etching, leaving the CVD film 109 on the sidewall of the gate electrode 107. As shown in FIG.

As a result, the spacer 110 is formed.

Next, as shown in FIG. 88, n-type impurities such as phosphorus (P) and arsenic (As) are ion-doped in portions corresponding to the source / drain regions of the n-channel transistor using the spacer 110 as a mask. Is introduced to form a high concentration impurity region 111 of about 10 ²⁰ to 10 ²² cm ^-3 .

Next, as shown in FIG. 90 and FIG. 101, on the p-type semiconductor substrate 100, the spacer 110 and the gate electrode 107, an oxide film, PSG (Phospho Silicate Glass) by CVD method is used. ) Interlayer insulating film 112 is formed of a film, a BPSG film or a multilayer film thereof.

As shown in FIG. 91, the contact hole 113 is opened in a desired place of the interlayer insulating film 112 using a known photolithography technique and an etching technique. The interlayer insulating film 112 is generally planarized using a reflowing of a PSG film, a BPSG film by heat treatment, or a coating planarizing film such as spin on glass (SOG).

Subsequently, as shown in FIGS. 92 and 103, the wiring material is deposited using a sputtering method, a CVD method, or the like, and then patterned using a known photolithography technique and an etching technique to form the wiring layer 114. Form.

As the wiring material, an aluminum alloy containing silicon (Si), copper (Cu) or the like as an additive, a high melting point metal film, a silicide of a high melting point metal, a nitride of a high melting point metal, and a composite film thereof are used.

On the wiring layer 114, a protective film 115, such as a nitride film or an oxide film, is formed by the CVD method.

At this time, the connection terminal part with the exterior is opened.

In this way, the 16-stage NAND type deflection ROM shown in Figs. 80 and 81 is completed.

Next, the structure of the NOR type mask ROM will be described with reference to FIG.

101 is a plan view showing an example of a NOR type mask ROM.

As shown in FIG. 104, the plurality of element isolation oxide films 133 are formed in island shapes at intervals.

In plan view, the bit lines B0 to B2 and the source line SL1 are formed at positions where the element isolation oxide film 133 is sandwiched.

Word lines W0 to W5 are formed in a direction substantially orthogonal to the bit lines B0 to B2 and the source line SL1.

The bit lines B0 to B2 are connected to the drain region of the transistor formed in the semiconductor substrate through the plurality of bit line contacts BC0 to BC8.

On the other hand, the source line SL1 is connected to the source region of the transistor formed in the semiconductor substrate through the plurality of source line contacts SC0 to SC3.

A transistor including word lines W0 to W5 as a gate electrode is formed at a position where the bit lines B0 to B2 and the word lines W0 to W5 overlap.

This transistor becomes a memory element.

In the transistor serving as the memory element, the impurity concentration in the channel region is adjusted. When ROM data is written, p-type impurities such as boron (B) are introduced into the channel region of the desired transistor in the transistor serving as the storage element.

As a result, the threshold voltage Vth of the transistor is adjusted to be higher than the threshold voltage Vth of the transistor where the ROM data is not written.

Next, the read operation of the transistor to which the ROM data is written using FIG. 105 will be described.

105 is an equivalent circuit diagram of the NOR mask ROM shown in FIG.

As shown in FIG. 105, it is assumed that ROM data has been written to a diagonal transistor.

That is, the diagonal threshold voltage Vth is adjusted to be higher than the threshold voltage Vth of the transistor which is not diagonal.

A method of selecting a transistor surrounded by circles in Fig. 105 and determining whether or not ROM data is recorded in the transistor will be described.

First, in order to select the transistor surrounded by the circle, a high potential is applied to the bit line B1 and the word line W1.

Thereby, the transistor surrounded by the circle is selected in the figure.

At this time, the semiconductor substrate and the source line SL1 are maintained at the ground potential.

The value of the voltage applied to the word line W1 is set to be lower than the threshold voltage of the transistor in which the ROM data is written and higher than the threshold voltage of the transistor in which the ROM data is not written.

Therefore, in this case, since ROM data is recorded in the transistor surrounded by circles in the figure, no current flows between the bit line B1 and the source line SL1.

If ROM data is not written to the transistor surrounded by circles, current flows between the bit line B1 and the source line SL1.

In this way, by detecting the current flowing between the bit line and the source line, it is determined whether or not the ROM data is recorded in the channel region of the selected transistor.

Next, the manufacturing method of the said NOR type mask ROM is demonstrated using FIG. 106!

106 to 114 are sectional views taken along the line C-C in FIG.

Referring to FIG. 106, in the same manner as in the case of the NAND type deflection ROM, the stress buffer film 131 is formed, and the element isolation oxide film 133 is formed.

If necessary, impurities in the region serving as the channel region of the transistor are implanted to adjust the impurity concentration of the channel region.

The resist pattern 134 is formed to expose the channel region of the desired transistor.

Then, using the resist pattern 134 as a mask, ion implantation of p-type impurities such as boron (B) forms the channel cut injection layer 132 having a concentration of about 10 ¹² to 10 ¹⁴ cm ^-2 .

Next, referring to FIG. 107, the stress buffer layer 131 formed on the p-type semiconductor substrate 130 is removed to form a gate insulating layer 136.

The gate electrode 137 is formed using the same method as the NAND type deflection ROM.

Subsequently, as shown in 108, the n-type impurities such as phosphorus (P) and arsenic (As) are ion-implanted using the gate electrode 137 as a mask to obtain a low concentration of about 10 ¹⁷ to 10 ¹⁹ cm ^-3 . An impurity diffusion region 138 is formed.

Thereafter, as shown in FIG. 109, a CVD film 139 made of an oxide film, a nitride film, and a polycrystalline silicon film is deposited on the gate insulating film 136 and the gate electrode 137. As shown in FIG.

As shown in FIG. 110, the spacer 140 is formed on the sidewall of the gate electrode 137 by anisotropic etching.

Then, the second to 111 also ion-implanted with an n-type impurity, such as phosphorus (P), arsenic (As) for the spacer 140 to the p-type semiconductor substrate 130 using a mask, as shown in, 10 ¹⁷ A high concentration impurity region 141 having a concentration of ˜10 ¹⁹ cm ⁻³ is formed.

Thereafter, as shown in FIG. 112, an interlayer insulating film 142 formed of an oxide film PSG film, a BPSG film, or their multilayer film is formed by the CVD method. Thereafter, as shown in FIG. 113, the contact hole 143 is formed in a desired place of the interlayer insulating film 142 using a known photolithography technique and an etching technique.

Subsequently, as shown in FIG. 114, the wiring material is deposited on the p-type semiconductor substrate 130 and the interlayer insulating film 142 by sputtering, CVD, or the like. The wiring layer 144 is formed by patterning this wiring material using a.

Thereafter, a protective film (not shown) such as a nitride film, an oxide film, or the like is formed on the wiring layer 144 by the CVD method, thereby completing a NOR mask ROM.

As described above, in the case of the NAND type mask ROM and the NOR type mask ROM, the channel cut injection layer 132 of the deflection injection layer 105 is formed before the gate insulating films 106 and 136 are formed. (I.e., writing ROM data), the process from determining the ROM contents to completing the mask ROM is very long.

Therefore, the process period from shipping the ROM data to receiving the customer from the customer is long, making QTAT (Quick Turn Around Time) difficult. Hereinafter, the proposed method for realizing the above QTAT will be described below, divided into the case of the NAND type mask ROM and the case of the NOR type mask ROM.

First, the case of a NAND type mask ROM is demonstrated.

As a technique for realizing the above-mentioned QTAT, the invention disclosed in Japanese Patent Laid-Open No. 58-70567 (1983) can be exemplified. The invention disclosed in Japanese Patent Application Laid-Open No. 58-70567, after forming an impurity region and a gate electrode, forms a resist pattern to expose the gate electrode of a desired transistor, and uses the resist pattern as a mask to penetrate the gate electrode. Inject

As a result, impurities are introduced into the channel region of the desired transistor.

Applying the invention disclosed in Japanese Patent Application Laid-Open No. 58-70567 to the conventional example, the n-type impurity ions are implanted with high energy to penetrate the gate electrode 107 after the formation of the high concentration impurity region 111 shown in FIG. The deflection injection layer 105 is formed.

As a result, the process up to the formation of the high concentration impurity region 111 is performed before the ROM data from the customer is written. Thus, QTAT can be achieved as compared with the conventional example.

However, in the above method, it is necessary to implant the impurity ions into the channel region through the gate electrode 107 and the gate insulating film 106.

In other words, impurities must be implanted with high energy.

In particular, in the case of a NAND type mask ROM, it is necessary to change the desired transistor to a deflection type. For this purpose, heavy elements such as phosphorus (P) and arsenic (As) must be injected.

As a result, by injecting relatively light elements such as boron B, higher energy is required as compared to the NOR type mask ROM for recording ROM data.

For example, using a polycrystalline silicon film having a thickness of about 300 m as the gate electrode 107 material, an implantation energy of about 300 to 500 KeV is required to inject phosphorus (P) ions through the gate electrode 107. Do.

Further, in view of the high speed operation of the semiconductor device, when the high melting point metal silicide is employed as the gate electrode 107 material in order to resist the gate electrode 107, ions are more difficult to penetrate the gate electrode 107.

For example, using a multilayer film of about 200 mm thick tungsten silicide and about 200 mm thick polycrystalline silicon as the gate electrode 107 material, the phosphorus (P) ion is implanted to penetrate the gate electrode 107. In order to inject the phosphorus (P) ions with a high energy of 500KeV or more.

In addition, in order to deflate the submicron-level transistor sufficiently deeply, an ion implantation amount of 10 ¹³ cm ^-3 or more is usually required.

In the ion implantation apparatus currently used for general semiconductor devices, it is difficult to perform such high energy ion implantation with high processing capability.

For this reason, especially in order to record ROM data, it is necessary to use the high energy ion implantation apparatus which can ion-inject with high energy of 500 KeV-MeV level.

However, such an ion implantation apparatus is more expensive than a conventional ion implantation apparatus and has a larger device size.

In addition, the resist used as a mask at the time of ion implantation needs to have a certain film thickness in order to fully function as a mask at the time of high energy ion implantation.

For example, in the case of high energy ion implantation of 500 KeV or more, the film thickness of the resist needs to be 2 μm or more.

However, in the miniaturization of semiconductor devices, in order to form a fine resist pattern, it is disadvantageous to increase the thickness of the resist film.

In other words, from the viewpoint of miniaturization of the semiconductor device, it can be said that it is disadvantageous to increase the thickness of the resist film, that is, to perform high energy ion implantation in this case.

In addition, by ion implantation at high energy, the thickness of the gate electrode 107 cannot be lowered.

For example, when phosphorus (P) ions are injected into silicon at 500 KeV energy, phosphorus ions reach a depth of about 0.62 µm on average, but the lateral expansion at this time becomes about 0.2 µm with standard deviation σ. .

Considering the distribution up to 3σ, the enlargement in the horizontal direction reaches up to 0.6 µm. As a result, in the case of a semiconductor device having a sub-micron degree, interference with adjacent memory elements cannot be ignored, which can be said to be a factor that hinders miniaturization.

Next, how the enlargement of the transverse direction of the implanted ions interferes with the adjacent memory elements will be described with reference to Figs. 115 (a) and (b).

115A shows the degree to which the resist pattern 116 is formed after the high concentration impurity region 111 is formed, and the gate electrode 107 can penetrate the channel region of a desired transistor in the conventional example described above. By the high energy ion implantation, the horizontal expansion of the deflection injection layer 105a becomes large.

In addition, as shown by 105b in the figure, it may be considered that the deflection injection layer 105a is expanded to the channel region of the adjacent transistor. This causes a problem that the execution channel length t of adjacent transistors is reduced.

115 (a) shows a cross section orthogonal to 115 (a).

As shown in FIG. 115 (b), since the enlargement of the deflection injection layer 105a in the horizontal direction is large, the end of the deflection injection layer 105a is enlarged to the bottom of the element isolation oxide film 103 to separate the field. There is also a problem that leakage current occurs between them.

It is considered that interference with adjacent elements can not be ignored by high energy ion implantation as described above.

Next, a case of the ROM type mask ROM will be described.

As in the case of the NAND mask ROM described above, in the case of the NOR type mask ROM, p-type impurities are implanted with high energy to penetrate the gate electrode 137 after the formation of the high concentration impurity region 141 to achieve QTAT. It is also possible to form the channel cut injection layer 132.

In this case, ion implantation must be performed to penetrate through the gate electrode 137, and ion implantation must be performed at high energy.

However, since boron (B), which is a light element, is frequently used as the p-type impurity, it is possible to penetrate the gate electrode 137, which is well used as the n-type impurity. However, even in this case, for example, when a polycrystalline silicon film having a thickness of about 300 mm is used as the gate electrode material, an injection energy of about 150 KeV is required.

In order to reduce the resistance of the gate electrode 137, when a multilayer film of a tungsten silicide having a thickness of about 200 mm and a polycrystalline silicon film having a thickness of about 200 mm is used as the gate electrode 137 material, about 250 to 400 KeV is injected. Energy is needed.

As mentioned above, the ion implantation apparatus generally used for semiconductor manufacture has many specifications which inject | pour in 200KeV or less.

In this case, the implantation energy required is lower than that of the NAND-type mask ROM, and a special specification device is required, and the ion implantation device is expensive and the device size is large.

In this case, the implantation energy may be lower than in the case of the NAND mask ROM described above. However, since boron (B), which is the implantation ion, is a lighter element such as phosphorus (P), the implantation ion range in the resist film is different from that of the NAND mask ROM. Almost the same.

This causes a problem that the thickness of the resist film must be thick, which is disadvantageous for miniaturization.

In addition, the implantation energy at the time of injecting through the gate electrode is lower than that in the case of the NAND mask ROM, but in the above-described case, the lateral expansion of the implantation ions is about the same as in the case of the NAND mask ROM.

As a result, in miniaturization of the semiconductor device, interference between adjacent transistors cannot be ignored, which becomes a factor that hinders miniaturization.

FIG. 116 shows that after forming the high concentration impurity region 141, a resist pattern 146 is formed to expose the gate electrode 137 of a desired transistor, and the p-type impurity such as boron (B) is buffered in the gate electrode 137. In the case where ion implantation is performed with high energy, the channel cut injection layer 132a is formed.

As shown in FIG. 116, since the boron B is implanted with high energy, it is conceivable that the implanted ions expand in the lateral direction and expand to the channel region of the adjacent transistor.

As a result, in this case, the threshold voltage Vth of adjacent transistors changes, causing a problem that causes malfunctions when reading data.

SUMMARY OF THE INVENTION An object of the present invention for solving the above problems is to provide a method for manufacturing a mask ROM semiconductor device and a mask ROM semiconductor device capable of shortening the delivery time without degrading the performance of a transistor in the mask ROM semiconductor device.

Another object of the present invention is to provide a mask ROM semiconductor device manufacturing method and a mask ROM semiconductor device capable of recording ROM data with low energy and shortening the delivery time.

Still another object of the present invention is to provide a mask ROM semiconductor device manufacturing method and a mask ROM semiconductor device which can cope with miniaturization and can shorten delivery time.

Still another object of the present invention is to provide a method for manufacturing a mask ROM semiconductor device and a mask ROM semiconductor device capable of shortening the delivery time while recording ROM data without using a special device to reduce manufacturing costs.

Each mask ROM semiconductor device according to an aspect of the present invention includes a second transistor having a relatively high threshold voltage connected to the first transistor in series with a first transistor having a relatively low threshold voltage.

In the mask ROM semiconductor device according to an aspect of the present invention, a first impurity of the second conductive type is spaced so as to form a channel region of the first and second transistors on a main surface of a semiconductor substrate of the first conductivity type having a main surface. A region, a shared impurity region and a second impurity region are formed.

In addition, a first gate electrode is formed on the first channel region disposed between the first impurity region and the shared impurity region, and the second channel region is disposed between the second impurity region and the shared impurity region. The second gate electrode is formed over the insulating film.

The first channel impurity region of the second conductivity type is formed in the first channel region such that the first impurity region and the shared impurity region are in contact with each other.

Further, a first channel cut impurity region of the first conductivity type is formed in the second channel region adjacent to the second impurity region to control the magnitude of the threshold voltage of the second transistor.

Further, a second channel cut impurity region of the first conductivity type is formed in the second channel region adjacent to the common impurity region. In the second channel region, a second channel impurity region of the second conductivity type is disposed between the first impurity region and the second channel cut impurity region to control the magnitude of the threshold voltage of the second transistor.

In the mask ROM semiconductor device according to this aspect, first and second channel cut impurity regions are formed at both ends of the second channel region of the second transistor.

The second channel impurity region of the second conductivity type is formed in the second channel region except for the first and second channel cut impurity regions.

The first channel impurity region of the second conductivity type is formed in the channel region of the first transistor.

This results in the deflection state of the first transistor. Meanwhile, the first and second channel cut impurity regions of the first conductive type are formed at both ends of the second channel region of the second transistor. Therefore, the threshold voltage of the second transistor can be increased above the threshold voltage of the first transistor.

In the method for manufacturing a mask ROM semiconductor device according to one aspect of the present invention, first and second gate electrodes of the first and second transistors are first formed on a main surface of a semiconductor substrate of the first conductive type via a gate insulating film.

The first impurity region, the shared impurity region, and the second impurity region of the second conductive type are respectively formed on the main surface of the semiconductor substrate to form the source and drain regions of the first and second transistors.

A sidewall insulating film is formed on the side of the first gate electrode.

An impurity is implanted into the second impurity region and the shared impurity region to control the magnitude of the threshold voltage of the second transistor using the first gate electrode, the second gate electrode, and the sidewall insulating layer as a mask.

In the method for manufacturing a mask ROM semiconductor device according to this aspect of the present invention, sidewalls are formed on the side of the first gate electrode.

Impurities that control the threshold voltage of the second transistor are ion implanted into the second impurity region and the common impurity region using the first gate electrode, the second gate electrode, and the sidewall insulating film as a mask.

In this operation, the introduction of impurities is performed with relatively low energy using a sidewall insulating film formed on the sidewall of the first gate electrode as a mask. Therefore, one end of the impurity region formed by the introduction of the impurity does not reach the channel region under the first gate electrode. On the other hand, the sidewall insulating film is not formed on the side of the second gate electrode.

Therefore, the end portion of the impurity region extends to the channel region under the second gate electrode. Also in this operation, impurities are introduced through the second impurity region and the common impurity region. Therefore, the ion implantation energy may be relatively low.

As such, the side diffusion of the impurity region is suppressed after the ion implantation, and thus adversely affecting the adjacent transistors can be effectively prevented.

In the method of manufacturing a mask ROM semiconductor device according to another aspect of the present invention, first and second gate electrodes of the first and second transistors having a gate insulating film are formed on the main surface of the semiconductor substrate of the first conductive type. .

The first impurity region, the shared impurity region, and the second impurity region of the second conductive type, which are the source and drain regions of the first and second transistors, are formed on the main surface of the semiconductor substrate.

And forming a resist pattern covering the first gate electrode and exposing the second gate electrode, and using the resist pattern and the second gate electrode as a mask, the threshold of the second transistor in the second impurity region and the shared impurity region. Ions are implanted with impurities to control the magnitude of the voltage.

After the ion implantation, diffusion is performed to diffuse the impurity introduced so that the ends of the pair of control impurity regions formed by impurity implantation to control the magnitude of the threshold voltage of the second transistor overlap at a position under the second gate electrode. Take care.

In the method of manufacturing a mask ROM semiconductor device according to this aspect of the present invention, a resist pattern covering the first gate electrode and exposing the second gate electrode is formed, and the second impurity region is formed using the second transistor pattern and the second gate electrode. Ions are implanted into the common impurity region.

Subsequently, the end portions of the pair of control impurity regions formed by ion implantation are diffused so as to overlap each other at a position under the second gate electrode.

As a result, when the impurity of the second conductivity type is introduced, the threshold voltage of the second transistor can be adjusted to be lower than the threshold voltage of the first transistor.

In addition, when the impurity of the first conductivity type is introduced, the threshold voltage of the second transistor may be adjusted to be higher than the threshold voltage of the first transistor.

In this manner, a denter is recorded in the mask ROM. Since impurities are ion implanted using the resist pattern and the second gate electrode as a mask, the implantation energy can be lowered.

Accordingly, since the impurity region does not extend to the channel region of the adjacent transistor, it is possible to prevent the adverse effect on the adjacent transistor that may be caused by the impurity region formed by the implantation of the impurity.

In the method for manufacturing a mask ROM semiconductor device according to another aspect of the present invention, an impurity layer of the second conductive type is formed in a region where a first transistor and a second transistor are to be formed on the main surface of the semiconductor substrate of the first conductive type.

The first impurity region, the shared impurity region, and the first conductive region are defined on the main surface of the semiconductor substrate of the first conductive type by the gate insulating film to define channel regions of the first and second transistors and form source and drain regions. To form an impurity region.

A sidewall insulating film is formed on the side of the first gate electrode.

The first conductive electrode, the second gate electrode, and the sidewall insulating layer are used as masks, and impurities of the first conductive type for controlling the magnitude of the threshold voltage of the second transistor are formed in the second impurity region and the shared impurity region. Ion implant.

In the method of manufacturing a semiconductor device according to this aspect of the present invention, an impurity layer of the second conductivity type is formed before the channel regions of the first and second transistors.

A first impurity region, a common impurity region, and a second impurity region of the second conductive type, which form the source and drain regions of the first and second transistors, are formed.

A sidewall insulating film is formed on the side of the first gate electrode of the first transistor, and the first conductive impurity is implanted into the second impurity region and the common impurity region using the second gate electrode and the sidewall insulating film as a mask.

Since the sidewall insulating layer is not formed on the sidewall of the second gate electrode, the first conductive type impurity region may be formed at least at both ends of the channel region of the second transistor.

Thus, the first and second channel cut impurity regions are formed.

This makes it possible to make the threshold voltage of the second transistor higher than the threshold voltage of the first transistor.

This writes data to the mask ROM.

Since the impurity of the first conductivity type is implanted into the second impurity region and the common impurity region, ion implantation may be performed with relatively low energy.

As a result, the expansion of the impurity region caused by the implanted impurities can be suppressed, and adverse effects on adjacent transistors, which may occur due to the writing of ROM data, can be effectively prevented.

In a method of manufacturing a mask ROM semiconductor device according to still another aspect of the present invention, an impurity layer of a second conductivity type is formed in a region where the first and second transistors are to be formed on a main surface of a semiconductor substrate of the first conductivity type. .

The first and second gate electrodes of the first and second transistors are formed on the main surface of the semiconductor substrate of the first conductive type via the gate insulating film. A first impurity region, a shared impurity region, and a second impurity region of the second conductivity type are formed on the main surface of the semiconductor substrate as source and drain regions of the first and second transistors.

And forming a resist pattern covering the first gate electrode and exposing the second gate electrode, and using the resist pattern and the second gate electrode as a mask, the threshold voltage of the second transistor in the second impurity region and the shared impurity region. Ions are implanted with impurities of the first conductivity type to control the size.

In the method for manufacturing a mask ROM semiconductor device according to this aspect of the present invention, a second conductive impurity layer is formed in the channel region of the first and second transistors and is formed of the source and drain regions of the first and second transistors. The first conductive impurity region, the covalent impurity region, and the second impurity region are formed.

A resist pattern is formed to cover the first gate electrode and expose the second gate electrode, and the first conductive type impurity is ionized in the second impurity region and the shared impurity region by using the resist pattern and the second gate electrode as a mask. Inject.

Thereby, it is possible to form the impurity region of the first conductivity type at least at both ends of the channel region of the second transistor.

This makes it possible to make the threshold voltage of the second transistor higher than the threshold voltage of the first transistor.

As a result, the data of the mask ROM is recorded in the second transistor.

In addition, since the impurity of the first conductivity type is ion implanted into the second impurity region and the shared impurity region, ion implantation with relatively low energy is possible.

It is thereby possible to effectively prevent adverse effects on adjacent transistors by ion implantation of the impurity.

The above and other objects, features, aspects and advantages of the present invention will become more apparent from the detailed description taken in conjunction with the accompanying drawings.

EXAMPLE

EMBODIMENT OF THE INVENTION Hereinafter, the Example of mask ROM which concerns on this invention is described using drawing.

In addition, since the top view of the Example demonstrated below is the same as the prior art example, the top view used by description of the prior art example is quoted for convenience.

In addition, the manufacturing method and the material of each part of the mask ROM are the same as in the prior art unless otherwise described.

First, an embodiment of a NAND type mask ROM will be described with reference to FIGS.

FIG. 1 shows a sectional view of the mask ROM in this embodiment, and corresponds to a sectional view along the line A-A of the mask ROM shown in FIG.

As shown in FIG. 1, the n-type low concentration impurity region 8 and the high concentration impurity region 11 are formed on the main surface of the p-type semiconductor substrate 1 at predetermined intervals.

Gate electrodes 7, 7a, 7b, and 7c are formed on the channel region defined by these impurity regions through the gate insulating film 6.

In this case, a pair of n-type punch-through injection layers 60 are formed in the channel region under the gate electrode 7a and the gate electrode 7b.

One end of the punch-through injection layer 60 overlaps the channel region under the gate electrode 7a and the gate electrode 7b. As a result, the threshold voltage Vth of the transistor having the gate electrode 7a and the gate electrode 7b (hereinafter referred to as a metal insulator silicon field effect transistor in the description of the embodiment) is relatively low (in this case, almost ground potential). It is possible to

As a result, the data of the mask ROM is recorded.

On the other hand, as shown in FIG. 1, the other end of the punch-through injection layer 60 includes a MISFET (for example, a MISFET including the gate electrode 7a) in which ROM data is written and a MISFET in which ROM data is not written. For example, focusing on the relationship with the MISFET including the gate electrode 7c, in the MISFET in which data is not written, the end is located at the gate electrode 7a side rather than the end of the low concentration impurity region 8. have.

That is, the punch-through injection layer 60 is not formed in the channel region of the MISFET in which the ROM data is not recorded.

Thereby, when writing ROM data, it does not adversely affect the adjacent MISFET.

A spacer 10 is formed on the sidewall of the gate electrode 7 of the MISFET in which ROM data is not written.

Due to the presence of this spacer 10, the end of the punch-through injection layer 60 is not formed to extend to the channel region of the MISFET in which ROM data is not written.

At this time, as shown in FIG. 1, an n-type impurity layer 60b formed at the time of forming the punch-through injection layer 60 is formed in the source / drain region of the MISFET in which ROM data is not recorded.

The n-type impurity layer 60b suppresses the electric field relaxation effect due to the LDD structure, and works advantageously for high speed sensing of the mask ROM.

The necessity of this LDD structure will be described later.

An interlayer insulating film 12 is formed on the p-type semiconductor substrate 1, the gate electrode 7, and the spacer 10, and a contact hole 13 is formed in the predetermined region of the interlayer insulating film 12.

A wiring layer 14 is formed on the interlayer insulating film 12, and the wiring layer 14 is formed through the contact hole 13 in the low concentration impurity region 8 and the high concentration impurity formed on the main surface of the p-type semiconductor substrate 1. It is connected to the area 11.

A protective film 15 is formed on the wiring layer 14.

FIG. 2 shows a sectional view of the mask ROM according to the present embodiment, and shows a cross section orthogonal to the cross section shown in FIG.

The cross section shown in FIG. 2 corresponds to the cross section taken along the line B-B in FIG. As shown in FIG. 2, the element isolation oxide film 3 is formed on the main surface of the p-type semiconductor substrate 1 at predetermined intervals.

A gate insulating film 6 is formed on the surface of the p-type semiconductor substrate 1 between the device isolation oxide films 3.

Since the gate electrode 7 is formed on the gate insulating film 6 and the element isolation oxide film 3, the interlayer insulating film 12 is formed on the gate electrode 7.

The wiring layer 14 patterned on the interlayer insulating film 12 is formed at intervals, and the protective film 15 is formed on the wiring layer 14.

The punch-through injection layer 60 is formed in a predetermined channel region of the channel region defined by the element isolation oxide film 3 on the main surface of the p-type semiconductor substrate 1.

In this case, the end portion of the punch-through injection layer 60 is formed under the device isolation oxide film 3 so that the inclination is not so rapid.

This greatly depends on the ion implantation energy of the impurity in forming the punch-through injection layer 60, which will be described in detail in the following description of the manufacturing method. Thereby, the generation of the leakage current between the field separations is remarkably suppressed. The punch-through injection layer 60 is formed by introducing a high concentration of n-type impurities such as phosphorus (P) and arsenic (As).

In this case, the concentration of the punch-through injection layer 60 is about 10 ^{18 -10 21} cm ^-3 .

As described above, one end of the punch-through injection layer 60 is formed so as to overlap in the channel region of the MISFET in which the ROM data is recorded. As a result, the source region, which is the n-type impurity region, and the drain region, which is the n-type impurity region, of the MISFET on which the ROM data is recorded are connected as described above.

As a result, the source / drain is brought into a conductive state.

In other words, the MISFET is always in a conductive state by the punch-through injection layer 60.

As a result, the punch-through injection layer 60 can be formed or not, making it easy to separate the MISFET from the conduction state or not.

3 and 4, the concentration distribution of the channel region and impurity region of the MISFET in which ROM data is recorded will be described. FIG. 3A is an enlarged cross-sectional view of the MISFET in which ROM data is recorded, and FIG. 3B is a diagram showing impurity concentration distribution in the MISFET channel region and impurity region shown in FIG.

FIG. 4A shows a case where p-type impurities are used as impurities for recording ROM data, and correspond to FIG. 3A.

FIG. 4 (b) shows the concentration distribution of the channel region and the impurity region of the MISFET shown in FIG.

That is, the MISFET shown in FIG. 3 is a deflection type MISFET, and the MISFET shown in FIG. 4 is an enhancement type MISFET.

Referring to FIG. 3A, a pair of punchthrough injection layers 60 are formed to overlap in the channel region of the MISFET.

Since the punch-through injection layer 60 is formed of n-type impurities, the MISFET is in a conductive state.

For example, when an n-type impurity is introduced at about 5 x 10 ¹⁴ cm ^-2, the concentration of the n-type impurity in this channel region is about 10 ¹⁴ cm ^-3 as shown in FIG.

As shown in Fig. 4A, by introducing p-type impurities, a pair of p-type impurity regions 60a are formed in this channel region so as to overlap each other.

In this case, since the p-type impurity is introduced into the channel region of the MISFET, it is possible to increase the threshold voltage of the MISFET.

In other words, the introduction of the p-type impurity makes this MISFET an enhancement MISFET.

In this case, for example, when the p-type impurity is introduced about 10 ¹⁴ cm ⁻² , the p-type impurity concentration in the channel region of this MISFET is about 10 ⁷ cm ⁻³ , as shown in FIG.

Since the enhancement type MISFET is used in the NOR mask ROM described below, details thereof will be described in the description of the NOR mask ROM described below.

The operation of the NAND type mask ROM having the above-described structure is similar to that of the conventional NAND type mask ROM.

In other words, it is conceivable that the punch-through injection layer 60 is formed in the source / drain region of the MISFET with a diagonal line in FIG.

In addition, the operation | movement of the other Example demonstrated below is also abbreviate | omitted when it is the same as before.

Next, the manufacturing method of the said NAND type mask ROM is demonstrated using FIGS.

5 to 16 are cross-sectional views showing step 1 to 12 steps step by step in the manufacturing process of the NAND type mask ROM in the above embodiment, and showing a part of the cross-sectional view shown in FIG.

17 to 28 show cross-sections orthogonal to the cross-sectional views shown in FIGS. 5 to 16 in each manufacturing step, and show a part of the cross-section shown in FIG.

5 to 16 and 17 to 28 each show the same process in the manufacturing process of the above embodiment in order, and will be described with reference to both drawings in the following description. First, p-type impurities such as boron are introduced into a p-type semiconductor substrate by an ion implantation method and a thermal diffusion method to form a p well. In the peripheral circuit portion, n-type impurities such as phosphorus (P) are introduced to form n wells.

5 and 17, a stress buffer film 1a such as a thermal oxide film is formed on the p-type semiconductor substrate 1, and an oxide film 2 such as a nitride film by CVD is formed thereon. Form.

The oxidation resistant film 2 is then patterned using known photolithography and etching techniques to expose the device isolation region. Then, the oxidation resistant film 2 is thermally oxidized to form a device isolation oxide film 3 in the device isolation region.

Next, referring to FIGS. 6 and 18, the oxide film 2 is removed, and if necessary, ion implantation or the like is applied to portions corresponding to the channel regions of the p-type channel and the n-type MISFET of the memory cell array region or peripheral circuit. The p-type or n-type impurity is introduced by the method to adjust the threshold voltage of each MISFET.

Next, referring to FIGS. 7 and 19, the stress buffer film 1d is removed, and the gate insulating film 6 is formed by thermal oxidation or the like.

The gate electrode 7 is formed by depositing a gate electrode material on the gate insulating film 6 by using a CVD method, a sputtering method, or the like, and patterning the gate electrode.

Next, as shown in FIGS. 8 and 20, n-type impurity ions such as phosphorus (P) and arsenic (As) are implanted using the gate electrode 7 as a mask, thereby providing 10 ¹⁷ to 10 ¹⁹ cm- ^. The low concentration impurity region 8 having a concentration of about ³ is formed in a self-aligning manner.

9 and 21, a CVD film 9 such as an oxide film, a nitride film, and a polycrystalline silicon film is formed on the gate insulating film 6 and the gate electrode 7 by the CVD method.

10 and 22, the spacer 10 is removed by anisotropic etching to remove the CVD film 9 from the flat portion, leaving the CVD film 9 on the side of the gate electrode 7. FIG. Form.

11 and 23, by implanting n-type impurities such as phosphorus (P) and arsenic (As) into the source / drain regions of the n-channel MISFET using the spacer 10 as a mask, A high concentration impurity region 11 having a concentration of about 10 ²⁰ to 10 ²² cm ^-3 is formed.

Next, referring to FIGS. 12 and 24, a resist pattern 16 is formed so as to expose the MISFET to which ROM data is to be written and to cover the MISFET to which ROM data is not to be written.

Using the resist pattern 16 as a mask, the spacer 10 formed on the side of the gate electrode 7 of the MISFET to which the ROM data should be written is etched away.

At this time, for example, when the spacer 10 is an oxide film formed by the CVD method, the spacer 10 is removed by a fluorine-based etching solution or by dry etching using a CHF ₃ -based etching gas or the like.

Next, referring to FIGS. 13 and 25, the resist pattern 16 is removed to form n-types of phosphorus (P) and arsenic (As) using the gate electrode 7 and the spacer 10 as masks. Impurity ions are implanted at an implantation amount of about 10 ¹⁴ to 10 ¹⁷ cm ^-2 .

And by performing heat treatment in a subsequent process, the punch-through injection layer 60 is formed.

At this time, an n-type impurity layer 60b is formed in the source / drain region of the MISFET in which ROM data is not recorded.

By the impurity layer 60b, it is possible to suppress the electric field relaxation effect by the LDD structure as described above.

To punch-through between the source / drain regions of the MISFET in which ROM data is recorded, the source region and the drain region of the source region and the drain region are formed by expanding the impurity region by ion implantation as described above and spreading the impurities by heat treatment in a subsequent process. It is necessary to conduct the n-type impurity region.

For example, it is assumed that when the gate electrode 7 has a width of 0.7 µm, phosphorus (P) ions are implanted at an energy of 200 KeV, and a heat treatment corresponding to 900 ° C. for 3 hours is performed in a subsequent process.

In this case, the diffusion length L can be represented by the following equation (1).

Using the diffusion coefficient 7.8E-16 cm 2 / s of phosphorus (P) at 900 ° C. in the formula (1), the diffusion length L is about 0.06 μm.

Therefore, in order to connect the distance between the source and the drain of 0.7 mu m, it is necessary that both of the impurity regions formed by ion implantation have a transverse diffusion of 0.29 mu m.

And the projection is a non-integer R _P 0.2539㎛ when injected into the silicon (P) to 200KeV, and swing ΔR _P of the projection range is 0.775㎛, lateral swing is ΔR _P is 0.1010㎛.

And when and the depth direction distribution of the injection followed a simple Gaussian distribution, phosphorus (P) concentration n (R _P) in the depth R _P is represented by the formula (2). In addition, the phosphorus (P) concentration n (R _P , X) of the depth R _P of the portion entered by the distance X at the end of the injection mask is represented by the formula (3).

In order to pass the p-type impurity concentration (approximately 10 ¹⁷ cm ⁻³ ) to the substrate at a place 0.29 μm away from the mask stage according to the above formulas (2) and (3), the injection amount ψ is 1 × 10 ¹⁵ cm ⁻² or more You need to.

This is the injection energy and injection amount which can be practically treated with a conventional intermediate current injection device.

In the evaluation by the experiment, the low injection amount was 1 × 10 ¹⁴ to 2 × 10 ¹⁴ cm ⁻² , and the current between the source and the drain flowed.

This is because channeling at the time of ion implantation, diffusion of implantation ions by knock-on of impurity ions previously implanted by implantation ions, dependency diffusion by high concentration of impurity concentration, tail of impurity distribution It is considered that the diffusion in the lateral direction of the impurity region becomes larger than the calculated value due to negative contribution or the like.

Then, as shown in Figs. 14 and 26, an interlayer formed by an oxide film, a BPSG film, or a multilayer film thereof using the CVD method on the p-type semiconductor substrate 1, the gate electrode 7, and the spacer 10. The insulating film 12 is formed, and as shown in FIGS. 15 and 27, the contact hole 13 is formed using the known photolithography technique and etching technique of the desired location of the interlayer insulating film 12. do.

Then, as shown in FIGS. 16 and 28, a wiring material is deposited on the interlayer insulating film 12 by CVD or the like and patterned by using photolithography and etching techniques, thereby forming a wiring layer made of aluminum alloy or the like. (14) is formed.

By forming a protective film 15 such as a nitride film, an oxide film or the like on the wiring layer 14 by the CVD method, the mask ROM shown in FIGS. 1 and 2 is completed.

According to the above-described manufacturing method of the mask ROM, QTAT can be achieved as compared with the manufacturing method of forming the deflection injection layer 105 before the conventional gate insulating film 106 is formed.

This is because the process up to the formation of the highly-concentrated impurity region 11 in the source / drain region, which is a process after the gate insulating film 6 is formed before writing ROM data from the customer, can be completed.

Compared to the manufacturing method of forming the deflection injection layer 5 by ion implanting impurities with high energy to penetrate the gate electrode, it is about the same in terms of QTAT, but performing relatively low energy recording of ROM data of 200KeV or less. It is possible.

This is advantageous in terms of cost because a conventional ion implantation apparatus can be used without using a special high energy ion implantation apparatus which is expensive and has a large device size.

In addition, since the implantation energy is low, the transverse diffusion of implantation ions in the semiconductor substrate is also relatively small. This makes it possible to effectively prevent adverse effects on adjacent MISFETs by writing ROM data.

In the above embodiment, the MISFET included in the mask ROM has an LDD structure.

This LDD structure is provided for suppressing hot carrier generation in the vicinity of the drain region of the transistor, thereby alleviating the electric field in the portion and improving the reliability of the transistor.

Therefore, the LDD structure is an essential element in a transistor to which a high voltage such as a peripheral circuit is applied.

In the above embodiment, however, the MISFET of the memory section also has an LDD structure.

This is because the MISFETs in the memory section are also formed at the same time in manufacturing the MISFETs in the peripheral circuit.

This makes it possible to reduce the number of manufacturing processes in the memory section compared with the case where the source / drain regions of the MISFET are manufactured separately from the peripheral circuit.

The reason why the field relaxation effect is not so necessary in the memory section is that the memory cell current flowing from the peripheral circuit to the transistor in the memory section is generally relatively small when reading data.

However, for high speed sensing, it is necessary to increase the memory cell current. To do so, it is necessary to raise the voltage applied to the transistor in the memory section.

In this case, it is necessary to consider the hot carrier effect.

In view of the above, in the above-described embodiment, when the ROM data is written, n-type impurities are introduced using the gate electrode 7 and the spacer 10 as a mask, so that even in the impurity region of the transistor in which the ROM data is not written. As the n-type impurity is introduced, the decrease in the memory cell current due to the parasitic resistance of the low concentration impurity region in the LDD structure is greatly reduced.

Thereby, a mask ROM corresponding to high speed sensing can be obtained. In the above embodiment, the spacer pattern 10 is removed using the resist pattern 16 as a mask, and then the resist pattern 16 is removed, and then the ROM data using the gate electrode 7 and the spacer 10 as a mask. Recorded.

However, as shown in FIG. 29, after the spacer 10 is removed using the resist pattern 16 as a mask, the resist pattern 16 is subsequently used as a mask to write ROM data. Ion implantation of (P) and arsenic (As) may be performed.

As a result, the memory current of the MISFET cannot be increased in the memory section, but other effects are the same as in the above embodiment.

Next, another Example based on this invention is described using FIGS. 30-38. FIG. 30 is a sectional view of the NAND type mask ROM in this embodiment, showing a cross section corresponding to the cross section shown in FIG. Referring to FIG. 30, in the mask ROM according to the present embodiment, a punch-through injection layer 60 is formed in the channel region of the MISFET in which the ROM data is to be written as in the above-described embodiment.

In the present embodiment, spacers 10 are formed on sidewalls of the gate electrode 7a and the gate electrode 7b of the MISFET in which the ROM data is written, and the impurity layer is formed in the source / drain region of the MISFET in which the ROM data is not written. 60b is not formed.

The other structure is the same as the above-mentioned embodiment, and the description about a structure is abbreviate | omitted.

In this way, the spacer 10 is also formed on the sidewalls of the gate electrode 7a and the gate electrode 7b of the MISFET in which the ROM data is written, so that when used in a microcode of a microprocessor or the like, the recording data is obtained from a planar cross-sectional structure. Since it is impossible to observe, there is an advantage to obtain a security effect.

The operation of this embodiment is almost the same as the above-described embodiment, and thus description thereof is omitted.

Next, the manufacturing method of the mask ROM in the present embodiment will be described with reference to FIGS. 31 to 38. FIG.

31 to 38 are cross-sectional views sequentially showing the first to eighth steps of the manufacturing process of the mask ROM in this embodiment, and a cross-sectional view showing a part of the cross section shown in FIG.

In addition, in each Example described later, the description is abbreviate | omitted about the thing of the same content as the said Example for convenience of description.

Therefore, in this case, for example, in the manufacturing method of the above-described embodiment, the first to fourth steps correspond to the first step in the present embodiment.

In addition, the cross section orthogonal to FIG. 30 is abbreviate | omitted for convenience of description.

Referring to FIG. 31, the gate electrode 7 is formed on the p-type semiconductor substrate 1 through the gate insulating film 6 through the same process as the above-described embodiment.

Using the gate electrode 7 as a mask, ion implantation of n-type impurities such as phosphorus (P) and arsenic (As) forms a low concentration impurity region 8 in a self-aligned manner.

As shown in FIG. 32, a resist pattern 17 is formed to expose the MISFET on which ROM data is written, and n, such as phosphorus (P), arsenic (As), etc. is used by using the resist pattern 17 as a mask. The punch-through injection layer 60 is formed by ion implantation of the type impurity.

In this case, the concentration of the punch-through injection layer 60 and the ion implantation amount of the n-type impurity are the same as in the above-described embodiment.

Then, as shown in FIG. 33, the CVD film 9 is formed on the gate insulating film 6 and the gate electrode 7 by the CVD method.

Thereafter, as shown in FIG. 34, the spacer 10 is formed by performing anisotropic etching to leave the CVD film 9 on the sidewall of the gate electrode 7.

As shown in FIG. 35, the high concentration impurity region 11 is formed using the spacer 10 as a mask, and as shown in FIG. 36, on the gate electrode 7 and the spacer 10. As shown in FIG. The interlayer insulating film 12 is formed.

As shown in FIG. 37, a contact hole 13 is formed in a desired region of the interlayer insulating film 12, and then in the interlayer insulating film 12 and the contact hole 13, as shown in FIG. The wiring layer 14 is formed.

Thereafter, a protective film (not shown) is formed on the wiring layer 14 to complete the mask ROM. According to the above manufacturing method, since the punch-through injection layer 60 is formed before the formation of the spacer 10, the effect of QTAT reduction can be reduced as compared with the manufacturing method shown in the above-described embodiment.

However, when ROM data is recorded, ROM data is recorded by ion implantation of relatively low energy of 200 KeV or less, and the same effect as the above-described embodiment is expected.

In addition, since the punch-spo injection layer 60 is formed before the spacer 10 is formed, the etching process for removing the spacer 10 can be omitted compared to the manufacturing method of the above-described embodiment.

In the case where the spacer 10 is removed by wet etching, portions of the separation oxide film and the like which are not the etching target may be removed due to the penetration of the etchant.

In addition, when the removal of the spacer 10 is finally performed using etching, the possibility of inflicting etching damage on the p-type semiconductor substrate 1 is also considered.

However, in the manufacturing process of the present embodiment, there is no removing step of the spacer 10, so the above problem does not occur.

In this respect, it can be said that the mask ROM manufactured by this embodiment is superior in reliability than the above embodiment.

Next, another embodiment of the mask ROM according to the present description will be described with reference to FIGS. 39 to 49. FIG.

The mask ROM of this embodiment assumes a NAND type mask ROM.

Therefore, ROM data is recorded by forming a deflection type MISFET and making other MISFETs an enhancement type MISFET.

In this case, all MISFETs are set in advance as deflection MISFETs, and ion implantation for recording ROM data is performed. Therefore, MISFETs other than the desired MISFETs are enhanced MISFETs.

As a result, a deflection type MISFET is formed by writing ROM data.

Hereinafter, the present embodiment will be described in detail with reference to FIGS. 39 to 49. FIG.

FIG. 39 shows a sectional view of the NAND type mask ROM in this embodiment, and is a sectional view corresponding to the sectional view shown in FIG.

As shown in FIG. 39, n-type low concentration impurity regions 28 and high concentration impurity regions 31 are formed on the main surfaces of the p-type semiconductor substrate 10 at intervals, respectively.

In addition, an n-type impurity layer 36 is formed in the channel region of each MISFET. The concentration of the n-type impurity layer 36 is about 10 ¹⁶ to 10 ¹⁷ cm ^-3 .

The gate electrode 27 is formed in the channel region via the gate insulating film 26.

If the desired MISFET is a MISFET in which ROM data is written, the impurity introduction layer 61 is formed so as to extend to the channel region of the MISFET except for the MISFET including the gate electrode 27a and the gate electrode 27b.

The impurity introduction layer 61 is an impurity formed at a concentration of 10 ¹⁵ to 10 ¹⁹ cm ^-3 in which p-type impurity ions such as boron (B) are implanted.

The impurity introduction layer 61 makes the impurity concentration in the channel region of the MISFET other than the desired MISFET uneven.

As a result, the desired MISFET is a deflection type MISFET, and the other MISFET is an enhancement type MISFET.

In this case, in the deflection type MISFET, spacers are formed on the side surfaces of the gate electrode 27a and the gate electrode 27b.

One end of the impurity introduction layer 61 is formed by this spacer 30 without extending to the desired MISFET channel region.

An interlayer insulating film 32 is formed on the gate electrode 27 and the spacer 30.

A wiring layer 34 is formed on this interlayer insulating film 32.

The wiring layer 34 is connected to the low concentration impurity region 28 and the high concentration impurity region 31 through the contact hole 33 provided at the predetermined position of the interlayer insulating film 32.

A protective film 35 is formed on the wiring layer 34.

In the mask ROM, impurity concentration distribution in the channel region is irregular in MISFETs other than the desired MISFET.

Thereby, the fall of the carrier movement speed in the center part of a channel area can be suppressed, and the performance of the whole MISFET can be improved.

Hereinafter, the concentration distribution of the impurity region and the channel region of the MISFET having the irregular channel region will be described in more detail with reference to FIG. 40.

40A is an enlarged view of the MISFET having an irregular channel region in FIG. FIG. 40 (b) shows the concentration distribution of the impurity region shown in FIG. 40 (a).

Referring to these drawings, in the channel region of the MISFET in which the impurity introduction layer 61 is formed, p-type impurity layer 61a formed by the impurity introduction layer 61 is formed at both ends thereof, and this p-type impurity layer 61a is formed. The n-type impurity region 36 is formed so as to be interposed therebetween.

As a result, the impurity concentration distribution in the channel region is irregular.

In this case, the concentration of the p-type impurity layer 61a is 10 ¹⁷ to 10 ¹⁹ cm ^-3 , and the concentration of the n-type impurity layer 36 embedded in the p-type impurity 61 a is 10 ¹⁵ to 10 ¹⁹ cm ^{−. 3} or so.

The end of the impurity introduction layer 61 may be in the channel region of the MISFET (the MISFET in which ROM data is not written) to be enhanced, and the end of the pair of impurity introduction layer 61 is the channel region. It may be formed so as to overlap in the inside.

Since the operation of the NAND type mask ROM in this embodiment is the same as in the above-described embodiment, description thereof is omitted.

Next, the first to seventh steps of the method for manufacturing a mask ROM in the present embodiment will be described with reference to FIGS. 41 to 47. FIG.

41 to 47 are cross-sectional views each showing a part of the cross-sectional view shown in FIG.

Referring to FIG. 41, n wells are formed in the p well and the peripheral circuit portion as necessary in the p-type semiconductor substrate 20, and a device isolation oxide film (not shown) is thermally oxidized in the device isolation region.

Thereafter, the n-type impurity layer 36 is formed by ion implantation of n-type impurities in the element formation region between the element isolation oxide films beyond the stress buffer film 21a.

42, the gate insulating film 26, the gate electrode 27, the spacer 30, the low concentration impurity region 28 and the high concentration impurity region 31 are formed through the same process as the above-described embodiment.

As shown in FIG. 43, a resist pattern 38 is formed to remove the spacer 30 of the desired MISFET.

The desired spacer 30 is removed by etching using the resist pattern 38 as a mask.

Then, boron (B), p-type impurity ions, such as by using the after removing the resist pattern 38, the gate electrode 27 and spacers 30 as a mask as shown in 44 Fig. 10 ¹¹ ~ 10 ¹⁴ cm ^It is implanted at about ^-2 degree, and the impurity introduction layer 61 is formed.

At this time, the implantation energy can be made lower than in the case of introducing the n-type impurity described above.

In this case, energy of about 100 to 200 KeV is sufficient. As a result, one end of the impurity introduction layer 61 is formed to extend to the channel region of the MISFET having no spacer 30.

Next, as shown in FIG. 45, an interlayer insulating film 32 is formed on the gate electrode 27 and the spacer 30. Then, as shown in FIG. 46, the interlayer insulating film 32 is formed at a predetermined position. The contact hole 33 is formed.

As shown in FIG. 47, a wiring layer 34 is formed on the interlayer insulating film 32 and the contact hole 33, and a protective film 35 (not shown) is formed on the wiring layer 34. The mask ROM is completed.

According to the method of manufacturing the mask ROM of the above embodiment, the QTAT can be increased and the ROM data can be recorded with a relatively low implantation energy of 200KeV or less as compared with the conventional one, and the same effect as in the above-described embodiment can be achieved.

In the case where the peripheral circuit portion determines the threshold voltage Vth of the n-channel MISFET by introducing p-type impurities into the source / drain regions as in the ROM data writing in this embodiment, the threshold voltage Vth of the peripheral circuit portion It is possible to simultaneously determine and write ROM data.

It is thereby possible to reduce the number of processes as a whole.

Although the p-type impurity was ion-implanted using the gate electrode 27 and the spacer 30 as a mask in the above embodiment, an oblique rotation ion implantation method is also effective to easily introduce this p-type impurity into the channel region. .

FIG. 48 shows a situation in which p-type impurities are introduced by inclining rotation ion implantation using the gate electrode 27 and the spacer 30 as a mask.

If the injection angle in this case is inclined by θ with respect to the vertical as shown in Fig. 48, the value of θ is preferably in the range of 10 to 45 °.

This makes it possible to inject p-type impurities into the channel region of the desired MISFET more efficiently.

In the above embodiment, p-type impurities were ion implanted using the gate electrode 27 and the spacer 30 as a mask.

However, as shown in FIG. 49, in the desired MISFET, the resist pattern 38, which is a mask for removing the spacer 30, is left even after the spacer 30 is removed, and the resist pattern 38 is used as a mask. The p-type impurity may be implanted by the inclined rotation ion implantation.

In this case, there is a possibility that a shadow portion of the resist pattern 38 may be generated when the implantation of the p-type impurity is implanted using the resist pattern 38 as a mask, but the resist pattern 38 has a similar effect as described above.

Next, another embodiment of the mask ROM according to the present invention will be described with reference to Figs.

This embodiment is based on the same NAND mask ROM as the above embodiment.

50 is a sectional view of the mask ROM in the present embodiment and corresponds to the sectional view shown in FIG.

39 and 50, the structural difference between the embodiment shown in FIG. 39 and the present embodiment is based on the spacer 30 on the sidewall of the gate electrode 27 of the MISFET in which the impurity introduction layer 61 is formed. ) Is formed or not.

In the present embodiment, the spacer 30 is formed on the sidewall of the gate electrode 27 of the MISFET in which the impurity introduction layer 61 is formed.

Other structures are the same as those in the embodiment shown in FIG.

In this embodiment, the spacer 30 is also formed on the sidewalls of the gate electrode 27 of the MISFET in which the impurity introduction layer 61 is formed. Since it cannot be determined, a security effect is obtained.

Other effects are almost similar to the embodiment shown in FIG.

Next, a method of manufacturing a mask ROM in this embodiment will be described with reference to FIGS. 51 to 58. FIG.

51 to 58 are cross-sectional views showing the first to eighth steps in the manufacturing process of the mask ROM in this embodiment.

In addition, the sectional drawing shown in FIGS. 51-58 is a figure which shows a part of cross section of the Example shown in FIG.

Referring to FIG. 51, an n-type impurity layer 36 is formed on the main surface of the p-type semiconductor substrate 20 through the same process as the above-described embodiment, and then on the main surface of the p-type semiconductor substrate 20. After the n-type impurity layer 36 is formed, the gate electrode 27 is formed on the p-type semiconductor substrate 20 via the gate insulating film 26.

The low concentration impurity region 28 is formed on the main surface of the p-type semiconductor substrate 20 in a self-aligned manner with the gate electrode 27 as a mask.

Referring to FIG. 52, a resist pattern 39 is formed to expose a MISFET to be processed into a photolithography process for ROM data recording and to be an enhancement MISFET.

Then, using the resist pattern 39 as a mask, the impurity introduction layer 61 is formed by injecting p-type impurities such as boron (B) at an implantation amount of about 10 ¹¹ to 10 ¹⁴ cm ^-2 .

The ion implantation energy in this case may be a relatively low energy of 200KeV or less.

The effect obtained thereby is the same as in the above-described embodiment.

Subsequently, as shown in FIG. 53, after removing the resist pattern 39, the CVD film 29 is formed on the entire surface of the p-type semiconductor substrate 20, and as shown in FIG. 30 is formed.

Next, as shown in FIG. 55, the high concentration impurity region 31 is formed by ion implantation using the gate electrode 27 and the spacer 30 as a mask, and then the gate electrode 27 and the spacer 30 are formed. An interlayer insulating film 32 is formed to cover the gap.

As shown in FIG. 57, a contact hole 33 is formed at a predetermined position of the interlayer insulating film 32, and as shown in FIG. 58, the wiring layer 34 is formed on the interlayer insulating film 32 and the contact hole 33. As shown in FIG. ).

A protective film (not shown) is then formed on the wiring layer 34 to complete the mask ROM. According to the mask ROM manufacturing method, QTAT can be achieved as compared with the conventional example.

In addition, recording ROM data with a relatively low energy can achieve the same effects as in the above-described embodiment.

In addition, since the etching process for removing the spacer 30 can be omitted, it is possible to effectively prevent the adverse effects such as the separated oxide film when wet etching is used and the etching damage of the semiconductor substrate when dry etching is used as described above. It becomes possible.

This makes it possible to improve the reliability of the mask ROM.

Next, another embodiment of the mask ROM in the embodiment of the present invention will be described with reference to FIGS. 59 to 66. FIG.

In this embodiment, the mask ROM is based on the NOR mask ROM.

FIG. 59 is a sectional view of the NOR mask ROM in this embodiment, and FIG. 104 is a diagram showing a cross section corresponding to the cross section taken along line C-C in FIG.

Referring to FIG. 59, n-type low concentration impurity regions 48 and high concentration impurity regions 51 are formed on the main surfaces of the p-type semiconductor substrate 40 at intervals.

The gate electrode 47 is formed on the channel region through the gate insulating film 46.

The spacer 50 is not formed on the sidewall of the predetermined gate electrode (in this case, the gate electrodes 47a and 47), and the spacer 50 is formed on the sidewall of the other gate electrode 47.

ROM data can be recorded using the presence or absence of the spacer 50. In ROM data writing, in this case, ion implantation of p-type impurities such as boron (B) is performed.

At this time, since the MISFET having the gate electrode 47a does not have the spacer 50, a p-type impurity layer (hereinafter referred to as a channel cut injection layer) 63 is formed to extend to the channel region.

The end of the channel cut injection layer 63 is not formed so as to extend to the channel region of the MISFET because the spacer 50 is provided in the MISFET having the spacer 50 formed on the sidewall of the gate electrode 47 (not shown). Displayed as a p-type impurity layer 63b, it is distinguished from the channel cut injection layer 63.)

Thereby, it is possible to make the threshold voltage Vth of the MISFET which does not have the spacer 50 higher than the threshold voltage Vth of the MISFET which has the spacer 50.

In this way, ROM data can be recorded.

In a mask ROM operating near 5V, the MISFET threshold voltage (Vth) in which ROM data is not written is about 0.5 to 2V, while increasing the threshold voltage (Vth) of the MISFET in which ROM data is written is about 3 to 10. It is possible.

As shown in FIG. 59, an interlayer insulating film 52 is formed to cover the gate electrode 47 and the spacer 50, and a contact hole 53 is formed at a predetermined position of the interlayer insulating film 52. As shown in FIG. .

A contact hole 53 is formed at a predetermined position of the interlayer insulating film 52.

A wiring layer 54 is formed on the interlayer insulating film 52, and is connected to the low concentration impurity region 48 and the high concentration impurity region 51 formed on the main surface of the p-type semiconductor substrate 40 through the contact hole 53. It is.

A protective film 55 is formed on the wiring layer 54.

Next, the manufacturing method of a mask ROM in a present Example is demonstrated using FIG. 60-65. FIG.

60 to 65 are cross sectional views sequentially showing the mask ROM manufacturing method in the present embodiment, and sectional views showing a part of the cross sectional views shown in FIG.

As shown in FIG. 60, the gate electrode 47 is formed on the p-type semiconductor substrate 40 with the gate insulating film 46 on the p-type semiconductor substrate 40 using the same method as the conventional example, and the gate electrode 47 is masked. The low concentration impurity region 48 is formed on the main surface of the p-type semiconductor substrate 41 in a self-aligned manner.

A spacer 50 is formed on the sidewall of the gate electrode 47 to form a high concentration impurity region 51 using the gate electrode 47 and the spacer 50 as a mask.

Referring next to FIG. 61, a resist pattern 56 is formed to expose a desired MISFET, and the spacer 50 is removed using this resist pattern 56 as a mask.

Then 62 also a p-type impurity ions such as to remove the resist pattern 56, using the gate electrode 47 and the spacer 50 as a mask hayo boron (B), as 10 ¹² to 10 ¹⁴ shown in It implants about cm <^-2> and the channel cut injection layer 63 is formed.

In the case of the present embodiment, as in the above-described embodiment, since the impurity is implanted in the cathode / drain region of the MISFET by using the gate electrode 47 and the spacer 50 as a mask, the ROM data is recorded. Can be said to be relatively low.

In this case, since boron B, which is lighter than phosphorus P described above, is used as the implantation impurity, the ion implantation energy is sufficient to be about 50 to 200 KeV.

Next, as shown in FIG. 63, the interlayer insulating film 52 is formed so as to cover the gate electrode 47 and the spacer 50, and as shown in FIG. 64, a contact is made at a predetermined position of the interlayer insulating film 52. As shown in FIG. The hole 53 is formed.

And as shown in FIG. 65, the wiring layer 54 is formed on the contact hole 53 and the interlayer insulation film 52. As shown in FIG.

A protective film 55 (not shown) is formed on the wiring layer 54 to complete the mask ROM.

As described above, in this embodiment, since ROM data can be recorded after the formation of the high concentration impurity region 51, it is possible to achieve QTAT as compared with the conventional example.

In addition, since ROM data can be recorded with a relatively low energy of 200 KeV or less, the same effects as in the above-described embodiment can be obtained.

In the above embodiment, after the resist pattern 56 was achieved, the spacer 50 of the desired MISFET was etched away using the resist pattern 56 as a mask, and then the resist pattern 56 was removed.

Then, ion implantation for writing ROM data was performed using the gate electrode 47 and the spacer 50 as a mask.

However, after removing the spacer 50, the resist pattern 56 may be used as a mask without removing the resist pattern 56, and ion implantation may be performed for ROM data recording.

FIG. 66 shows a state where the channel cut injection layer 63 is formed by ion implantation for recording ROM data using the resist pattern 56 as a mask.

Thus, by forming the channel cut injection layer 63 using the resist pattern 56 as a mask, the ROM data is more reliably compared to the case where the ROM data is written using the spacer 30 and the gate electrode 47 as a mask. Can be recorded.

That is, as shown in FIG. 66, since the sidewall in the opening of the resist pattern 56 is on the MISFET side where ROM data is written rather than the spacer 50, ion implantation is performed using this resist pattern 56 as a mask. In one case, it can be said that the channel cut injection layer 63 is less likely to extend to the channel region of the MISFET in which the ROM data is not recorded than when the spacer 50 is used as a mask.

In addition, since ion implantation for ROM data recording can be made relatively low in energy, it can be advantageous in miniaturization as compared with the case where the resist film thickness is required (in the case of high energy ion implantation).

Incidentally, the above-described oblique rotation ion implantation method may be used as an ion implantation method for recording ROM data.

This makes it possible to form the channel cut injection layer more easily to extend into the channel region of the desired MISFET.

In the case where the gate electrode 47 and the spacer 50 are used as masks, ion implantation is not prevented by the resist pattern 56 as compared with the case where ROM data is written using the resist pattern 56 as a mask. Impurities can be implanted at larger implant angles, and process condition determination has the advantage of increased degrees of freedom.

Next, another embodiment of the mask ROM according to the present invention will be described with reference to FIGS. 67 to 75. FIG.

This embodiment is based on the NOR mask ROM.

FIG. 67 is a sectional view of the NOR mask ROM in this embodiment, and is a diagram showing a cross section corresponding to the cross section shown in FIG.

Referring to FIGS. 67 and 59, the difference between the embodiment shown in FIG. 59 and this embodiment is that the spacer 50 is formed on the sidewall of the gate electrode 47a of the MISFET in which ROM data is written. There are two points in which the p-type impurity layer 63b is not formed in the source / drain region of the MISFET in which ROM data is not recorded.

Otherwise, the structure of this embodiment is the same as that of the embodiment shown in FIG.

As in the present embodiment, the spacer 50 is formed on the sidewall of the MISFET in which the ROM data is recorded, thereby obtaining the security effect described above.

Next, with reference to Figs. 68 to 75, the first to eighth steps of the manufacturing process of the mask ROM in this embodiment will be described.

65 to 75 are views showing sequential mask ROM cross-sections according to the manufacturing process in this embodiment, and showing cross sections corresponding to the cross sections shown in FIG.

Referring to FIG. 68, the gate electrode 47 is formed on the p-type semiconductor substrate 40 via the gate insulating film 46 using the same method as in the related art, and the gate electrode 47 is used as a mask to form n. By implanting ion impurities, low concentration impurity regions 48 are formed in a self-aligned manner.

Then 69 also a boron (B), p-type impurity ions such as to expose the MISFET formed in the resist pattern 57, and using this resist pattern 57 as a mask a desired, as 10 shown in the ^12th and The channel cut injection layer 63 is formed by injecting about 10 ¹⁴ cm ⁻² .

In this step, impurities can be introduced into the source / drain regions of the desired MISFET by using the resist pattern 57 as a mask. Therefore, as in the above-described embodiment, relatively low energy, in this case, injection energy of about 50 to 200 KeV is achieved. Ion implantation is possible.

Next, as shown in FIG. 70, a CVD film 49 is formed on the entire surface of the p-type semiconductor substrate 40 and anisotropically etched as shown in FIG. 71, thereby forming the spacer 50 on the sidewall of the gate electrode 47. As shown in FIG. To form.

Then, as shown in FIG. 72, the high concentration impurity region 51 is formed by ion implantation of n-type impurities using this spacer 50 as a mask.

As shown in FIG. 73, an interlayer insulating film 52 is formed to cover the gate electrode 47 and the spacer 50, and as shown in FIG. 74, a contact hole is formed at a predetermined position of the interlayer insulating film 52. As shown in FIG. 53).

Subsequently, as shown in FIG. 75, the wiring layer 54 is formed on the interlayer insulating film 52 and the contact 53, and the protective film 55 (not shown) is formed on the wiring layer 54, thereby providing a mask ROM. Is completed.

According to the mask ROM manufacturing method, it is possible to achieve QTAT as compared with the conventional example. In addition, the advantages of recording ROM data by low energy ion implantation are the same as in the above-described embodiment.

Moreover, since the film thickness of the resist pattern 57 can also be made thin, it can be said that it is advantageous also in refinement | miniaturization.

In addition, since the etching removal process of the spacer 50 is unnecessary as compared with the above-described embodiment, the problem that can be caused by using wet etching or dry etching is eliminated.

Although the above embodiment is described on the assumption that all n-type channel MISFETs are used as memory elements, the above-described embodiments can be applied to mask ROMs having p-type channel MISFETs as memory elements.

In this case, both the p-type and n-type in the above embodiment can be changed to the reverse conductivity type.

According to the mask ROM semiconductor device according to the present invention, it is possible to shorten the delivery time compared with the prior art.

For example, in the above-described conventional example, if the preprocess for manufacturing a mask ROM semiconductor device is assumed to be 100, the process from writing ROM data to completing the mask ROM semiconductor device is about 70 to 80% of the total. It can be said.

According to the present invention, since ROM data is written after the formation of the high concentration impurity region, the process can be made 20 to 40% of the whole until the mask ROM is completed after the ROM data is written.

That is, in the conventional manufacturing process, ROM data can be recorded after performing the eighth process (corresponding to FIGS. 84 to 89) in advance from the third process.

In another aspect of the present invention, since ROM data is recorded after the formation of the low concentration impurity region, the process from recording the ROM data to the completion of the mask ROM semiconductor device can be approximately 50%.

In other words, the ROM data can be recorded after the fifth step (corresponding to Figs. 84 to 86) is performed in advance in the third step of the conventional manufacturing step. As a result, the delivery time is surely shorter than in the related art.

In addition, since ROM data is written by low energy ion implantation in ROM data writing, it is possible to suppress the transverse diffusion of the implanted impurities in the semiconductor substrate.

This makes it possible to considerably lower the possibility that impurities for ROM data writing are injected into the channel region of the transistor in which the ROM data is not written, when the transistors in which the ROM data is not written and the transistor in which the ROM data is written are adjacent to each other.

In other words, it is possible to effectively prevent adverse effects on adjacent transistors.

It is thereby possible to improve the reliability of the mask ROM semiconductor device.

It is also possible to use an ion implantation apparatus in order to record ROM data by ion implantation at low energy.

As a result, it is possible to significantly reduce the cost of the ion implanter as compared with the case of writing ROM data (high energy ion implantation is required) by ion implantation to penetrate the gate electrode to shorten the delivery time. At the same time, the installation space of the ion implantation apparatus can be reduced.

By recording the ROM data with low energy, even when a resist film is used as a mask for recording the ROM data, the resist film and the film thickness can be made thin.

This is advantageous for miniaturizing the mask ROM semiconductor device. In addition, since the transistor serving as the memory element has an LDD structure, the transistor can be manufactured simultaneously in the peripheral circuit, so that the manufacturing process can be reduced.

Thereby, manufacturing cost can be reduced.

In addition, the impurity concentration in the channel region of the transistor may be uneven. In this case, since the decrease in carrier mobility at the center portion of the channel region can be suppressed low, the performance of the transistor is improved as a whole.

In other words, it is possible to improve the performance of the transistor serving as the memory element at the same time as the ROM data is written.

Although the invention has been described and described in detail, it is to be understood that the manners and embodiments of the description are the same and the spirit and scope of the invention are limited only by the appended claims.

Claims (32)

A mask ROM semiconductor device comprising a first transistor having a low threshold voltage connected in series and a second transistor having a relatively high threshold voltage, the first conductive semiconductor substrate having a main surface, and the first and the first transistors. A first impurity region, a shared impurity region and a second impurity region of a second conductivity type formed on a main surface of the semiconductor substrate at intervals from each other so as to form a channel region of the two transistors, the first impurity region and the shared impurity region A first gate electrode formed through an insulating film on the first channel region located between the second gate electrode formed through an insulating film on the second channel region located between the second and the shared impurity regions; A first channel impurity region of a second conductivity type formed in the first channel region and in contact with the first impurity region and the shared impurity region; A first channel cut impurity region of a first conductivity type formed in a second channel region adjacent to the second impurity region to control the magnitude of the threshold voltage of the second transistor, and to control the magnitude of the threshold voltage of the second transistor Between the first channel type impurity region of the first conductive type and the second channel cut impurity region formed in the second channel region adjacent to the common impurity region and the threshold voltage of the second transistor. And a second channel region of the second conductivity type disposed in the second channel region. The mask ROM semiconductor device of claim 1, wherein the mask ROM semiconductor device is a NAND type mask ROM semiconductor device. The mask ROM semiconductor device of claim 1, wherein the first and second transistors have an LDD structure. The mask ROM of claim 1, further comprising a sidewall insulating film formed on a sidewall of the first gate electrode, an intermediate insulating film covering the sidewall insulating film, an upper surface of the first gate electrode, and a side surface and an upper surface of the second gate electrode. Semiconductor device. The mask ROM semiconductor device of claim 2, wherein concentrations of the first and second channel cut impurity regions are in a range of 10 ¹⁵ and 10 ¹⁹ cm ⁻³ . The method of claim 5, wherein concentrations of the first and second channel impurity regions are in a range of 10 ¹⁶ and 10 ¹⁷ cm ⁻³ . A method of manufacturing a mask ROM semiconductor device comprising a first transistor having a high threshold voltage and a second transistor having a relatively low threshold voltage connected in series with a gate insulating film interposed on a main surface of a semiconductor substrate of a first conductive type. Forming the first and second gate electrodes of the first and second transistors, and forming source and drain regions of the first and second transistors on the main surface of the semiconductor substrate, respectively. Forming a first impurity region shared impurity region and a second impurity region, forming a sidewall insulating film on a side surface of the first gate electrode, and using the first gate electrode, the second gate electrode, and the sidewall insulating film as a mask The ion impurity is injected into the second impurity region and the shared impurity region to control the threshold voltage of the second transistor. Mask ROM, a semiconductor device including the step of. The method of claim 7, wherein the first and second transistors have an LDD structure, and the forming of the first impurity region, the shared impurity region and the second impurity region may include a first low concentration impurity region, a shared low concentration impurity region, and And forming a first high concentration impurity region, a shared high concentration impurity region, and a second high concentration impurity region using the sidewall insulating film as a mask after forming the second low concentration impurity region. The method of claim 7, wherein the forming of the sidewall insulating film includes forming the sidewall insulating film on side surfaces of the first and second gate electrodes and removing the sidewall insulating film formed on side surfaces of the second gate electrode. Method of manufacturing a mask ROM half-assembly device. 8. The method of claim 7, wherein the impurity controlling the magnitude of the threshold voltage of the second transistor is of a second conductivity type. 11. The method of claim 10, further comprising the step of diffusing the impurity, such as a pair of controlled impurity regions, formed by implantation of impurity ions of the second conductivity type to have ends overlapping each other at a position under the second gate electrode. Method of manufacturing a mask ROM semiconductor device. The method of manufacturing a mask ROM semiconductor device according to claim 10, wherein the ion implantation ratio of the impurity of the second conductivity type is in the range of about 10 ¹⁴ and 10 ¹⁷ cm ^-3 . The method of claim 10, wherein the ion implantation is a gradient rotation ion implantation. The mask ROM semiconductor device of claim 13, wherein the gradient rotation ion implantation has an ion implantation angle of the second conductive impurity for gradient rotation ion implantation in a range of 10 and 45 ° in a direction perpendicular to a main surface of the semiconductor substrate. Manufacturing method. 8. The method of claim 7, wherein the impurity controlling the magnitude of the threshold voltage of the second transistor is of a first conductivity type. The method of manufacturing a mask ROM semiconductor device according to claim 15, wherein an ion implantation ratio of the impurity of the first conductivity type is in a range of 10 ¹² and 10 ¹⁴ cm ^-2 . The method of manufacturing a mask ROM semiconductor device according to claim 16, wherein the ion implantation of the impurity of the first conductivity type is a gradient rotation ion implantation. 18. The method of claim 17, wherein an ion implantation angle of the impurity of the first conductivity type for the tilt rotation ion implantation is in a range of 10 and 45 degrees in a direction perpendicular to the main surface of the semiconductor substrate. A method of manufacturing a mask ROM semiconductor device comprising a first transistor having a high threshold voltage connected in series and a second transistor having a relatively low threshold voltage, wherein a gate insulating film is provided on the main surface of the semiconductor substrate of the first conductive type. Forming a first and a second gate electrode of the first and second transistors and a second conductive type first forming a source and a drain region of the first and second transistors on a main surface of the semiconductor substrate; Forming an impurity region, a shared impurity region, and a second impurity region; forming a resist pattern covering the first gate electrode and exposing the second gate electrode; and using the resist pattern and the second gate electrode as a mask Impurity is formed in the second impurity region and the shared impurity region to control the magnitude of the threshold voltage of the second transistor. The impurities introduced so that the ends of the pair of control impurity regions formed by impurity implantation to control the magnitude of the threshold voltage of the second transistor after the ion implantation and the ion implantation overlap at a position under the second gate electrode. A method of manufacturing a mask ROM semiconductor device comprising the step of diffusing a film. 20. The method of claim 19, wherein the impurity controlling the magnitude of the threshold voltage of the second transistor is of a second conductivity type. 20. The method of claim 19, wherein the impurity controlling the magnitude of the threshold voltage of the second transistor is a first conductivity type. 20. The method of claim 19, further comprising forming a sidewall insulating film on a side surface of the first gate electrode, wherein the resist pattern covers the first gate electrode and the sidewall. 20. The method of claim 19, further comprising forming an insulating film on side surfaces of the first and second gate electrodes, and removing the sidewall insulating film on the side surfaces of the second gate electrode using the resist pattern as a mask. Method of manufacturing a mask ROM semiconductor device. A method of manufacturing a mask ROM semiconductor device comprising a first transistor having a relatively low threshold voltage connected in series and a second transistor having a relatively high threshold voltage, wherein the first transistor is formed on a main surface of a semiconductor substrate of a first conductive type. And forming a second conductive impurity layer in a region where the second transistor is to be formed, and defining a channel region of the first and second transistors by a gate insulating film on a main surface of the first conductive semiconductor substrate. And forming a first impurity region, a shared impurity region, and a second impurity region of a second conductive type to form a drain region, forming a sidewall insulating film on a side of the first gate electrode, and forming the first gate electrode. And using the second gate electrode and the sidewall insulating layer as a mask, the second impurity region and the shared impurity region of the second transistor. A method for manufacturing a mask ROM semiconductor device, comprising the step of ion implanting impurities of a first conductivity type for controlling the magnitude of a threshold voltage. 25. The method of claim 24, wherein the first and second transistors have an LDD structure, and the forming of the first impurity region shared impurity region and the second impurity region is performed by the first low concentration impurity region, the shared low concentration impurity region, and the second low concentration. And forming a first high concentration impurity region shared high concentration impurity region and a second high concentration impurity region using the sidewall insulating film as a mask after the formation of the impurity region. A method for manufacturing a mask ROM semiconductor device according to claim 24, wherein the ion implantation ratio of the impurity of the first conductivity type is in the range of 10 ¹¹ and 10 ¹⁴ cm ^-2 . 25. The method of claim 24, wherein the ion implantation is gradient rotation ion implantation. 27. The method of manufacturing a mask ROM semiconductor device according to claim 26, wherein energy for implanting ions into the impurity region of the first conductivity type is in a range of 100 and 200 KeV. The method of manufacturing a mask ROM semiconductor device according to claim 27, wherein an implantation angle of the first conductive impurity of the oblique rotation ion implantation is in a range of 10 and 45 degrees in a direction perpendicular to a main surface of the semiconductor substrate. A method of manufacturing a mask ROM semiconductor device comprising a first transistor having a relatively low threshold voltage connected in series and a second transistor having a relatively high threshold voltage. Forming a second conductive impurity layer when the second transistor is to be formed, and first and second transistors of the first and second transistors having a gate insulating film formed on a main surface of the semiconductor substrate of the first conductive type. Forming a second gate electrode; and a first impurity region, a shared impurity region, and a second impurity region of a second conductivity type forming source and drain regions of the first and second transistors on a main surface of the semiconductor substrate. Forming a resist pattern to cover the first gate electrode and to expose the second gate electrode; and forming the resist pattern and the second gate electrode. Method for manufacturing a mask ROM, a semiconductor device of the second impurity region and the shared impurity region by a disk and a step of ion-implanting a first impurity of a conductivity type for controlling the magnitude of the threshold voltage of the second transistor. 31. The method of claim 30, further comprising forming a sidewall insulating film on a side surface of the first gate electrode, wherein the resist covers the first gate electrode and the sidewall insulating film. 32. The mask ROM semiconductor device of claim 30, further comprising forming sidewall insulating films of the first and second gate electrodes and removing the sidewall insulating films of the second gate electrode using the resist pattern as a mask. Manufacturing method.