JPH0475376A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To achieve the more higher integration density of a ROM circuit by forming a second same-conductivity-type conductor layer beneath a first conductor layer constituting the source and the drain of a transistor, and shorting the source and the drain of the transistor with the conductor layer. CONSTITUTION:A region 4 has the approximately rectangular planar shape with respect to a transistor which is not used for constituting a ROM. The region includes the entire region of a transistor which is formed of a gate 2, a source 3a and a drain 3b and the peripheral part of a field oxide film 5 for isolating the neighboring transistors. The heavy dose (implantation of a large amount) of P<+> ions is performed as shown by arrow lines. At this time, a mask 7 having holes 6 corresponding to the regions 4 is provided at the upper side of a semiconductor substrate 1 so that the P<+> ions are implanted only into the regions 4. The P<+> ions are implanted through the mask 7. Then, a heavy dose layer 8 which is the P<+>-type conductor layer is formed at the lower side of the gate 2, the source 3a, the drain 3b and the peripheral part of the field oxide film 5. Therefore, the source 3a and the drain 3b are shorted through the heavy dose layer 8. Namely the transistor is shorted.

Description

[Detailed description of the invention] <Industrial application field> The present invention relates to a semiconductor integrated circuit device.

<Prior Art> A conventional semiconductor integrated circuit device will be described below. Conventionally, for example, when constructing a P-channel ROM, the ROM pattern is constructed of a diffusion layer, a polysilicon layer, or a metal layer formed on a semiconductor substrate.
Contacts are provided in the circuit to connect the layers and short circuit the transistors.

<Problems to be solved by the invention> However, providing contacts in this way
Since the circuit pattern becomes complicated, it becomes an obstacle to improving the degree of integration of semiconductor integrated circuit devices.

In particular, ROM pattern circuits are a part that is expected to be highly integrated efficiently because they are a collection of identical circuits that are repeatedly formed. could not be achieved.

The present invention was devised in view of the above circumstances, and an object of the present invention is to provide a highly integrated semiconductor integrated circuit device, such as a P-channel ROM, without forming contacts.

<Means for Solving the Problems> In order to solve the above problems, the semiconductor integrated circuit device of the present invention provides a circuit formed by short-circuiting some transistors among a plurality of transistors formed on a semiconductor substrate. In the semiconductor integrated circuit device, the short circuit occurs between a region forming the transistor and a peripheral portion of a field oxide film separating adjacent transistors from a first conductive layer forming a source and a drain of the transistor. A heavy dose of ions of the same conductivity type is performed to form a second conductive layer of the conductivity type below the transistor, and the source and drain of the transistor are short-circuited by this second conductive layer. It is.

Furthermore, in order to maintain a sufficient distance between adjacent second conductive layers to prevent short circuits between the second conductive layers, it is preferable to perform heavy dosing after forming a polysilicon layer on the field oxide film.

<Operation> When the source, drain, and gate of a transistor are heavily dosed with ions of the same conductivity type as the first conductive layer constituting the source and drain, a second conductive layer of this conductivity type is formed below the transistor. The second conductive layer short-circuits the source and drain, ie, the transistor.

Furthermore, if a heavy dose is performed after forming a polysilicon layer on a field oxide film, ions will not pass through the field oxide film. Therefore, since the second conductive layers are formed adjacent to each other with a sufficient distance, the second conductive layers are not short-circuited.

<Example> Hereinafter, the present invention will be described in detail with reference to the drawings. 1 and 2 are drawings for explaining a first embodiment of the present invention, in which FIG. 1 is an explanatory cross-sectional view and FIG. 2 is an explanatory plan view. FIG. 3 is an explanatory cross-sectional view of the second embodiment, and FIG. 4 is an explanatory plan view of the third embodiment. The embodiments all take as an example a semiconductor integrated circuit device in which a ROM is constituted by a plurality of transistors formed on a semiconductor substrate.

First, a first example will be described.

As shown in FIG. 2, on the surface of the N-type semiconductor substrate 1,
A polysilicon layer 2, which is the gate of the transistor, and P-type diffusion layers 3, which are the source and drain regions of the transistor, are formed on both sides of the polysilicon layer 2. A plurality of P-channel transistors are formed.

ROM is constructed using these P-channel transistors. At this time, there are transistors that are not used in the configuration of the ROM, and conventionally, such transistors have been short-circuited using contacts as described above. In this embodiment, for unused transistors, a region 4 which is approximately rectangular in plan view as shown in FIG. For a region including the entire area of the transistor and the peripheral portion of the field oxide film 5 separating adjacent transistors,
A heavy dose (large amount of implantation) of P+ ions is performed as indicated by the arrow.

At this time, as shown in FIG. 1, in order to implant P ions only into the region 4, the region 4
A mask 7 having an opening 6 corresponding to the P ion is implanted through this mask 7. Then, in the semiconductor substrate 1, a heavy-dose layer 8, which is a P-type cell layer, is formed below the gate 2, the source 3a, the drain 3b, and the peripheral portion of the field oxide film 50.
A and the drain 3b are short-circuited by this heavy dose N8, that is, this transistor is short-circuited.

Note that in the case of a heavy dose of P+ ions, the ions are implanted with extremely high energy, so that the P2 ions penetrate the field oxide film 5, so that the distance d between the above-mentioned deep-dose layers 8 formed at the bottom of adjacent transistors is It is not always ensured sufficiently, and there is a possibility that the heavy dose layers 8 may be short-circuited in some cases.

The second embodiment is able to avoid these problems of the first embodiment, and differs from the embodiment shown in FIG. 1 only in the following points. That is, as shown in the third session, after forming polysilicon layer 9 on field oxide film 5, a heavy dose is performed. Then, since the P ion field oxide film 5 is not implanted to the bottom, a sufficient distance d between the heavy dose layers 8 is ensured as shown in the figure, so that the heavy dose layers 8 are adjacent to each other. Matching transistors will not be shorted together.

Next, a third example will be described.

In the first and second embodiments, the heavy dose layer 8
In this embodiment, the heavy dose layer 8 is formed under approximately half of the region where the transistors are formed.

That is, in order to short-circuit the source and drain of a transistor, the region 4 explained in FIG. Even if the region 4a is substantially rectangular and has an area about half of the region 4 shown in the figure, but extends over the source and drain, it is possible to effectively short-circuit the transistor as in the first embodiment.

By forming a heavy dose layer in such a region 4a, as can be seen by comparing FIG. 4 with FIG. 2, the interval between the P-type diffusion layers, which are the source/drain regions, can be made shorter than before, which improves the ROM circuit. It is possible to achieve even higher integration.

<Effects of the Invention> As explained above, the semiconductor integrated circuit device of the present invention has the following effects:
When short-circuiting some of the transistors formed on a semiconductor substrate to form a predetermined circuit, the same type of conductivity as the first conductive layer constituting the source and drain of the transistor to be short-circuited. A second conductive layer of the same conductivity type as the first conductive layer is formed below the transistor by implanting a large amount of ions of the same type, and the source and drain of the transistor are short-circuited by this conductive layer.

Therefore, the semiconductor integrated circuit device of the present invention not only allows the construction of ROM pattern circuits and the like to be easily and easily achieved, but also allows short-circuiting of transistors by a heavy dose of ions without making contacts. By applying this to, for example, approximately half of the area, the distance between the first conductive layers can be shortened, making it possible to achieve higher integration of transistor elements.

In addition, if a heavy dose is performed after forming a polysilicon layer on the field oxide film, second conductive layers are formed adjacent to each other with a sufficient distance between them, so that short circuits between the second conductive layers can occur. There is no.

[Brief explanation of drawings]

1 and 2 are drawings for explaining a first embodiment of the present invention, in which FIG. 1 is an explanatory cross-sectional view and FIG. 2 is an explanatory plan view. Figure 3 is a cross-sectional explanatory diagram of the second embodiment;
The figure is an explanatory plan view of the third embodiment. 1...Semiconductor substrate, 2...Gate, 3...
P-type diffusion layer, 3a...source, 3b...drain,
8...Heavy dose layer. Figure 3 Figure 4

Claims (1)

[Claims] (1) In a semiconductor integrated circuit device including a circuit formed by short-circuiting some transistors among a plurality of transistors formed on a semiconductor substrate, the short circuit is caused by a region constituting the transistor and an adjacent transistor. A heavy dose of ions of the same conductivity type as the first conductive layer constituting the source and drain of the transistor is applied to the peripheral portion of the field oxide film separating the transistors, and a second conductive layer of the conductivity type is applied below the transistor. 1. A semiconductor integrated circuit device, wherein a second conductive layer is formed, and a source and a drain of the transistor are short-circuited by the second conductive layer.