KR0131950B1 - Method for reporting state of common bus on initializing - Google Patents

Abstract

According to the present invention, one main processor 10 and a plurality of coprocessors 20 are interconnected through redundant first and second common buses, and the coprocessors 20 are connected to the first and second common buses. Hardware check using the clock pulse, the frame sync pulse, and the occupancy time for the first or second common bus 60 provided from the main processor 10 and the software state using the loopback data. And an input / output processor 30 is connected to the main processor 10 through the first and second common buses 60, and the input / output processor 30 is connected to the main processor 10. The present invention relates to a method for reporting a common bus state to an operator when a processor is initialized in an electronic switchgear that can display information of the information through an input / output terminal (40). (10) checks the state of the first and second common bus 60 in hardware and software state upon initialization by checking the state of the first and second common bus 60 in a normal state. A first process of detecting the first / second common bus 60 in the steady state and transmitting the common bus 60 in the steady state to the main processor 10; If the first / second common bus 60 is in an abnormal state at the same time as a result of performing the first process, the second processor 20 transmits a reason for the abnormal state to the main processor 10; The main processor 10 applies the reason for the abnormal state of the first and second common bus 60 and the first and second common bus 60 in use from the coprocessor 20 to the input / output processor 30. A third process is performed by the input / output processor 30 to display the reason for the abnormal state of the first / second common bus 60 and the first and second common bus 60 in use to the operator through the input / output terminal 40. Include.

Description

How to Report Common Bus Status During Processor Initialization at Electronic Switching

1 is a block diagram of a hardware system applied to the present invention.

2 is a block diagram illustrating the matching between a number of auxiliary processors and a main processor.

3 is a flowchart illustrating a processor initialization reason and a process of reporting a common bus state when the processor is initialized.

4 is a flowchart illustrating a reporting process when a common bus fault condition detected by the hardware of the present invention occurs.

5 is a flowchart showing a reporting process when a common bus fault condition detected by the software of the present invention occurs.

6 is a process flow diagram upon receipt of initialization reason and common bus state information received by a particular or multiple processor of the present invention.

* Explanation of symbols for main parts of the drawings

10: main processor 20: coprocessor

30: I / O Processor 40: I / O Terminal

50: debugging terminal 60: common bus

The present invention relates to a method for reporting a status of a common bus used by a processor when a processor is initialized in an electronic switch, and in particular, an electronic switch that promptly informs a system operator of a failure occurring when a common bus is used to perform a recovery operation appropriately. The present invention relates to a state reporting method of a common bus at processor initialization.

In general, a common bus shared between the main processor, which is the upper level processor of a conventional typical electronic switch, and the coprocessors, which are the plurality of lower level processors, is a physical hardware path that allows communication data to be transmitted and received between the processors. . Therefore, when the common bus is in an abnormal state, communication between processors cannot be performed, so that the service of the electronic switchboard may cause a temporary interruption state or a long-term service interruption phenomenon.

On the other hand, the abnormal state of the common bus may include a hardware-detectable clock fault, a frame sync fault, a particular processor occupying the common bus for a time greater than or equal to a threshold value, and the like. For example, a loopback test for identifying a common bus abnormality state by receiving and comparing data transmitted by a processor again using a common bus.

Therefore, in the prior art, when a common bus fault condition is detected in each processor with respect to the occurrence of a common bus fault condition as described above, an interrupt is generated and the corresponding fault condition is detected so that a clock fault, frame sync fault, or loopback test failure occurs. The recovery operation was performed by switching the duplicated common bus. In addition, when a specific processor monopolized the common bus for a time exceeding a threshold, the recovery operation was forcibly released by occupying the common bus.

However, in the above-described conventional method, since the recovery operation is performed in each processor, the operator cannot determine the state through the I / O terminal, which is the operator terminal connected to the I / O processor, which is the operator matching processor, and check the common bus state. Since there is no obligation to do so, if the operator does not deliberately check the common bus status of a particular processor, in case of continuous common bus failure, each processor will only perform common bus switchover operation or common bus de-occupation operation and fail to perform normal inter-processor communication functions. As a result, service interruption of the electronic exchange may be brought about.

In addition, the debugging can be matched by RS-232C method in order for the operator to check the common bus status of a specific processor (for example, the common bus currently used among the redundant common buses or whether an abnormal condition occurs on the common bus). You can check the common bus status by using the instructions provided by the processor you want to test by connecting the terminals, but this is cumbersome to connect and check the terminals for each processor you want to check.

As described above, in the related art, there is a limited method for an operator to check when an abnormal state of a common bus shared by a processor occurs, and thus, when an operator encounters a common bus abnormal state, appropriate recovery measures (for example, processor board replacement and common bus connection) are performed. There was a problem that can not be carried out quickly).

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems of the prior art, and an object of the present invention is to provide an operator with an ability to recognize an abnormal state and a recovery state of a common bus used by a processor at the time of processor initialization of an electronic switchboard. The present invention provides a method for reporting a common bus state at processor initialization of an electronic exchange.

In order to achieve this object, the present invention provides that one main processor and a plurality of coprocessors are interconnected through redundant first and second common buses, and the coprocessors 20 are connected to the first and second common buses. The abnormal state can be performed through a hardware check using a clock pulse, a frame sync pulse, and an occupancy time for the first or second common bus provided from the main processor, and a software check using loopback data. An I / O processor is connected to the main processor through a common bus, and the I / O processor relates to a method of reporting a common bus state to an operator when the processor is initialized in an electronic switch that can display information from the main processor through an I / O terminal. The coprocessor, upon initialization, initializes the phase of the first and second common buses. Checking a state in hardware and software, detecting a first / second common bus in a steady state, and transmitting the common bus in a steady state to a main processor; A second step of, if the first / second common bus is in an abnormal state simultaneously as a result of performing the first process, the coprocessor sends a reason for the abnormal state to the main processor; The primary processor applies the first / second common bus in use from the coprocessor and the reason for the abnormal states of the first and second common buses to the input / output processor so that the first / second processor is in use to the operator via the input / output terminal. And a third process of displaying the reason for the abnormal state of the common bus and the first and second common buses.

Other objects and various advantages of the present invention will become more apparent from the preferred embodiments of the present invention described below with reference to the accompanying drawings by those skilled in the art.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 is a block diagram of a hardware system applied to the present invention. As shown in the figure, the hardware system applied to the present invention includes a main processor 10, a plurality of coprocessors 20, an input / output processor 30, an input / output terminal 40, a debugging terminal 50, and a common bus ( 60).

The main processor 10 is a high-level processor of the electronic switchboard, and includes application programs such as an operating system, call processing, number translation, and operation maintenance related to controlling the overall operation of the electronic switchboard, and the clock and the common bus 60. Provide frame sync.

In addition, the coprocessor 20 is a sub-processor of the electronic switchboard, and includes an operating system and related programs such as signal processing, relay control, and state sensing, and acquires a bus usage right from the processor 10 through the common bus 60. In one case, communication data is transmitted and received.

In addition, the input / output processor 30 is a processor for operator matching, and is an input / output control-only processor for outputting a message generated in the system to the input / output terminal 40 such as command conformity check, result message output, system message output, and the like.

Meanwhile, the input / output terminal 40 is an input / output terminal that is connected to the input / output processor 30 and used by an operator to perform a function such as inputting a command, outputting an input result, checking a system message, and the debugging terminal 50. As a dummy terminal used by the operator for debugging purposes, the operator connects the main processor 10 and the plurality of coprocessors 20 in an RS-232C matching manner.

In addition, the common bus 60 is a physical hardware bus for allowing a plurality of processors to operate in a state in which the same bus resources are shared, and is a physical transmission / reception path that operates in a redundant manner to ensure reliability, and the main processor 10 ) Is a path for transmitting and receiving data between the coprocessor 20 and the main processor 10 and the input / output processor 30.

Next, a method of reporting a common bus state upon processor initialization in an electronic switch according to a preferred embodiment of the present invention in a hardware system applied to the present invention including the above-described configuration will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram illustrating a match between a plurality of coprocessors 20 and a main processor 10. The abnormal state of the common bus 60 in the bus matcher 25 (for example, a clock fault or a frame). Sync fault, which occupies the bus over the time limit of a specific processor) .In this case, if a fault condition is detected, it informs the main processor 10 that a common bus fault has occurred by generating a common bus fault interrupt. The main processor 10 checks the cause of the common bus fault stored in the predetermined area in the interrupt service routine and performs an appropriate recovery operation according to the cause.

3 is a detailed flowchart of a preferred embodiment of the present invention, and shows a process of reporting a processor initialization and a common bus state when the coprocessor 20 is initialized.

First, the coprocessor 20 reads the initialization reason in a predetermined area at the time of initialization and transmits it to the main processor 1 using communication data (step 300).

Next, to check whether the operation of the first common bus 60 is normal (step 302) to check the common bus state, and if it is normal, the common bus 60 used by the processor 20 is first common. Transfer the bus to the main processor (step 304), and if the first common bus 60 is abnormal in step 302, transfer to the second common bus 60 (step 306), and then the second common bus ( It is checked whether the operation of 60) is normal (step 308). At this time, if it is normal, similarly to step 304, the common bus 60 currently used by the processor 20 is transmitted to the main processor 10 as the second common bus (step 310), and terminates normally. Since the common bus 60 is not available, the reason why the common bus is not available is stored in an area for storing the initialization reason (step 312), and the initialization process of the processor is performed again.

Next, FIG. 4 is a flowchart illustrating a reporting process when a common bus error condition detected by the hardware of the present invention occurs.

First, when a common bus fault interrupt is generated (step 400), the reason for generating the common bus fault stored in a predetermined area is read (step 402). If the generated fault is a clock fault (step 402, 404), if the generated fault is a clock fault, the clock fault is stored and the clock fault generation count is increased (step 408). If it is a fault, store the fact that a frame sync fault has occurred for the reason for the common bus fault and increase the frame sync fault occurrence count (step 410), and if the fault is a fault that a particular processor has occupied the common bus for more than the threshold, then the common bus Store the fact that a bus occupied fault above the threshold was raised for the reason for the fault, increase the bus occupancy count for a time above the threshold (step 412), force release of the bus occupancy (step 420), and the type and common status of the common bus fault that occurred. Which bus is the common bus, to the main processor 10 (step 426). ).

Next, after step 408,410, it is determined whether the bus in which the fault has occurred is the first common bus or the second common bus (step 414), and if the first common bus is switched to the second common bus (step 416), on the contrary, If it is a common bus, switch to the first common bus (step 418), and compare the number of times the bus switching is performed to a predetermined threshold value or more (step 422). If the threshold is exceeded, the reason for the processor initialization that the common bus is not available is stored in a certain area. (Step 428) and perform a processor initialization.

In addition, if the number of times bus switching is performed in step 422 is not greater than or equal to the threshold value, the number of times bus switching is performed is increased by 1 (step 424). Is sent to the main processor 10 (step 426) and ends.

On the other hand, when a loopback test failure is detected, a flowchart showing a reporting process when a common bus abnormality condition detected by the software of the present invention of FIG. 5 is performed is performed.

First, the reason for generating the common bus fault is stored as a loopback test failure (step 500), the bus in which the common bus fault has occurred is determined (step 502), and if the first common bus is replaced, the recovery operation is performed by switching to the second common bus ( In step 5040, on the contrary, if the second common bus is faulted, the transfer operation is performed by switching to the first common bus (step 506).

Next, the threshold number is successively compared with the number of times bus switching is performed (step 508). If the threshold value is greater than or equal to the threshold value, the processor initialization reason that the common bus is unavailable is stored in a predetermined area (step 514), and the processor initialization is performed.

On the other hand, if the number of consecutive bus changes in step 508 is less than or equal to the threshold, the number of consecutive bus changes is increased by '1' (step 510) and the type of common bus fault and the common bus in which the fault occurs Transmits to the main processor 10 (step 512) and terminates.

Next, when the main processor 10 receives the initialization reason, the common bus status, the common bus fault occurrence reason, and the bus in which the common bus occurred when the processor is initialized from the specific or multiple processors according to the above process, As shown in FIG. 6, I / O is reconfigured for each processor to receive the initialization reason, the reason why the fault occurred on the common bus, and the bus in which the bus where the common bus fault occurred is duplicated. It is output through the input / output terminal 40 connected to the processor 30.

First, it is determined whether the received communication data is normal (step 600). If it is normal, the received message is determined (step 602, 606). If the received message relates to the initialization reason and common bus state at the time of processor initialization, each transmitted processor Reclassify the 20 and reconfigure the reason for the processor initialization and the state of the common bus to a format known to the operator (step 604), and output it through the input / output terminal 40 connected to the input / output processor 30 ( In step 610, if the received message is communication data related to the occurrence of a common bus fault, the processor 20 divides each transmitted processor 20 and reconfigures the bus in which the common bus fault occurs for each processor in a format that an operator can know (step 608). The output is performed through the input / output terminal 40 as in step 610.

As described above, according to the present invention, the operator can easily perform the failure and recovery of a specific processor, thereby easily extracting the maintenance of the common bus resource and the statistical data on the occurrence of the common bus failure, It has the advantage of preventing system service interruption.

Claims (5)

One main processor 10 and a plurality of coprocessors 20 are interconnected via redundant first and second common buses 60, and the coprocessors 20 are connected to the first and second common buses. Hardware check using the clock pulse, the frame sync pulse, and the occupancy time for the first or second common bus 60 provided from the main processor 10 and the software state using the loopback data. And an input / output processor 30 is connected to the main processor 10 through the second and second common buses 60, and the input / output processor 30 is connected to the main processor 10. In a method for reporting a common bus state to an operator at processor initialization in an electronic switch that can display information through an input / output terminal (40), the coprocessor (10) is initially initialized. In order to detect the state of the first and second common bus 60 in hardware and software, the first and second common bus 60 in the normal state are detected, and the common bus 60 in the normal state is detected. A first process of transmitting to the main processor 10; If the first / second common bus (60) is in an abnormal state at the same time as a result of performing the first process, the second processor (20) transmits a reason for the abnormal state to the main processor (10); The main processor 10 informs the input / output processor 30 of the reason for the abnormal state of the first / second common bus 60 and the first and second common bus 60 in use from the coprocessor 20. So that the input / output processor 30 displays an error state reason of the first / second common bus 60 and the first and second common bus 60 in use to the operator through the input / output terminal 40. The common bus state reporting method at the time of processor initialization in the electronic switch comprising a third process. The method of claim 1, wherein the first process comprises: reading a processor initialization reason in a predetermined area and transmitting a processor initialization reason to the main processor (10); The operation of the first common bus 60 is inspected among the redundant common bus 60, and if the operation is normal, the common bus 60 currently used is the first common bus 60 to the main processor 10. And switching to the second common bus 60 and checking the operation of the second common bus 60 in the abnormal state. If the operation of the second common bus 60 is normal, the current common bus 60 is transmitted to the main processor 10 when the operation is normal. If the abnormal state occurs, the common bus 60 cannot be used. And storing the reason for initialization in the predetermined area for storing the initialization reason. The method of claim 1, wherein the second process comprises: reading a common bus error state reason detected and stored in hardware in a predetermined area when a common bus fault interrupt occurs due to detection by hardware; If the fault condition of the common bus 60 is a clock fault, store the common bus fault condition reason as a clock fault, increase the clock fault occurrence count, switch the faulty common bus 60 to another redundant common bus, and frame sync If it is a fault, it stores the reason for the abnormal condition as frame sync fault, increases the count of frame sync fault occurrences, transfers the common bus in abnormal status to another redundant common bus, and if it is determined to occupy the bus above the threshold of a specific processor, occupies the threshold above the threshold. Storing an abnormal state due to a value, increasing a bus occupancy fault occurrence count above a threshold and forcibly releasing the occupancy of the common bus; If the counted number of transfers is greater than or equal to the set threshold, if the threshold is greater than or equal to the threshold, the processor initializes the reason for not using the common bus in a certain area and reinitializes it. A method of reporting a common bus state when a processor is initialized in an electronic switch, characterized in that the step of transmitting the kind and the generated common bus to the main processor (10). 2. The method of claim 1, wherein the second process comprises: storing a reason why a common bus (60) abnormal condition occurs as a loopback test when a loopback test failure is detected by software; Determining a common bus 60 in an abnormal state and transferring the redundant common bus 60 to another redundant bus; Comparing the number of switching times of the common bus 60, if the number of times of switching is greater than or equal to the set threshold, the processor initialization reason that the common bus cannot be used is stored in a certain area and the processor is initialized. And transmitting a common bus abnormal state type and a common bus (60) having an abnormal state to the main processor (10). The method of claim 1, wherein the third process includes: data from the plurality of coprocessors 20 including a bus for which a processor initialization reason, a common bus state, a common bus abnormal state type, and a common bus 60 in which an abnormal state has occurred are generated. Determining whether the received data is normally received when receiving and determining what data is normally received; The processor in the electronic switchboard, characterized in that the divided data for each of the coprocessor 20 that transmits the received data to be reconfigured in a format known to the operator and output to the input and output terminals connected to the input and output processor 30. How to report common status at initialization.