JP2600614B2 - An exchange system that can collect fault information - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching system for collecting fault information, and more particularly to a switching system capable of collecting fault information for collecting communication history with a higher-level control unit by using a dual port memory.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a configuration example of a conventional switching system composed of a plurality of functional blocks. FIG. 4 shows an example of a configuration in each functional block of a conventional switching system. Conventionally, as shown in FIG. 3, a switching system has an upper control unit 170 for controlling the entire switching system and individual processors for providing individual services (for example, common line control, circuit switching, call processing control, cell switching, etc.). Functional blocks 190 having
And a system bus 180 that connects the higher-level control unit 170 and each functional block 190.

As shown in FIG. 4, each functional block 190 includes a higher-level interface circuit 200 serving as information transmission means between the higher-level control unit and each functional block 190, and a functional block realizing different functions for each functional block 190. Individual circuit 240 and upper interface circuit 2
00 and a processor bus 230 for connecting the functional block individual circuit 240. Processor bus 23
The processor 22 that controls each functional block 190 is set to 0.
0 and an RO for storing processor firmware in which software for determining the operation of the processor 220 is stored.
M210 and RAM used as work memory, etc.
250 are connected.

In the above configuration, the function block 190
Performs a service specific to the functional block 190 according to a command from the higher-level control unit 170 based on the content stored in the ROM 210 for storing processor firmware.
The status is returned to the upper control unit 170. Also,
Commands between the function block 190 and the higher-level control unit 170
The exchange of status is performed via the system bus 180 and the upper interface circuit 200.

[0005] In the switching system configured as described above, the upper control unit 1 is controlled by the processor 220 individually provided in each of the plurality of function blocks 190.
70, and controls the operation of each functional block 190, and taking communication history is not particularly considered. When the communication history is obtained, a function of collecting the running history of the processor 220 is provided, and the communication history is obtained from the content of the running history. In this case, processor 2
When performing an exchange operation in which the load applied to the processor 20 is large, the running history of the processor 220 increases, making it difficult to collect, and the communication history based on this becomes inaccurate.

[0006]

However, the above-mentioned conventional switching system has the following problems.

(1) Since there is no function to collect the running history of the processor immediately before the occurrence of the fault, it is difficult to analyze the fault after the fault occurs, which hinders the improvement of the system performance.

(2) Even if the function of collecting the traveling history is provided in the processor, it may not be possible to accurately collect the traveling history in an operation state in which the load on the processor increases. In such a case, it becomes difficult to analyze a fault that has occurred during operation, which hinders improvement in system performance.

(3) Since each function block has only one processor for communicating with the higher-level control unit, if a failure occurs in the processor, the function block provided with the processor fails. State. The host controller cannot recognize the occurrence of this failure,
A lot of time is spent before recovery, and of course important information cannot be sent or received.

(4) Since each function block is connected to another function block or a higher-level control unit by a system bus, if a failure occurs in a processor in the function block, other functions connected by the system bus May adversely affect blocks.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned various problems of the prior art, and is capable of constantly collecting the running history of the main processor. In addition to being able to perform failure analysis, it can provide the minimum failure processing and service of a functional block even in the event of a failure, and prevent the occurrence of disturbance in other functional blocks due to the failure of its own device. It is an object of the present invention to provide an exchange system capable of collecting trouble information.

[0012]

A high-level control unit for controlling the entire switching system, a plurality of function blocks having individual processors for providing individual services, and a system for connecting the high-level control unit and the function blocks An exchange system capable of collecting fault information composed of a bus and
Each of the plurality of functional blocks includes a higher-level interface circuit serving as information transmission means between a higher-level control unit and each functional block, a functional block individual circuit that realizes the function of each functional block, and a functional block individual circuit and a functional block individual function block. A main processor system bus and a sub-processor system bus that independently connect the circuits, a main processor that controls the functional block individual circuit in response to a control message from the higher-level control unit, and a running history of the main processor. A sub-processor to collect, a dual-port memory for storing messages from the higher-level control unit and work data and running history of the main processor, and a failure-time trace information storage unit that operates under the control of the sub-processor. , Always monitor the operation of the main processor,
A peripheral circuit for running history tracing that notifies the sub-processor when a failure occurs in the main processor, a main processor firmware storage section in which software for determining the operation of the main processor is stored, and an operation of the sub-processor is determined. A main processor and a main processor firmware storage unit, the main processor and the main processor firmware storage unit each including at least a sub processor firmware storage unit storing software to be executed and a sub processor work memory storing work data of the sub processor. The sub-processor, the sub-processor firmware storage unit, the sub-processor work memory, and the fault trace information storage unit are interconnected by a sub-processor bus. Port memo Is connected to both the main processor bus and the sub-processor bus and is configured to be accessible from any bus.The sub-processor is notified from the traveling history tracing peripheral circuit that a fault has occurred in the main processor. Then, the collected traveling history is stored in the failure trace information storage unit.

Further, when a failure occurs in the main processor, the sub-processor blocks a line of the main processor and communicates important information with a higher-level control unit.

[0014]

In the present invention configured as described above, in addition to the main processor, a sub-processor for collecting the running history of the main processor is provided, and a main processor bus and a sub-processor bus are provided accordingly. ing.

When a failure occurs in the main processor, the sub-processor stores the collected traveling history in the failure-time trace information storage section connected to the sub-processor bus, so that the traveling history is collected and stored in the main processor. It is performed irrespective of the degree of failure that has occurred.

In the case where the main processor system line is closed when a failure occurs in the main processor and important information is communicated with the upper control unit, communication of the important information is minimized by performing communication of the important information. Service can be continued. Further, by blocking the line of the main processor system, there is no possibility that the main processor in the faulted state disturbs other function blocks.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an exchange system capable of collecting fault information according to the present invention. FIG. 2 is a block diagram showing an embodiment in a functional block 30 constituting a switching system capable of collecting fault information according to the present invention.

The switching system in this embodiment is composed of two switching systems. Each switching system provides an upper control unit 10 for controlling the entire switching system and individual services as shown in FIG. A plurality of functional blocks 30 each having an individual processor
System bus 20 for connecting the power supply and each functional block 30
And a bus crossing circuit 40 that connects the system buses 20 of each switching system.

As shown in FIG. 2, each function block 30 includes a higher-level interface circuit 50 serving as an information transmission means between the higher-level control unit 10 (see FIG. 1) and each function block 30.
And a functional block individual circuit 90 for realizing the function of each functional block 30, and a main processor bus 80 and a sub processor bus 120 for independently connecting the upper interface circuit 50 and the functional block individual circuit 90, respectively. .

The main processor bus 80 is connected to a main processor 70 for controlling each function block 30 and a main processor firmware storage ROM 60 as a main processor firmware storage unit.
0 contains the sub-processor 130 and the sub-processor firmware storage R
An OM 140, a sub-processor work memory 150,
A failure trace information storage EEPROM, which is a failure trace information storage unit, is connected. Further, the peripheral circuit 100 for tracing the traveling history and the dual port memory 1
10 is a main processor bus 80 and a sub processor bus 1
20 are connected to both.

The main processor 70 controls each functional block 30.

The sub processor 130 is a main processor 70
Is collected in the dual port memory 110, and when a failure occurs in the main processor 70, the line is closed, and only important information is communicated with the upper control unit 10 shown in FIG.

The dual port memory 110 is configured to be accessible from any of the main processor bus 80 and the sub processor bus 120, and stores the running history and control data of the main processor 70.

ROM for storing main processor firmware
The software for determining the operation of the main processor 70 is stored in R 60 for storing the sub processor firmware.
The OM 140 stores software that determines the operation of the sub-processor 130.

The sub-processor work memory 150 includes:
The work data of the sub-processor 130 is stored.

The traveling history tracing peripheral circuit 100 monitors the operation of the main processor 90 and notifies the sub-processor 130 of the occurrence of a failure when a failure occurs. EEP for storing trace information at the time of failure, which is a trace information storage unit at the time of failure
When a failure occurs in the main processor 70, the ROM 160 stores a running history of the main processor 70 at that time.

Next, a description will be given of a processing procedure of the failure information collecting method according to the present embodiment.

During normal operation, the sub-processor 130
While confirming the normal operation of the main processor 70 by the traveling history tracing peripheral circuit 100, the traveling history of the main processor 70 is collected and stored in the dual port memory 110.

The traveling history tracing peripheral circuit 100 constantly monitors the operation of the main processor 70, so that the main processor 70 is controlled by the host controller or the opposing device (if any).
When the main processor 70 becomes unable to communicate with the main processor 70 or runs out of control, the sub processor 130 is immediately notified of the occurrence of a fault by causing an interrupt to the sub processor 130.

Upon receiving the notification from the traveling history tracing peripheral circuit 100, the sub-processor 130 reads out the traveling history of the main processor 70 and the contents of the control memory in the functional block 30 written in the dual port memory 110. The running history of the main processor 70 is an EEPR for storing trace information at the time of failure, which is a trace information storage unit at the time of failure.
The OM 160 transfers the control memory in the function block 30 to the sub-processor work memory 150.

Here, the dual port memory 110 is
It can be accessed from any of the main processor bus 80 and the sub processor bus 120. Therefore, data and memory contents in the dual-port memory 110 can be read from the sub-processor bus 120 without obtaining the access right to the main processor bus 80. Therefore, regardless of the level of the failure that has occurred in the main processor 70, the data can be surely obtained. The running history of the main processor 70 is collected and stored.

Further, since the sub-processor 130 collects the running history of the main processor 70 as described above, the running history can be accurately collected even when the main processor 70 is performing a normal operation.

Further, the sub-processor 130 notifies the opposing device and the connected functional block of its own device failure, and prevents the main processor 70 in the failed state from causing disturbance to other functional blocks. However, sub processor 1
By 30, only transmission and reception of important information is performed and communication is enabled.

The prevention of disturbance to other function blocks in the present embodiment is performed by blocking the line of the main processor system in the self-function block 30. In the faulty function block whose line is blocked and separated from other function blocks, an EEPROM 16 for storing trace information at the time of a fault is stored.
Even if the traveling history information of the main processor 70 transferred to 0 is rewritten or erased by the main processor 70 in the failure state, or even if the power is turned off, the information effective for failure analysis is Since it will not be erased,
Even after the functional block 30 is replaced, the failure information can be read by another means (such as mounting on another failure analysis system).

Conventionally, when a failure occurs in the main processor 70, a non-response state continues for an access from a host, and the failure of the functional block 30 is detected only by the length of time of the non-response state. However, in this embodiment, since the communication with the higher-level control unit 10 is possible by the sub-processor bus 130 and the higher-level interface circuit 50,
It is possible to notify the host controller 10 of the failure promptly, and it is possible to minimize the influence on the other function blocks due to the failure of the system and the time until recovery.

[0037]

Since the present invention is constructed as described above, it has the following effects.

According to the first aspect of the present invention, the function block includes a sub-processor for collecting the running history of the main processor and a plurality of buses, and a dual-port memory accessible from the plurality of buses. With this arrangement, the running history of the main processor can always be accurately collected, the failure after the occurrence of the functional block failure can be analyzed, and effective data can be provided to improve the performance of the system.

According to the second aspect of the present invention, when a failure occurs in the main processor, the sub-processor provided in the function block blocks the line of the main processor system of the own function block, thereby enabling other functions to be performed. There is an effect that it is possible to prevent occurrence of disturbance to the block.

Further, even if the line is blocked, only the transmission and reception of important information such as the reception of fault information from other devices is enabled and communication is possible. This has the effect of shortening the time required to provide the service for important information.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of an exchange system capable of collecting fault information according to the present invention.

FIG. 2 is a block diagram showing one embodiment of functional blocks constituting a switching system capable of collecting fault information according to the present invention.

FIG. 3 is a block diagram illustrating a configuration example of a conventional switching system including a plurality of functional blocks.

FIG. 4 is a diagram showing an example of a configuration in each functional block of a conventional switching system.

[Explanation of symbols]

 REFERENCE SIGNS LIST 10 upper control unit 20 system bus 30 functional block 40 bus crossing circuit 50 upper interface circuit 60 ROM for storing main processor firmware 70 main processor 80 main processor bus 90 individual functional block circuit 100 peripheral circuit for running history tracing 110 dual port memory 120 sub Processor bus 130 Secondary processor 140 Secondary processor firmware storage ROM 150 Secondary processor work memory 160 EEPROM for storing trace information at the time of failure

Claims (2)

(57) [Claims] 1. A high-level control unit for controlling the entire switching system, a plurality of function blocks having individual processors for providing individual services, and a system bus connecting the high-level control unit and the function blocks A switching system capable of collecting fault information, wherein each of the plurality of functional blocks includes a higher-level interface circuit serving as information transmission means between a higher-level control unit and each of the functional blocks, and a function of realizing the function of each of the functional blocks. A block individual circuit, a main processor system bus and a sub processor system bus for independently connecting the upper interface circuit and the function block individual circuit, and the function block individual circuit according to a control message from the upper control unit. A main processor for controlling, and a sub-processor for collecting a running history of the main processor. A dual-port memory for storing messages from the upper control unit, work data of the main processor, and a running history; a failure-time trace information storage unit that operates under the control of the sub-processor; and the main processor. A peripheral circuit for running history tracing that constantly monitors the operation of the main processor and notifies the sub-processor when a failure occurs in the main processor, and a main processor firmware storage unit that stores software for determining the operation of the main processor, A main processor and a main processor, comprising at least a sub-processor firmware storage unit in which software for determining the operation of the sub-processor is stored; and a sub-processor work memory in which work data of the sub-processor is stored. The firmware storage is the main processor The sub-processor, the sub-processor firmware storage unit, the sub-processor work memory, and the fault trace information storage unit are interconnected by a sub-processor bus, and are connected to each other by a sub-processor bus. The dual-port memory is connected to both the main processor bus and the sub-processor bus, and is configured to be accessible from any of the buses. Is notified, and the collected traveling history is stored in a failure-time trace information storage unit. 2. The switching system according to claim 1, wherein the sub-processor is adapted to communicate important information only in the sub-processor system when a main processor fails. An exchange system capable of collecting fault information, wherein the communication line is closed and transmission / reception with a higher-level control unit is performed.