KR930006861B1 - Input/output port faults process method - Google Patents
Input/output port faults process method Download PDFInfo
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- KR930006861B1 KR930006861B1 KR1019900022822A KR900022822A KR930006861B1 KR 930006861 B1 KR930006861 B1 KR 930006861B1 KR 1019900022822 A KR1019900022822 A KR 1019900022822A KR 900022822 A KR900022822 A KR 900022822A KR 930006861 B1 KR930006861 B1 KR 930006861B1
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- input
- port
- output
- mpma
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M3/00—Automatic or semi-automatic exchanges
- H04M3/22—Arrangements for supervision, monitoring or testing
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- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Debugging And Monitoring (AREA)
Abstract
Description
제1도는 본 발명이 적용되는 전전자 교환기의 구성도.1 is a block diagram of an electric electron exchanger to which the present invention is applied.
제2도는 본 발명에 의한 입출력 포트장애 처리방법의 흐름도.2 is a flow chart of the input / output port failure processing method according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : MPMA 2 : IOIA1: MPMA 2: IOIA
3 : CPU 4 : DPRAM3: CPU 4: DPRAM
5 : ROM 6 : RAM5: ROM 6: RAM
7 : 인터럽트 처리기 8 : SCC7: interrupt handler 8: SCC
9 : 입출력부9: input / output unit
본 발명은 전전자 교환기의 입출력 포트장애 처리방법에 관한 것이다.The present invention relates to a method for handling input / output port failure of an electronic switch.
전전자 교환기의 맨-머신 통신(Man-Machine Communition)을 위한 프로세서에 연결된 입출력장비 (CRT,PC,프린터등)들을 통하여 통신을 하게된다.It communicates through input / output equipment (CRT, PC, printer, etc.) connected to the processor for Man-Machine Communition of the electronic switchboard.
종래에는 입출력 장비들과 전자교환 시스팀과의 통신을 위한 정합에만 관심을 두었다. 그러나 전자교환 시스팀은 항상 정상상태로 일반 사용자에게 서비스를 해야하므로 입출력 포트도 항상 정상동작을 하여야하며 비정상인 것은 즉시 감지하여 수리하도록 알려줘야 하며, 또 중요한 정보를 비정상인 포트로 내보내서 유실되지 않도록 해야 하기 때문에, 입출력 포트의 상태(connect/disconnect,power on/off)를 검색하여 관리할 필요가 있다.In the prior art, attention was focused only on matching for communication between input and output devices and the electronic switching system. However, since the electronic exchange system should always service the general user in a normal state, I / O ports should always be in normal operation, and an abnormality should be detected and repaired immediately, and important information should be sent to the abnormal port to prevent loss. Therefore, it is necessary to search for and manage the state (connect / disconnect, power on / off) of the input / output port.
따라서 본 발명은 상기 필요성을 충족하기 위해 안출된 것으로서 초기상태의 입출력 포트의 상태를 검색하여 관라하다가 상태의 변동이 있을시 즉시 감지하여 처리할 수 있도록 하는 입출력 포트장애 처리방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide an input / output port failure processing method that can detect and handle an input / output port state of an initial state as soon as it is devised to satisfy the above needs, and when there is a state change. have.
상기 목적을 달성하기 위해 본 발명은 중앙처리장치와 DPRAM(Dual Port RAM)과 ROM과 RAM과 인터럽트 처리기와 입출력 장비제어기로 구성된 입출력 인터페이스 수단, 상기 입출력 인터페이스 수단에 연결된 주중앙처리장치 및 메모리 보드(MPMA), 및 상기 입출력 인터페이스 수단에 연결된 입출력 수단을 포함하여 구성된 전전자 교환기의 입출력 포트장애 처리방법에 있어서, 하드웨어 및 각종 관리 테이블을 초기화하고 입출력 포트의 초기상태를 점검하여 보고하는 제1단계, 정상 동작상태로 들어가는 제2단계, 및 장애 인터럽트가 발생하면 상기 입출력 포트의 장애인지 검색하여 통보하는 제3단계에 의해 수행하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides an input / output interface means composed of a central processing unit, a dual port RAM (DPRAM), a ROM, a RAM, an interrupt processor, and an input / output equipment controller, a main central processing unit and a memory board connected to the input / output interface means ( MPMA), and an input / output port failure processing method of an all-electronic switch including the input / output means connected to the input / output interface means, the first step of initializing hardware and various management tables and checking and reporting the initial state of the input / output port, And performing a second step of entering a normal operation state and a third step of searching for and notifying the failure of the input / output port when a fault interrupt occurs.
이하, 첨부된 도면을 참조하여 본 발명의 일실시예를 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
제1도는 본 발명이 적용된 전전자 교환기의 구성도로, 1은 MPMA, 2는 IOIA, 3은 CPU, 4는 DPRAM, 5는 ROM, 6은 RAM, 7 은 인터럽트 처리기, 8은 SCC, 9는 입출력부, 10은 RS-232C선로를 각각 나타낸다.1 is a schematic diagram of an electronic switching system to which the present invention is applied, 1 is MPMA, 2 is IOIA, 3 is CPU, 4 is DPRAM, 5 is ROM, 6 is RAM, 7 is Interrupt handler, 8 is SCC, and 9 is I / O. 10 denotes RS-232C lines.
본 발명이 적용되는 전전자 교환기는 제1도에 도시한 바와같이 메인 CPU 및 메모리 보드(이하, MPMA라 한다)(1)와 입출력 인터페이스 보드(이하, IOIA라 한다)(2) 및 입출력부(9)등으로 구성되어 있다.The electronic switch to which the present invention is applied has a main CPU and a memory board (hereinafter referred to as MPMA) 1, an input / output interface board (hereinafter referred to as IOIA) 2 and an input / output section (shown in FIG. 1). 9) and so on.
IOIA(2)는 중앙처리장치(이하, CPU라 한다)(3), 메인 CPU와 로컬(local)CPU 양쪽에서 억세스할 수 있는 DPRAM(Dual Port RAM)(4), ROM(5), RAM(6), 인터럽트 처리기(7), 입출력 장비 제어기(이하 SCC라 한다)(8)로 구성되어 있으며, 상기 IOIA(2)에 입출력 장비(9)가 연결되어 있다.IOIA 2 is a central processing unit (hereinafter referred to as CPU) 3, DPRAM (Dual Port RAM) 4, which is accessible from both main CPU and local CPU, ROM 5, RAM ( 6), an interrupt processor 7 and an input / output device controller (hereinafter referred to as SCC) 8, and an input / output device 9 is connected to the IOIA 2.
IOIA(2)에서는 CPU(3)가 SCC(8)의 레지스터 내용을 읽어보면 그때의 입출력 포트상태를 알 수 있고, 입출력 포트의 상태가 변동될 때는 입출력 장비(9)에 연결된 RS-232C 선로(10)의 DTR 신호에 변동이 생겨서 SCC(8)의 DCD 신호입력단에 입력되어 CPU(3) 쪽으로 인터럽트를 걸게된다.In IOIA 2, when CPU 3 reads the register contents of SCC 8, the I / O port state at that time can be known, and when the state of the I / O port is changed, RS-232C line 10 connected to I / O device 9 A change occurs in the DTR signal, which is inputted to the DCD signal input terminal of the SCC 8 to interrupt the CPU 3.
제2도는 본 발명에 의한 포트의 장애 처리방법의 흐름도이다.2 is a flowchart of a method for handling a failure of a port according to the present invention.
입출력 인터페이스 보드의 동작을 시작하면 우선 각종 하드웨어 및 관리 테이블들을 초기화하고(21), SCC의 레지스터를 읽어서 포트상태를 점검하여, 그 상태를 DPRAM의 특정 영역에 기록해 놓고(22), MPMA로 인터럽트를 걸어서 상태를 보고한 후(23), 정상 동작상태로 들어간다(24).When the operation of the I / O interface board starts, the various hardware and management tables are initialized (21), the port status is checked by reading the registers of the SCC, the state is recorded in a specific area of the DPRAM (22), and the interrupt is performed by the MPMA. After reporting the condition on foot (23), it enters the normal operating state (24).
정상 동작중 장애 인터럽트가 발생하면(25), 입출력 포트장애인가를 조사하여(26), 아니면 그 상태를 MPMA로 통보하고(29), 정상 동작상태로 들어간다. 입출력 포트의 장애이면 포트 상태를 점검하여(27) 그 상태를 특정영역에 기록해 두고 MPMA로 인터럽트를 걸어 통보하고(28) 정상 동작상태로 들어간다.If a fault interrupt occurs during normal operation (25), it checks whether the input / output port failure (26), or notifies the MPMA of the state (29), and enters the normal operation state. If the input / output port is faulty, the port state is checked (27), the state is recorded in a specific area, an interrupt is notified to the MPMA (28), and the normal operation state is entered.
상기와 같이 구성되어 작동하는 본 발명은 전전자 교환기의 MMC 프로세서에서 입출력 포트의 장애상태를 즉시 감지하여, 장애요소를 수리하도록 알려주고 중요한 정보를 장애가 있는 포트로 내보내지 않도록 하는 효과가 있다.The present invention configured and operated as described above has an effect of immediately detecting a failure state of an input / output port in an MMC processor of an electronic switchboard, informing a repair of a failure element, and not exporting important information to a failed port.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900022822A KR930006861B1 (en) | 1990-12-31 | 1990-12-31 | Input/output port faults process method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900022822A KR930006861B1 (en) | 1990-12-31 | 1990-12-31 | Input/output port faults process method |
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| Publication Number | Publication Date |
|---|---|
| KR920014062A KR920014062A (en) | 1992-07-30 |
| KR930006861B1 true KR930006861B1 (en) | 1993-07-24 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019900022822A KR930006861B1 (en) | 1990-12-31 | 1990-12-31 | Input/output port faults process method |
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| KR (1) | KR930006861B1 (en) |
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| KR920014062A (en) | 1992-07-30 |
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