KR0123258B1 - Testing jig-board for basic speed matching circuit - Google Patents

Abstract

There is provided a jig board for testing a base speed matching circuit board. The jig board includes: a clock generating means for generating a first clock signal and a second clock signal which is PCM highway clock and is necessary for both of external IBQA and a cross point switch(22) and supplying the first clock signal to a microprocessor(21); a neighboring circuit part(27) connected to the microprocessor(21) and a ROM(26); a common memory(24) which is accessible by external IDPA and the microprocessor(21) and receives and transmits data; and an external test path reading buffer(25) for determining an operation state of test relay of the IBQA.

Description

Basic Speed Matching Circuit Board Test Jig Board

1 is a test jig configuration to which the present invention is applied.

2 is a block diagram of a test jig board according to the present invention.

* Explanation of symbols for main parts of the drawings

21 microprocessor 22 crosspoint switch

23: clock generation circuit section 24: common memory

25: External test path read buffer 26: ROM

27: peripheral circuit

The present invention relates to a basic speed matching circuit board test jig board.

ISB Basic IBSQA (ISDN Basic access 2BIQ Board Assembly), which is a basic speed matching circuit board among subscriber matching devices of an electronic information exchange (ISDN) electronic switch, enters the commercialization stage, and is tested to check whether there is an abnormality in the basic speed subscriber matching circuit board. A device was required and a device for diagnosing the board in the event of a malfunction was required.

In order to meet the above requirements, the present invention transmits the 'B' channel to the IBQA and the PCM highway, and determines whether an error of the LT (Line Control) or NT (Network Termination Device) loopback data is determined according to the control of the upper board. The purpose is to provide a basic speed matching circuit board test jig board to easily test the function of.

In order to achieve the above object, the present invention, a ROM (Read Only Memory) for mounting a program to be performed: a microprocessor for controlling each function block in accordance with the program embedded in the ROM: by generating a click using an oscillator Click generation means that provides the necessary clicks on the processor and generates and supplies the PCM highway click and synchronization signals required by external IBQAs and cross-point switches to be described later: Connected to the microprocessor and ROM and supporting operation with external circuits. Peripheral circuit unit: A common memory that allows the IDPA (ISDN D channel Control Processor Board Assembly) and the microprocessor to access and exchange data by jointly accessing the data: Data transmitted by multiplexing to the corresponding channel of the PCM highway in the IBQA. Receive and demultiplex it to remind And a cross point switch for reading a microprocessor and multiplexing the data written by the microprocessor on a PCM highway to the IBQA; and an external test path read buffer for checking a test relay driving state of the IBQA.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a test jig configuration to which the present invention is applied, and NT is connected to IBQA to perform a function such as NT loopback, and CRT is connected to IDPA to perform a test and observe the result.

IDPA controls the IBQA and BSIJ (Basic Access Subscriber Interface Test Jig Board Assembly) according to the embedded program to perform test procedures and output the results to the CRT. The PBU-C is a DC / DC converter, supplied with -48V to supply the power required for this unit.

2 is an internal configuration diagram of the BSIJ according to the present invention, in which 21 is a microprocessor, 22 is a cross point switch, 23 is a clock generation circuit part, 24 is a common memory, 25 is an external test path read buffer, 26 is ROM, and 27 is Each peripheral circuit part is shown.

Referring to the configuration shown in the drawings for each function as follows.

First, the clock generation circuit unit 23 generates a clock using an oscillator to provide a CPU clock required by the microprocessor 21, and generates and supplies a PCM highway clock and a synchronization signal required by the IBQA and the cross point switch 22. do.

ROM (Read Only Memory) 26 reads and writes the main elements required for operation of the present invention, reads and writes common memory 24 for communication with IDPA, and writes and reads 'B' channel data to and from crosspoint switch 22. Load a program that performs external test path reading.

The peripheral circuit unit 27 is composed of a processor reset circuit, an interface circuit for serial communication with an external CRT, an address decoder, an LC bus interface, and the like so that the processor can easily operate with an external circuit.

The LC bus interface (not shown) matches the address assigned to its slot on the backboard and sends a response signal (/ DTACK) to allow access to its common memory.

The common memory 24 comprises two DPRAMs having two port pairs (Dual Port), one for odd addresses and the other for even addresses, so that IDPA and the microprocessor 21 of the present invention This memory is commonly accessed to exchange data. If the upper board and its own microprocessor 21 simultaneously access the same address, it accesses a little bit too late and transmits the busy signal and transmits the response signal when the peripheral circuit is on the LC bus side. In the case of the processor 21, a wait signal / WAIT is generated to prevent an error due to mutual collision.

The cross-point switch 22 receives data transmitted by multiplexing to the corresponding channel of the PCM highway in IBQA, demultiplexes it to be read by the microprocessor, and multiplexes the data written by the microprocessor 21 to the PCM highway to IBQA. Send.

The external test path read buffer 25 is for checking the test relay driving state of the IBQA and is connected to the external test path. When the external test path is set, the external test path is opened as '0' and is designated as '1'.

The microprocessor 21 controls all the circuits in accordance with the program embedded in the ROM.

The present invention as described above allows to configure the PCM highway required in the basic speed matching circuit board jig, and under the control of IDPA transmits 'B' channel data to the IBQA to determine the data error at the time of LT or NT loopback, It can be used to carry out automated tests, such as checking external test path settings.

Claims (1)

ROM (Read Only Memory) 26 for mounting a program to be performed: Microprocessor 21 for controlling each function block according to a program embedded in the ROM 26: A microprocessor by generating a clock using an oscillator Clock generation means 23 which provides the necessary clock in 21 and generates and supplies the required PCM highway clock and synchronization signal from an external IBQA (ISDN Basic Access 2BIQ Board Assembly) and the cross point switch 22 to be described later: Peripheral circuitry 27 connected to the microprocessor 21 and the ROM 26 and capable of operating with an external circuit: an external ISDN D channel control processor board assembly (IDPA) and the microprocessor 21 jointly The common memory 24 which accesses and exchanges data by using this memory: receives data transmitted by multiplexing to the corresponding channel of the PCM highway in the IBQA. Demultiplexing so that the microprocessor 21 can read and cross-point switch 22 for multiplexing the data written by the microprocessor 21 to the PCM highway to the IBQA, and the test relay driving state of the IBQA. A basic speed match circuit board task jig board, comprising: an external test path read buffer 25 for verifying.