JPWO2023276734A1 - - Google Patents
Info
- Publication number
- JPWO2023276734A1 JPWO2023276734A1 JP2023531803A JP2023531803A JPWO2023276734A1 JP WO2023276734 A1 JPWO2023276734 A1 JP WO2023276734A1 JP 2023531803 A JP2023531803 A JP 2023531803A JP 2023531803 A JP2023531803 A JP 2023531803A JP WO2023276734 A1 JPWO2023276734 A1 JP WO2023276734A1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
- H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
- H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
- H03K3/0377—Bistables with hysteresis, e.g. Schmitt trigger
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- General Physics & Mathematics (AREA)
- Electronic Switches (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2021107097 | 2021-06-28 | ||
| PCT/JP2022/024377 WO2023276734A1 (ja) | 2021-06-28 | 2022-06-17 | パワーオンリセット回路および半導体装置 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPWO2023276734A1 true JPWO2023276734A1 (https=) | 2023-01-05 |
Family
ID=84692365
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2023531803A Pending JPWO2023276734A1 (https=) | 2021-06-28 | 2022-06-17 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US12463636B2 (https=) |
| JP (1) | JPWO2023276734A1 (https=) |
| WO (1) | WO2023276734A1 (https=) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5781644A (en) * | 1980-11-07 | 1982-05-21 | Matsushita Electric Ind Co Ltd | Coincidence detecting circuit |
| JPS60189029A (ja) * | 1984-03-08 | 1985-09-26 | Rohm Co Ltd | 電源オンリセツト回路 |
| JPH01225222A (ja) * | 1988-03-04 | 1989-09-08 | Nec Corp | パワーオンリセツト回路 |
| JPH04162820A (ja) * | 1990-10-26 | 1992-06-08 | Nec Corp | 電源投入リセット回路 |
| JPH04347925A (ja) * | 1991-05-24 | 1992-12-03 | Nec Corp | パワーオンリセット回路 |
| JPH05160684A (ja) * | 1991-12-06 | 1993-06-25 | Matsushita Electric Ind Co Ltd | ラッチ回路 |
| JPH07239348A (ja) * | 1994-02-28 | 1995-09-12 | Fujitsu Ltd | パワーオンリセット回路及び電源電圧検出回路 |
| JP2006005459A (ja) * | 2004-06-15 | 2006-01-05 | Fujitsu Ltd | リセット回路 |
| JP2007282095A (ja) * | 2006-04-11 | 2007-10-25 | Elpida Memory Inc | フリップフロップを用いたパワーオンリセット回路、及びこれを備えた半導体装置 |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005210474A (ja) * | 2004-01-23 | 2005-08-04 | Matsushita Electric Ind Co Ltd | ロジック出力確定回路 |
| US8421502B2 (en) * | 2005-11-10 | 2013-04-16 | Intel Corporation | Power reducing logic and non-destructive latch circuits and applications |
| JP6205163B2 (ja) | 2013-04-15 | 2017-09-27 | ラピスセミコンダクタ株式会社 | 半導体装置 |
| DE102016102696A1 (de) * | 2016-02-16 | 2017-08-17 | Infineon Technologies Ag | Vorrichtung und Verfahren zur internen Resetsignalerzeugung |
-
2022
- 2022-06-17 WO PCT/JP2022/024377 patent/WO2023276734A1/ja not_active Ceased
- 2022-06-17 JP JP2023531803A patent/JPWO2023276734A1/ja active Pending
-
2023
- 2023-12-26 US US18/396,131 patent/US12463636B2/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5781644A (en) * | 1980-11-07 | 1982-05-21 | Matsushita Electric Ind Co Ltd | Coincidence detecting circuit |
| JPS60189029A (ja) * | 1984-03-08 | 1985-09-26 | Rohm Co Ltd | 電源オンリセツト回路 |
| JPH01225222A (ja) * | 1988-03-04 | 1989-09-08 | Nec Corp | パワーオンリセツト回路 |
| JPH04162820A (ja) * | 1990-10-26 | 1992-06-08 | Nec Corp | 電源投入リセット回路 |
| JPH04347925A (ja) * | 1991-05-24 | 1992-12-03 | Nec Corp | パワーオンリセット回路 |
| JPH05160684A (ja) * | 1991-12-06 | 1993-06-25 | Matsushita Electric Ind Co Ltd | ラッチ回路 |
| JPH07239348A (ja) * | 1994-02-28 | 1995-09-12 | Fujitsu Ltd | パワーオンリセット回路及び電源電圧検出回路 |
| JP2006005459A (ja) * | 2004-06-15 | 2006-01-05 | Fujitsu Ltd | リセット回路 |
| JP2007282095A (ja) * | 2006-04-11 | 2007-10-25 | Elpida Memory Inc | フリップフロップを用いたパワーオンリセット回路、及びこれを備えた半導体装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| US12463636B2 (en) | 2025-11-04 |
| US20240128969A1 (en) | 2024-04-18 |
| WO2023276734A1 (ja) | 2023-01-05 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20250610 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20260106 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20260302 |