JPWO2023234023A1 - - Google Patents

Info

Publication number
JPWO2023234023A1
JPWO2023234023A1 JP2024524323A JP2024524323A JPWO2023234023A1 JP WO2023234023 A1 JPWO2023234023 A1 JP WO2023234023A1 JP 2024524323 A JP2024524323 A JP 2024524323A JP 2024524323 A JP2024524323 A JP 2024524323A JP WO2023234023 A1 JPWO2023234023 A1 JP WO2023234023A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2024524323A
Other languages
Japanese (ja)
Other versions
JPWO2023234023A5 (https=
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPWO2023234023A1 publication Critical patent/JPWO2023234023A1/ja
Publication of JPWO2023234023A5 publication Critical patent/JPWO2023234023A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
JP2024524323A 2022-06-01 2023-05-17 Pending JPWO2023234023A1 (https=)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2022089630 2022-06-01
PCT/JP2023/018392 WO2023234023A1 (ja) 2022-06-01 2023-05-17 積層基板

Publications (2)

Publication Number Publication Date
JPWO2023234023A1 true JPWO2023234023A1 (https=) 2023-12-07
JPWO2023234023A5 JPWO2023234023A5 (https=) 2025-01-31

Family

ID=89026526

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2024524323A Pending JPWO2023234023A1 (https=) 2022-06-01 2023-05-17

Country Status (4)

Country Link
US (1) US20250087568A1 (https=)
JP (1) JPWO2023234023A1 (https=)
CN (1) CN119156895A (https=)
WO (1) WO2023234023A1 (https=)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010098291A (ja) * 2008-10-17 2010-04-30 Samsung Electro-Mechanics Co Ltd 無収縮セラミック基板及び無収縮セラミック基板の製造方法
JP2010232596A (ja) * 2009-03-30 2010-10-14 Murata Mfg Co Ltd 多層配線基板の製造方法および多層配線基板
JP2014160705A (ja) * 2013-02-19 2014-09-04 Kyocera Corp 配線基板、これを用いた実装構造体、これを用いた電子装置および配線基板の製造方法
WO2017150611A1 (ja) * 2016-03-02 2017-09-08 株式会社村田製作所 モジュール部品、モジュール部品の製造方法、及び多層基板
WO2019003729A1 (ja) * 2017-06-26 2019-01-03 株式会社村田製作所 多層配線基板、及び、多層配線基板の製造方法
WO2021084860A1 (ja) * 2019-10-30 2021-05-06 京セラ株式会社 配線基板

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010098291A (ja) * 2008-10-17 2010-04-30 Samsung Electro-Mechanics Co Ltd 無収縮セラミック基板及び無収縮セラミック基板の製造方法
JP2010232596A (ja) * 2009-03-30 2010-10-14 Murata Mfg Co Ltd 多層配線基板の製造方法および多層配線基板
JP2014160705A (ja) * 2013-02-19 2014-09-04 Kyocera Corp 配線基板、これを用いた実装構造体、これを用いた電子装置および配線基板の製造方法
WO2017150611A1 (ja) * 2016-03-02 2017-09-08 株式会社村田製作所 モジュール部品、モジュール部品の製造方法、及び多層基板
WO2019003729A1 (ja) * 2017-06-26 2019-01-03 株式会社村田製作所 多層配線基板、及び、多層配線基板の製造方法
WO2021084860A1 (ja) * 2019-10-30 2021-05-06 京セラ株式会社 配線基板

Also Published As

Publication number Publication date
WO2023234023A1 (ja) 2023-12-07
CN119156895A (zh) 2024-12-17
US20250087568A1 (en) 2025-03-13

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