JPWO2023112677A1 - - Google Patents

Info

Publication number
JPWO2023112677A1
JPWO2023112677A1 JP2023567670A JP2023567670A JPWO2023112677A1 JP WO2023112677 A1 JPWO2023112677 A1 JP WO2023112677A1 JP 2023567670 A JP2023567670 A JP 2023567670A JP 2023567670 A JP2023567670 A JP 2023567670A JP WO2023112677 A1 JPWO2023112677 A1 JP WO2023112677A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2023567670A
Other languages
Japanese (ja)
Other versions
JPWO2023112677A5 (https=
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPWO2023112677A1 publication Critical patent/JPWO2023112677A1/ja
Publication of JPWO2023112677A5 publication Critical patent/JPWO2023112677A5/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00Cutting or separating of wafers, substrates or parts of devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40Leadframes
    • H10W70/464Additional interconnections in combination with leadframes
    • H10W70/468Circuit boards
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01Manufacture or treatment
    • H10W70/04Manufacture or treatment of leadframes
    • H10W70/048Mechanical treatments, e.g. punching, cutting, deforming or cold welding
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/01Manufacture or treatment
    • H10W74/016Manufacture or treatment using moulds
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/726Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
JP2023567670A 2021-12-13 2022-11-30 Pending JPWO2023112677A1 (https=)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2021201802 2021-12-13
PCT/JP2022/044165 WO2023112677A1 (ja) 2021-12-13 2022-11-30 半導体装置および半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPWO2023112677A1 true JPWO2023112677A1 (https=) 2023-06-22
JPWO2023112677A5 JPWO2023112677A5 (https=) 2024-08-26

Family

ID=86774201

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023567670A Pending JPWO2023112677A1 (https=) 2021-12-13 2022-11-30

Country Status (5)

Country Link
US (1) US20240312878A1 (https=)
JP (1) JPWO2023112677A1 (https=)
CN (1) CN118541798A (https=)
DE (1) DE112022005438T5 (https=)
WO (1) WO2023112677A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2025047268A1 (ja) * 2023-08-25 2025-03-06 ローム株式会社 半導体装置
CN118380338A (zh) * 2024-04-26 2024-07-23 强茂电子(无锡)有限公司 一种无引脚半导体封装器件的制作方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10366948B2 (en) * 2016-03-17 2019-07-30 Rohm Co., Ltd. Semiconductor device and method for manufacturing the same
JP2018085487A (ja) * 2016-11-25 2018-05-31 マクセルホールディングス株式会社 半導体装置の製造方法および半導体装置
JP6909629B2 (ja) 2017-05-10 2021-07-28 ローム株式会社 半導体装置
JP2021027211A (ja) * 2019-08-07 2021-02-22 ローム株式会社 電子装置
JP2021158317A (ja) * 2020-03-30 2021-10-07 ローム株式会社 半導体装置

Also Published As

Publication number Publication date
WO2023112677A1 (ja) 2023-06-22
CN118541798A (zh) 2024-08-23
US20240312878A1 (en) 2024-09-19
DE112022005438T5 (de) 2024-08-29

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Legal Events

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