JPWO2023047461A5 - - Google Patents

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JPWO2023047461A5
JPWO2023047461A5 JP2023549195A JP2023549195A JPWO2023047461A5 JP WO2023047461 A5 JPWO2023047461 A5 JP WO2023047461A5 JP 2023549195 A JP2023549195 A JP 2023549195A JP 2023549195 A JP2023549195 A JP 2023549195A JP WO2023047461 A5 JPWO2023047461 A5 JP WO2023047461A5
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helical channel
insulator layer
hinged
region
groove
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JP7666617B2 (ja
JPWO2023047461A1 (https=
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JP2023549195A 2021-09-21 2021-09-21 量子ビット、量子演算装置及び量子ビットの製造方法 Active JP7666617B2 (ja)

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Application Number Priority Date Filing Date Title
PCT/JP2021/034578 WO2023047461A1 (ja) 2021-09-21 2021-09-21 量子ビット、量子演算装置及び量子ビットの製造方法

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JPWO2023047461A1 JPWO2023047461A1 (https=) 2023-03-30
JPWO2023047461A5 true JPWO2023047461A5 (https=) 2024-05-28
JP7666617B2 JP7666617B2 (ja) 2025-04-22

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JP (1) JP7666617B2 (https=)
WO (1) WO2023047461A1 (https=)

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JPWO2023181247A1 (https=) * 2022-03-24 2023-09-28

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102017002616A1 (de) * 2017-03-20 2018-09-20 Forschungszentrum Jülich GmbH Verfahren zur in-situ Herstellung von "Majorana-Materialien - Supraleiter" Hybridnetzwerken, sowie eine durch das Verfahren hergestellte Hybridstruktur
JP2020096107A (ja) * 2018-12-13 2020-06-18 株式会社日立製作所 量子ビット及びその制御方法

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