JPWO2022238798A1 - - Google Patents

Info

Publication number
JPWO2022238798A1
JPWO2022238798A1 JP2023520563A JP2023520563A JPWO2022238798A1 JP WO2022238798 A1 JPWO2022238798 A1 JP WO2022238798A1 JP 2023520563 A JP2023520563 A JP 2023520563A JP 2023520563 A JP2023520563 A JP 2023520563A JP WO2022238798 A1 JPWO2022238798 A1 JP WO2022238798A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2023520563A
Other languages
Japanese (ja)
Other versions
JPWO2022238798A5 (https=
JP7811940B2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPWO2022238798A1 publication Critical patent/JPWO2022238798A1/ja
Publication of JPWO2022238798A5 publication Critical patent/JPWO2022238798A5/ja
Application granted granted Critical
Publication of JP7811940B2 publication Critical patent/JP7811940B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/18—Peripheral circuit regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/33—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor extending under the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/26—Configurations of stacked chips the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)
JP2023520563A 2021-05-10 2022-04-26 半導体装置 Active JP7811940B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP2021079594 2021-05-10
JP2021079595 2021-05-10
JP2021079594 2021-05-10
JP2021079595 2021-05-10
PCT/IB2022/053840 WO2022238798A1 (ja) 2021-05-10 2022-04-26 半導体装置

Publications (3)

Publication Number Publication Date
JPWO2022238798A1 true JPWO2022238798A1 (https=) 2022-11-17
JPWO2022238798A5 JPWO2022238798A5 (https=) 2025-03-26
JP7811940B2 JP7811940B2 (ja) 2026-02-06

Family

ID=84029477

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023520563A Active JP7811940B2 (ja) 2021-05-10 2022-04-26 半導体装置

Country Status (4)

Country Link
US (1) US20240147708A1 (https=)
JP (1) JP7811940B2 (https=)
KR (1) KR20240006569A (https=)
WO (1) WO2022238798A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12608060B2 (en) * 2023-01-06 2026-04-21 Micron Technology, Inc. Power management and delivery for high bandwidth memory
KR20250163307A (ko) 2023-03-21 2025-11-20 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치, 기억 장치, 전자 기기, 및 처리 장치

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013131533A (ja) * 2011-12-20 2013-07-04 Elpida Memory Inc 半導体装置
JP2013138177A (ja) * 2011-11-28 2013-07-11 Elpida Memory Inc 半導体装置の製造方法
JP2013211091A (ja) * 2010-04-16 2013-10-10 Semiconductor Energy Lab Co Ltd 半導体装置
JP2019061677A (ja) * 2017-09-27 2019-04-18 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． 積層型メモリ装置及びその動作方法並びにメモリシステム

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1970952A3 (en) * 2007-03-13 2009-05-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
WO2011052488A1 (en) * 2009-10-30 2011-05-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2012256821A (ja) 2010-09-13 2012-12-27 Semiconductor Energy Lab Co Ltd 記憶装置
US8848464B2 (en) * 2011-04-29 2014-09-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of driving semiconductor device
US8709889B2 (en) * 2011-05-19 2014-04-29 Semiconductor Energy Laboratory Co., Ltd. Semiconductor memory device and manufacturing method thereof
KR102270823B1 (ko) * 2013-10-22 2021-06-30 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치와 그 제작 방법
US9953695B2 (en) * 2015-12-29 2018-04-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, electronic device, and semiconductor wafer
JP7202319B2 (ja) * 2018-01-25 2023-01-11 株式会社半導体エネルギー研究所 半導体材料、および半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013211091A (ja) * 2010-04-16 2013-10-10 Semiconductor Energy Lab Co Ltd 半導体装置
JP2013138177A (ja) * 2011-11-28 2013-07-11 Elpida Memory Inc 半導体装置の製造方法
JP2013131533A (ja) * 2011-12-20 2013-07-04 Elpida Memory Inc 半導体装置
JP2019061677A (ja) * 2017-09-27 2019-04-18 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． 積層型メモリ装置及びその動作方法並びにメモリシステム

Also Published As

Publication number Publication date
US20240147708A1 (en) 2024-05-02
JP7811940B2 (ja) 2026-02-06
KR20240006569A (ko) 2024-01-15
WO2022238798A1 (ja) 2022-11-17

Similar Documents

Publication Publication Date Title
BR112023005462A2 (https=)
BR112023012656A2 (https=)
BR112023009656A2 (https=)
BR112022009896A2 (https=)
JPWO2022238798A1 (https=)
BR112022024743A2 (https=)
BR112022026905A2 (https=)
BR112023011738A2 (https=)
BR112023004146A2 (https=)
BR112023006729A2 (https=)
BR102021018859A2 (https=)
BR102021015500A2 (https=)
BR112023016292A2 (https=)
BR112023011539A2 (https=)
BR112023011610A2 (https=)
BR112023008976A2 (https=)
BR102021020147A2 (https=)
BR102021018926A2 (https=)
BR102021018167A2 (https=)
BR102021017576A2 (https=)
BR102021016837A2 (https=)
BR102021016551A2 (https=)
BR102021016375A2 (https=)
BR102021016176A2 (https=)
BR102021016200A2 (https=)

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20250317

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20250317

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20260106

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20260127

R150 Certificate of patent or registration of utility model

Ref document number: 7811940

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150