JPWO2022029541A1 - - Google Patents

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Publication number
JPWO2022029541A1
JPWO2022029541A1 JP2022541320A JP2022541320A JPWO2022029541A1 JP WO2022029541 A1 JPWO2022029541 A1 JP WO2022029541A1 JP 2022541320 A JP2022541320 A JP 2022541320A JP 2022541320 A JP2022541320 A JP 2022541320A JP WO2022029541 A1 JPWO2022029541 A1 JP WO2022029541A1
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JP
Japan
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JP2022541320A
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Japanese (ja)
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JPWO2022029541A5 (https=
JP7689533B2 (ja
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Priority to JP2025088138A priority Critical patent/JP2025131644A/ja
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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443Sum of products
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06JHYBRID COMPUTING ARRANGEMENTS
    • G06J1/00Hybrid computing arrangements
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06JHYBRID COMPUTING ARRANGEMENTS
    • G06J1/00Hybrid computing arrangements
    • G06J1/005Hybrid computing arrangements for correlation; for convolution; for Z or Fourier Transform
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/04Architecture, e.g. interconnection topology
    • G06N3/0464Convolutional networks [CNN, ConvNet]
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065Analogue means
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/02Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6704Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/674Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6757Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85Complementary IGFETs, e.g. CMOS
    • H10D84/853Complementary IGFETs, e.g. CMOS comprising FinFETs
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802Special implementations
    • G06F2207/4814Non-logic devices, e.g. operational amplifiers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6729Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733Multi-gate TFTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/08Manufacture or treatment characterised by using material-based technologies using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00Three-dimensional [3D] integrated devices
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Biophysics (AREA)
  • Health & Medical Sciences (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Evolutionary Computation (AREA)
  • Artificial Intelligence (AREA)
  • Molecular Biology (AREA)
  • General Health & Medical Sciences (AREA)
  • Data Mining & Analysis (AREA)
  • Computational Linguistics (AREA)
  • Neurology (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Automation & Control Theory (AREA)
  • Fuzzy Systems (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Memory System (AREA)
  • Dram (AREA)
JP2022541320A 2020-08-03 2021-07-26 半導体装置 Active JP7689533B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2025088138A JP2025131644A (ja) 2020-08-03 2025-05-27 半導体装置

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2020131673 2020-08-03
JP2020131673 2020-08-03
PCT/IB2021/056692 WO2022029541A1 (ja) 2020-08-03 2021-07-26 半導体装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2025088138A Division JP2025131644A (ja) 2020-08-03 2025-05-27 半導体装置

Publications (3)

Publication Number Publication Date
JPWO2022029541A1 true JPWO2022029541A1 (https=) 2022-02-10
JPWO2022029541A5 JPWO2022029541A5 (https=) 2024-07-26
JP7689533B2 JP7689533B2 (ja) 2025-06-06

Family

ID=80117216

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2022541320A Active JP7689533B2 (ja) 2020-08-03 2021-07-26 半導体装置
JP2025088138A Pending JP2025131644A (ja) 2020-08-03 2025-05-27 半導体装置

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2025088138A Pending JP2025131644A (ja) 2020-08-03 2025-05-27 半導体装置

Country Status (5)

Country Link
US (1) US20230352477A1 (https=)
JP (2) JP7689533B2 (https=)
KR (1) KR20230047117A (https=)
CN (1) CN116097274A (https=)
WO (1) WO2022029541A1 (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7596386B2 (ja) 2020-08-03 2024-12-09 株式会社半導体エネルギー研究所 半導体装置、及び電子機器
JP7717080B2 (ja) * 2020-09-18 2025-08-01 株式会社半導体エネルギー研究所 半導体装置、および電子機器
US12481867B2 (en) * 2021-04-28 2025-11-25 Arm Limited Memory for artificial neural network accelerator
WO2023146567A1 (en) * 2022-01-28 2023-08-03 Silicon Storage Technology, Inc. Artificial neural network comprising an analog array and a digital array
US12530561B2 (en) 2022-01-28 2026-01-20 Silicon Storage Technology, Inc Artificial neural network comprising an analog array and a digital array
KR20250156740A (ko) * 2023-02-24 2025-11-03 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
WO2024176062A1 (ja) * 2023-02-24 2024-08-29 株式会社半導体エネルギー研究所 半導体装置
JPWO2024194749A1 (https=) * 2023-03-21 2024-09-26

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019036280A (ja) * 2017-08-11 2019-03-07 株式会社半導体エネルギー研究所 グラフィックスプロセッシングユニット、コンピュータ、電子機器及び並列計算機
JP2019057053A (ja) * 2017-09-20 2019-04-11 東芝メモリ株式会社 半導体記憶装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1125201A (ja) * 1997-07-02 1999-01-29 Tadahiro Omi 半導体集積回路
US9842842B2 (en) * 2014-03-19 2017-12-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor memory device and semiconductor device and electronic device having the same
JP2018129046A (ja) * 2017-02-08 2018-08-16 株式会社半導体エネルギー研究所 Aiシステム
JP2018133016A (ja) * 2017-02-17 2018-08-23 株式会社半導体エネルギー研究所 ニューラルネットワークシステム
JP6956784B2 (ja) * 2017-06-08 2021-11-02 株式会社半導体エネルギー研究所 撮像装置
US10796221B2 (en) 2017-10-19 2020-10-06 General Electric Company Deep learning architecture for automated image feature extraction
WO2020234681A1 (ja) * 2019-05-17 2020-11-26 株式会社半導体エネルギー研究所 半導体装置、及び電子機器
US12093808B2 (en) * 2020-12-09 2024-09-17 Arm Limited Mixed-signal artificial neural network accelerator

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019036280A (ja) * 2017-08-11 2019-03-07 株式会社半導体エネルギー研究所 グラフィックスプロセッシングユニット、コンピュータ、電子機器及び並列計算機
JP2019057053A (ja) * 2017-09-20 2019-04-11 東芝メモリ株式会社 半導体記憶装置

Also Published As

Publication number Publication date
JP2025131644A (ja) 2025-09-09
WO2022029541A1 (ja) 2022-02-10
CN116097274A (zh) 2023-05-09
US20230352477A1 (en) 2023-11-02
KR20230047117A (ko) 2023-04-06
JP7689533B2 (ja) 2025-06-06

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