JPWO2022018560A1 - - Google Patents

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Publication number
JPWO2022018560A1
JPWO2022018560A1 JP2022538485A JP2022538485A JPWO2022018560A1 JP WO2022018560 A1 JPWO2022018560 A1 JP WO2022018560A1 JP 2022538485 A JP2022538485 A JP 2022538485A JP 2022538485 A JP2022538485 A JP 2022538485A JP WO2022018560 A1 JPWO2022018560 A1 JP WO2022018560A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2022538485A
Other languages
Japanese (ja)
Other versions
JPWO2022018560A5 (enExample
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed filed Critical
Publication of JPWO2022018560A1 publication Critical patent/JPWO2022018560A1/ja
Publication of JPWO2022018560A5 publication Critical patent/JPWO2022018560A5/ja
Priority to JP2025062645A priority Critical patent/JP2025100591A/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356Bistable circuits
    • H03K3/356104Bistable circuits using complementary field-effect transistors
    • H03K3/356113Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H03K3/35613Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45Differential amplifiers
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45Differential amplifiers
    • H03F3/45071Differential amplifiers with semiconductor devices only
    • H03F3/45076Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183Long tailed pairs
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01Details
    • H03K3/012Modifications of generator to improve response time or to decrease power consumption
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356Bistable circuits
    • H03K3/356104Bistable circuits using complementary field-effect transistors
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01Shaping pulses
    • H03K5/08Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/2481Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12Analogue/digital converters
    • H03M1/50Analogue/digital converters with intermediate conversion to time interval
    • H03M1/56Input signal compared with linear ramp
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/674Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6729Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733Multi-gate TFTs
    • H10D30/6734Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Theoretical Computer Science (AREA)
  • Thin Film Transistor (AREA)
  • Manipulation Of Pulses (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
JP2022538485A 2020-07-24 2021-07-12 Withdrawn JPWO2022018560A1 (enExample)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2025062645A JP2025100591A (ja) 2020-07-24 2025-04-04 半導体装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2020125992 2020-07-24
PCT/IB2021/056221 WO2022018560A1 (ja) 2020-07-24 2021-07-12 半導体装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2025062645A Division JP2025100591A (ja) 2020-07-24 2025-04-04 半導体装置

Publications (2)

Publication Number Publication Date
JPWO2022018560A1 true JPWO2022018560A1 (enExample) 2022-01-27
JPWO2022018560A5 JPWO2022018560A5 (enExample) 2024-07-02

Family

ID=79728638

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2022538485A Withdrawn JPWO2022018560A1 (enExample) 2020-07-24 2021-07-12
JP2025062645A Pending JP2025100591A (ja) 2020-07-24 2025-04-04 半導体装置

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2025062645A Pending JP2025100591A (ja) 2020-07-24 2025-04-04 半導体装置

Country Status (5)

Country Link
US (1) US12126344B2 (enExample)
JP (2) JPWO2022018560A1 (enExample)
KR (1) KR20230041967A (enExample)
CN (1) CN115885472A (enExample)
WO (1) WO2022018560A1 (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2025099800A1 (ja) * 2023-11-06 2025-05-15 株式会社ソシオネクスト 半導体集積回路装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014096769A (ja) * 2012-11-12 2014-05-22 Fujitsu Ltd 比較回路およびa/d変換回路
JP2017192124A (ja) * 2016-02-10 2017-10-19 株式会社半導体エネルギー研究所 半導体装置、電子部品、および電子機器
JP2018011294A (ja) * 2016-06-30 2018-01-18 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の動作方法
JP2018207486A (ja) * 2017-05-31 2018-12-27 株式会社半導体エネルギー研究所 比較回路、半導体装置、電子部品、および電子機器
WO2020031016A1 (ja) * 2018-08-10 2020-02-13 株式会社半導体エネルギー研究所 アンプ回路、ラッチ回路、及び検知装置

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FR2573211B1 (fr) 1984-11-09 1986-12-12 Labo Electronique Physique Comparateur synchronise
JP2004304312A (ja) * 2003-03-28 2004-10-28 Toshiba Corp アナログ/ディジタル変換器および通信装置
JP5412639B2 (ja) * 2008-10-31 2014-02-12 国立大学法人東京工業大学 比較器及びアナログデジタル変換器
KR20130061678A (ko) 2010-04-16 2013-06-11 가부시키가이샤 한도오따이 에네루기 켄큐쇼 전원 회로
WO2011145707A1 (en) 2010-05-21 2011-11-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and display device
KR101872188B1 (ko) 2010-05-21 2018-06-29 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 표시 장치
JP5627512B2 (ja) 2011-03-04 2014-11-19 三菱電機株式会社 パワーモジュール
JP6023453B2 (ja) 2011-04-15 2016-11-09 株式会社半導体エネルギー研究所 記憶装置
US9935622B2 (en) 2011-04-28 2018-04-03 Semiconductor Energy Laboratory Co., Ltd. Comparator and semiconductor device including comparator
WO2014157019A1 (en) 2013-03-25 2014-10-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US20150035509A1 (en) 2013-07-31 2015-02-05 Semiconductor Energy Laboratory Co., Ltd. Control circuit and dc-dc converter
JP6392603B2 (ja) 2013-09-27 2018-09-19 株式会社半導体エネルギー研究所 半導体装置
JP6906978B2 (ja) 2016-02-25 2021-07-21 株式会社半導体エネルギー研究所 半導体装置、半導体ウェハ、および電子機器
US10236875B2 (en) * 2016-04-15 2019-03-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for operating the semiconductor device
KR102487750B1 (ko) * 2017-03-03 2023-01-11 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 반도체 장치의 구동 방법
US9755655B1 (en) * 2017-03-08 2017-09-05 Xilinx, Inc. Dynamic quantizers having multiple reset levels
CN112425071A (zh) 2018-07-20 2021-02-26 株式会社半导体能源研究所 接收电路
US11714138B2 (en) 2018-11-22 2023-08-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, power storage device, and electronic device
US11973198B2 (en) 2018-11-22 2024-04-30 Semiconductor Energy Laboratory Co., Ltd. Device detecting abnormality of secondary battery and semiconductor device
JP7345497B2 (ja) 2018-11-22 2023-09-15 株式会社半導体エネルギー研究所 電池パック
KR102779364B1 (ko) 2018-12-19 2025-03-12 가부시키가이샤 한도오따이 에네루기 켄큐쇼 히스테리시스 콤퍼레이터, 반도체 장치, 및 축전 장치
WO2020128673A1 (ja) 2018-12-21 2020-06-25 株式会社半導体エネルギー研究所 半導体装置、並びに電子機器及び人工衛星

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014096769A (ja) * 2012-11-12 2014-05-22 Fujitsu Ltd 比較回路およびa/d変換回路
JP2017192124A (ja) * 2016-02-10 2017-10-19 株式会社半導体エネルギー研究所 半導体装置、電子部品、および電子機器
JP2018011294A (ja) * 2016-06-30 2018-01-18 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の動作方法
JP2018207486A (ja) * 2017-05-31 2018-12-27 株式会社半導体エネルギー研究所 比較回路、半導体装置、電子部品、および電子機器
WO2020031016A1 (ja) * 2018-08-10 2020-02-13 株式会社半導体エネルギー研究所 アンプ回路、ラッチ回路、及び検知装置

Also Published As

Publication number Publication date
US12126344B2 (en) 2024-10-22
US20230198509A1 (en) 2023-06-22
WO2022018560A1 (ja) 2022-01-27
KR20230041967A (ko) 2023-03-27
JP2025100591A (ja) 2025-07-03
CN115885472A (zh) 2023-03-31

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