JPWO2021125094A1 - - Google Patents

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Publication number
JPWO2021125094A1
JPWO2021125094A1 JP2021565553A JP2021565553A JPWO2021125094A1 JP WO2021125094 A1 JPWO2021125094 A1 JP WO2021125094A1 JP 2021565553 A JP2021565553 A JP 2021565553A JP 2021565553 A JP2021565553 A JP 2021565553A JP WO2021125094 A1 JPWO2021125094 A1 JP WO2021125094A1
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JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2021565553A
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Japanese (ja)
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JP7594192B2 (ja
JPWO2021125094A5 (https=
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Publication of JPWO2021125094A1 publication Critical patent/JPWO2021125094A1/ja
Publication of JPWO2021125094A5 publication Critical patent/JPWO2021125094A5/ja
Application granted granted Critical
Publication of JP7594192B2 publication Critical patent/JP7594192B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6735—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes having gates fully surrounding the channels, e.g. gate-all-around
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/43—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
    • H10D62/121—Nanowire, nanosheet or nanotube semiconductor bodies oriented parallel to substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/0698—Local interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/427—Power or ground buses
JP2021565553A 2019-12-19 2020-12-11 半導体記憶装置 Active JP7594192B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2019229339 2019-12-19
JP2019229339 2019-12-19
PCT/JP2020/046340 WO2021125094A1 (ja) 2019-12-19 2020-12-11 半導体記憶装置

Publications (3)

Publication Number Publication Date
JPWO2021125094A1 true JPWO2021125094A1 (https=) 2021-06-24
JPWO2021125094A5 JPWO2021125094A5 (https=) 2022-08-15
JP7594192B2 JP7594192B2 (ja) 2024-12-04

Family

ID=76478626

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2021565553A Active JP7594192B2 (ja) 2019-12-19 2020-12-11 半導体記憶装置

Country Status (3)

Country Link
US (2) US12232308B2 (https=)
JP (1) JP7594192B2 (https=)
WO (1) WO2021125094A1 (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020246344A1 (ja) * 2019-06-03 2020-12-10 株式会社ソシオネクスト 半導体記憶装置
JP7640861B2 (ja) * 2019-10-18 2025-03-06 株式会社ソシオネクスト 半導体集積回路装置
US11114153B2 (en) * 2019-12-30 2021-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. SRAM devices with reduced coupling capacitance
US20220359545A1 (en) * 2021-05-07 2022-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor memory devices with dielectric fin structures
WO2023171452A1 (ja) * 2022-03-07 2023-09-14 株式会社ソシオネクスト 半導体記憶装置
WO2023204111A1 (ja) * 2022-04-20 2023-10-26 株式会社ソシオネクスト 半導体記憶装置
US20240113104A1 (en) * 2022-09-30 2024-04-04 Intel Corporation Forksheet transistor structures with gate cut spine

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008176910A (ja) * 2006-12-21 2008-07-31 Matsushita Electric Ind Co Ltd 半導体記憶装置
US20170162583A1 (en) * 2015-12-03 2017-06-08 Samsung Electronics Co., Ltd. Static random access memory (sram) device for improving electrical characteristics and logic device including the same
US20170194037A1 (en) * 2015-12-31 2017-07-06 Taiwan Semiconductor Manufacturing Company Ltd. Digtial circuit structures to control leakage current
WO2018025597A1 (ja) * 2016-08-01 2018-02-08 株式会社ソシオネクスト 半導体チップ

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7839697B2 (en) 2006-12-21 2010-11-23 Panasonic Corporation Semiconductor memory device
US9362292B1 (en) 2015-04-17 2016-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Two-port SRAM cell structure for vertical devices
WO2017169150A1 (ja) * 2016-03-28 2017-10-05 株式会社ソシオネクスト 半導体集積回路装置
WO2019077747A1 (ja) * 2017-10-20 2019-04-25 株式会社ソシオネクスト 半導体記憶回路

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008176910A (ja) * 2006-12-21 2008-07-31 Matsushita Electric Ind Co Ltd 半導体記憶装置
US20170162583A1 (en) * 2015-12-03 2017-06-08 Samsung Electronics Co., Ltd. Static random access memory (sram) device for improving electrical characteristics and logic device including the same
US20170194037A1 (en) * 2015-12-31 2017-07-06 Taiwan Semiconductor Manufacturing Company Ltd. Digtial circuit structures to control leakage current
WO2018025597A1 (ja) * 2016-08-01 2018-02-08 株式会社ソシオネクスト 半導体チップ

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
WECKX P., ET AL.: "Stacked nanosheet fork architecture for SRAM design and device co-optimization toward 3nm", IEEE CONFERENCE PROCEEDINGS, vol. 2017, JPN7024004451, 2017, US, pages 20 - 5, ISSN: 0005442430 *

Also Published As

Publication number Publication date
JP7594192B2 (ja) 2024-12-04
WO2021125094A1 (ja) 2021-06-24
US20250159860A1 (en) 2025-05-15
US20220310631A1 (en) 2022-09-29
US12232308B2 (en) 2025-02-18

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