JPWO2020123471A5 - - Google Patents
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- JPWO2020123471A5 JPWO2020123471A5 JP2021533424A JP2021533424A JPWO2020123471A5 JP WO2020123471 A5 JPWO2020123471 A5 JP WO2020123471A5 JP 2021533424 A JP2021533424 A JP 2021533424A JP 2021533424 A JP2021533424 A JP 2021533424A JP WO2020123471 A5 JPWO2020123471 A5 JP WO2020123471A5
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- JP
- Japan
- Prior art keywords
- ecc
- data block
- address
- data
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 238000000034 method Methods 0.000 claims 3
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2023153988A JP7754612B2 (ja) | 2018-12-11 | 2023-09-20 | インラインｅｃｃ保護のための方法及びシステム |
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201862777993P | 2018-12-11 | 2018-12-11 | |
| US62/777,993 | 2018-12-11 | ||
| US16/590,515 US11119909B2 (en) | 2018-12-11 | 2019-10-02 | Method and system for in-line ECC protection |
| US16/590,515 | 2019-10-02 | ||
| PCT/US2019/065416 WO2020123471A1 (en) | 2018-12-11 | 2019-12-10 | Method and system for in-line ecc protection |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2023153988A Division JP7754612B2 (ja) | 2018-12-11 | 2023-09-20 | インラインｅｃｃ保護のための方法及びシステム |
Publications (4)
| Publication Number | Publication Date |
|---|---|
| JP2022520150A JP2022520150A (ja) | 2022-03-29 |
| JPWO2020123471A5 true JPWO2020123471A5 (https=) | 2022-12-09 |
| JP2022520150A5 JP2022520150A5 (https=) | 2022-12-09 |
| JP7354253B2 JP7354253B2 (ja) | 2023-10-02 |
Family
ID=70972067
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2021533424A Active JP7354253B2 (ja) | 2018-12-11 | 2019-12-10 | インラインｅｃｃ保護のための方法及びシステム |
| JP2023153988A Active JP7754612B2 (ja) | 2018-12-11 | 2023-09-20 | インラインｅｃｃ保護のための方法及びシステム |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2023153988A Active JP7754612B2 (ja) | 2018-12-11 | 2023-09-20 | インラインｅｃｃ保護のための方法及びシステム |
Country Status (5)
| Country | Link |
|---|---|
| US (4) | US11119909B2 (https=) |
| EP (1) | EP3895017B1 (https=) |
| JP (2) | JP7354253B2 (https=) |
| CN (2) | CN119127562A (https=) |
| WO (1) | WO2020123471A1 (https=) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11119909B2 (en) * | 2018-12-11 | 2021-09-14 | Texas Instmments Incorporated | Method and system for in-line ECC protection |
| US11416334B2 (en) * | 2019-05-24 | 2022-08-16 | Texas Instmments Incorporated | Handling non-correctable errors |
| US12175363B2 (en) | 2020-07-27 | 2024-12-24 | Microchip Technology Inc. | Regression neural network for identifying threshold voltages to be used in reads of flash memory devices |
| US11385961B2 (en) * | 2020-08-14 | 2022-07-12 | Micron Technology, Inc. | Adaptive parity techniques for a memory device |
| US12393846B2 (en) | 2020-08-20 | 2025-08-19 | Microchip Technology Inc. | Partitionable neural network for solid state drives |
| US12493778B2 (en) | 2020-12-15 | 2025-12-09 | Microchip Technology Inc. | Method and apparatus for performing a neural network operation |
| US12014068B2 (en) | 2021-04-27 | 2024-06-18 | Microchip Technology Inc. | System and method for double data rate (DDR) chip-kill recovery |
| US11561857B2 (en) * | 2021-05-11 | 2023-01-24 | Robert Bosch Gmbh | Method for the secured storing of a data element to be stored by a computer program in an external memory |
| US11934696B2 (en) | 2021-05-18 | 2024-03-19 | Microchip Technology Inc. | Machine learning assisted quality of service (QoS) for solid state drives |
| US11699493B2 (en) | 2021-05-24 | 2023-07-11 | Microchip Technology Inc. | Method and apparatus for performing a read of a flash memory using predicted retention-and-read-disturb-compensated threshold voltage shift offset values |
| US11663076B2 (en) | 2021-06-01 | 2023-05-30 | Microchip Technology Inc. | Memory address protection |
| DE112022002131B4 (de) | 2021-09-28 | 2026-02-05 | Microchip Technology Inc. | Ldpc-dekodierung mit trapped-block-management |
| US12124328B2 (en) * | 2022-04-26 | 2024-10-22 | Nxp Usa, Inc. | Data processing system having a memory controller with inline error correction code (ECC) support |
| TWI823519B (zh) * | 2022-08-15 | 2023-11-21 | 慧榮科技股份有限公司 | 資料儲存裝置以及非揮發式記憶體控制方法 |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0415547A3 (en) * | 1989-08-01 | 1993-03-24 | Digital Equipment Corporation | Method of handling nonexistent memory errors |
| IT1261411B (it) * | 1993-03-12 | 1996-05-23 | Texas Instruments Italia Spa | Metodo e circuiteria per l'uso di memorie aventi locazioni difettose erelativa apparecchiatura di produzione. |
| US6804799B2 (en) | 2001-06-26 | 2004-10-12 | Advanced Micro Devices, Inc. | Using type bits to track storage of ECC and predecode bits in a level two cache |
| US7043679B1 (en) | 2002-06-27 | 2006-05-09 | Advanced Micro Devices, Inc. | Piggybacking of ECC corrections behind loads |
| TWI277869B (en) * | 2005-08-23 | 2007-04-01 | Via Tech Inc | Architecture and method for storing data |
| US7676730B2 (en) * | 2005-09-30 | 2010-03-09 | Quantum Corporation | Method and apparatus for implementing error correction coding in a random access memory |
| JP2007104708A (ja) | 2006-11-27 | 2007-04-19 | Renesas Technology Corp | データ処理方法 |
| US8135935B2 (en) * | 2007-03-20 | 2012-03-13 | Advanced Micro Devices, Inc. | ECC implementation in non-ECC components |
| JP2009104757A (ja) | 2007-10-02 | 2009-05-14 | Panasonic Corp | 半導体記憶装置 |
| US8127185B2 (en) * | 2009-01-23 | 2012-02-28 | Micron Technology, Inc. | Memory devices and methods for managing error regions |
| JP2011257966A (ja) | 2010-06-09 | 2011-12-22 | Mitsubishi Electric Corp | キャッシュ装置及び情報処理装置 |
| US8341498B2 (en) * | 2010-10-01 | 2012-12-25 | Sandisk Technologies Inc. | System and method of data encoding |
| JP5617776B2 (ja) | 2011-06-27 | 2014-11-05 | 株式会社デンソー | メモリ回路，メモリ装置及びメモリデータの誤り訂正方法 |
| US9417821B2 (en) | 2011-09-30 | 2016-08-16 | Intel Corporation | Presentation of direct accessed storage under a logical drive model |
| US9582354B2 (en) | 2014-01-28 | 2017-02-28 | Infineon Technologies Ag | Apparatus and method for improving data storage by data inversion |
| US9904595B1 (en) | 2016-08-23 | 2018-02-27 | Texas Instruments Incorporated | Error correction hardware with fault detection |
| US11119909B2 (en) * | 2018-12-11 | 2021-09-14 | Texas Instmments Incorporated | Method and system for in-line ECC protection |
-
2019
- 2019-10-02 US US16/590,515 patent/US11119909B2/en active Active
- 2019-12-10 JP JP2021533424A patent/JP7354253B2/ja active Active
- 2019-12-10 CN CN202411163946.XA patent/CN119127562A/zh active Pending
- 2019-12-10 EP EP19895886.0A patent/EP3895017B1/en active Active
- 2019-12-10 WO PCT/US2019/065416 patent/WO2020123471A1/en not_active Ceased
- 2019-12-10 CN CN201980068709.6A patent/CN112867993B/zh active Active
-
2021
- 2021-09-14 US US17/474,141 patent/US11726907B2/en active Active
-
2023
- 2023-08-14 US US18/449,025 patent/US12204443B2/en active Active
- 2023-09-20 JP JP2023153988A patent/JP7754612B2/ja active Active
-
2025
- 2025-01-21 US US19/032,567 patent/US20250165393A1/en active Pending
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