JP7354253B2 - インラインｅｃｃ保護のための方法及びシステム - Google Patents

インラインｅｃｃ保護のための方法及びシステム Download PDF

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JP7354253B2
JP7354253B2 JP2021533424A JP2021533424A JP7354253B2 JP 7354253 B2 JP7354253 B2 JP 7354253B2 JP 2021533424 A JP2021533424 A JP 2021533424A JP 2021533424 A JP2021533424 A JP 2021533424A JP 7354253 B2 JP7354253 B2 JP 7354253B2
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ecc
data
block
address
memory
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JPWO2020123471A5 (https=
JP2022520150A5 (https=
JP2022520150A (ja
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ローランド ビュードイン デニス
ディラジラル ソジトラ リテシュ
ポール ヴィサリ サミュエル
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日本テキサス・インスツルメンツ合同会社
テキサス インスツルメンツ インコーポレイテッド
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Priority to JP2023153988A priority Critical patent/JP7754612B2/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/04—Addressing variable-length words or parts of words
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0879—Burst mode
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/30—Providing cache or TLB in specific location of a processing system
    • G06F2212/306—In system interconnect, e.g. between two buses
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/40—Specific encoding of data in memory or cache
    • G06F2212/403—Error protection encoding, e.g. using parity or ECC codes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0411—Online error correction

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Quality & Reliability (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System (AREA)
JP2021533424A 2018-12-11 2019-12-10 インラインｅｃｃ保護のための方法及びシステム Active JP7354253B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2023153988A JP7754612B2 (ja) 2018-12-11 2023-09-20 インラインｅｃｃ保護のための方法及びシステム

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201862777993P 2018-12-11 2018-12-11
US62/777,993 2018-12-11
US16/590,515 US11119909B2 (en) 2018-12-11 2019-10-02 Method and system for in-line ECC protection
US16/590,515 2019-10-02
PCT/US2019/065416 WO2020123471A1 (en) 2018-12-11 2019-12-10 Method and system for in-line ecc protection

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2023153988A Division JP7754612B2 (ja) 2018-12-11 2023-09-20 インラインｅｃｃ保護のための方法及びシステム

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JP2022520150A JP2022520150A (ja) 2022-03-29
JPWO2020123471A5 JPWO2020123471A5 (https=) 2022-12-09
JP2022520150A5 JP2022520150A5 (https=) 2022-12-09
JP7354253B2 true JP7354253B2 (ja) 2023-10-02

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JP2023153988A Active JP7754612B2 (ja) 2018-12-11 2023-09-20 インラインｅｃｃ保護のための方法及びシステム

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US (4) US11119909B2 (https=)
EP (1) EP3895017B1 (https=)
JP (2) JP7354253B2 (https=)
CN (2) CN119127562A (https=)
WO (1) WO2020123471A1 (https=)

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US11119909B2 (en) * 2018-12-11 2021-09-14 Texas Instmments Incorporated Method and system for in-line ECC protection
US11416334B2 (en) * 2019-05-24 2022-08-16 Texas Instmments Incorporated Handling non-correctable errors
US12175363B2 (en) 2020-07-27 2024-12-24 Microchip Technology Inc. Regression neural network for identifying threshold voltages to be used in reads of flash memory devices
US11385961B2 (en) * 2020-08-14 2022-07-12 Micron Technology, Inc. Adaptive parity techniques for a memory device
US12393846B2 (en) 2020-08-20 2025-08-19 Microchip Technology Inc. Partitionable neural network for solid state drives
US12493778B2 (en) 2020-12-15 2025-12-09 Microchip Technology Inc. Method and apparatus for performing a neural network operation
US12014068B2 (en) 2021-04-27 2024-06-18 Microchip Technology Inc. System and method for double data rate (DDR) chip-kill recovery
US11561857B2 (en) * 2021-05-11 2023-01-24 Robert Bosch Gmbh Method for the secured storing of a data element to be stored by a computer program in an external memory
US11934696B2 (en) 2021-05-18 2024-03-19 Microchip Technology Inc. Machine learning assisted quality of service (QoS) for solid state drives
US11699493B2 (en) 2021-05-24 2023-07-11 Microchip Technology Inc. Method and apparatus for performing a read of a flash memory using predicted retention-and-read-disturb-compensated threshold voltage shift offset values
US11663076B2 (en) 2021-06-01 2023-05-30 Microchip Technology Inc. Memory address protection
DE112022002131B4 (de) 2021-09-28 2026-02-05 Microchip Technology Inc. Ldpc-dekodierung mit trapped-block-management
US12124328B2 (en) * 2022-04-26 2024-10-22 Nxp Usa, Inc. Data processing system having a memory controller with inline error correction code (ECC) support
TWI823519B (zh) * 2022-08-15 2023-11-21 慧榮科技股份有限公司 資料儲存裝置以及非揮發式記憶體控制方法

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JP2007104708A (ja) 2006-11-27 2007-04-19 Renesas Technology Corp データ処理方法
JP2010522374A (ja) 2007-03-20 2010-07-01 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 非ｅｃｃコンポーネントにおけるｅｃｃの実装

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Publication number Publication date
EP3895017A1 (en) 2021-10-20
JP2023169327A (ja) 2023-11-29
WO2020123471A1 (en) 2020-06-18
US12204443B2 (en) 2025-01-21
EP3895017B1 (en) 2026-04-15
US20210406171A1 (en) 2021-12-30
US11119909B2 (en) 2021-09-14
US20250165393A1 (en) 2025-05-22
CN112867993A (zh) 2021-05-28
JP7754612B2 (ja) 2025-10-15
US20200183826A1 (en) 2020-06-11
EP3895017A4 (en) 2022-06-22
CN119127562A (zh) 2024-12-13
JP2022520150A (ja) 2022-03-29
CN112867993B (zh) 2024-09-03
US20230393975A1 (en) 2023-12-07
US11726907B2 (en) 2023-08-15

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