CN119127562A - 用于嵌入式ecc保护的方法及系统 - Google Patents

用于嵌入式ecc保护的方法及系统 Download PDF

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Publication number
CN119127562A
CN119127562A CN202411163946.XA CN202411163946A CN119127562A CN 119127562 A CN119127562 A CN 119127562A CN 202411163946 A CN202411163946 A CN 202411163946A CN 119127562 A CN119127562 A CN 119127562A
Authority
CN
China
Prior art keywords
data
ecc
memory
address
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202411163946.XA
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English (en)
Chinese (zh)
Inventor
D·R·博杜安
R·D·索吉特拉
S·P·维萨利
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
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Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of CN119127562A publication Critical patent/CN119127562A/zh
Pending legal-status Critical Current

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Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/0223User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023Free address space management
    • G06F12/0238Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/0223User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/04Addressing variable-length words or parts of words
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877Cache access modes
    • G06F12/0879Burst mode
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4027Coupling between buses using bus bridges
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38Response verification devices
    • G11C29/42Response verification devices using error correcting codes [ECC] or parity check
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70Masking faults in memories by using spares or by reconfiguring
    • G11C29/76Masking faults in memories by using spares or by reconfiguring using address translation or modifications
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/06Address interface arrangements, e.g. address buffers
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10Providing a specific technical effect
    • G06F2212/1032Reliability improvement, data loss prevention, degraded operation etc
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/30Providing cache or TLB in specific location of a processing system
    • G06F2212/306In system interconnect, e.g. between two buses
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/40Specific encoding of data in memory or cache
    • G06F2212/403Error protection encoding, e.g. using parity or ECC codes
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0411Online error correction

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Quality & Reliability (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System (AREA)
CN202411163946.XA 2018-12-11 2019-12-10 用于嵌入式ecc保护的方法及系统 Pending CN119127562A (zh)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US201862777993P 2018-12-11 2018-12-11
US62/777,993 2018-12-11
US16/590,515 US11119909B2 (en) 2018-12-11 2019-10-02 Method and system for in-line ECC protection
US16/590,515 2019-10-02
PCT/US2019/065416 WO2020123471A1 (en) 2018-12-11 2019-12-10 Method and system for in-line ecc protection
CN201980068709.6A CN112867993B (zh) 2018-12-11 2019-12-10 用于嵌入式ecc保护的方法及系统

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CN201980068709.6A Division CN112867993B (zh) 2018-12-11 2019-12-10 用于嵌入式ecc保护的方法及系统

Publications (1)

Publication Number Publication Date
CN119127562A true CN119127562A (zh) 2024-12-13

Family

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Family Applications (2)

Application Number Title Priority Date Filing Date
CN202411163946.XA Pending CN119127562A (zh) 2018-12-11 2019-12-10 用于嵌入式ecc保护的方法及系统
CN201980068709.6A Active CN112867993B (zh) 2018-12-11 2019-12-10 用于嵌入式ecc保护的方法及系统

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN201980068709.6A Active CN112867993B (zh) 2018-12-11 2019-12-10 用于嵌入式ecc保护的方法及系统

Country Status (5)

Country Link
US (4) US11119909B2 (https=)
EP (1) EP3895017B1 (https=)
JP (2) JP7354253B2 (https=)
CN (2) CN119127562A (https=)
WO (1) WO2020123471A1 (https=)

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US11119909B2 (en) * 2018-12-11 2021-09-14 Texas Instmments Incorporated Method and system for in-line ECC protection
US11416334B2 (en) * 2019-05-24 2022-08-16 Texas Instmments Incorporated Handling non-correctable errors
US12175363B2 (en) 2020-07-27 2024-12-24 Microchip Technology Inc. Regression neural network for identifying threshold voltages to be used in reads of flash memory devices
US11385961B2 (en) * 2020-08-14 2022-07-12 Micron Technology, Inc. Adaptive parity techniques for a memory device
US12393846B2 (en) 2020-08-20 2025-08-19 Microchip Technology Inc. Partitionable neural network for solid state drives
US12493778B2 (en) 2020-12-15 2025-12-09 Microchip Technology Inc. Method and apparatus for performing a neural network operation
US12014068B2 (en) 2021-04-27 2024-06-18 Microchip Technology Inc. System and method for double data rate (DDR) chip-kill recovery
US11561857B2 (en) * 2021-05-11 2023-01-24 Robert Bosch Gmbh Method for the secured storing of a data element to be stored by a computer program in an external memory
US11934696B2 (en) 2021-05-18 2024-03-19 Microchip Technology Inc. Machine learning assisted quality of service (QoS) for solid state drives
US11699493B2 (en) 2021-05-24 2023-07-11 Microchip Technology Inc. Method and apparatus for performing a read of a flash memory using predicted retention-and-read-disturb-compensated threshold voltage shift offset values
US11663076B2 (en) 2021-06-01 2023-05-30 Microchip Technology Inc. Memory address protection
DE112022002131B4 (de) 2021-09-28 2026-02-05 Microchip Technology Inc. Ldpc-dekodierung mit trapped-block-management
US12124328B2 (en) * 2022-04-26 2024-10-22 Nxp Usa, Inc. Data processing system having a memory controller with inline error correction code (ECC) support
TWI823519B (zh) * 2022-08-15 2023-11-21 慧榮科技股份有限公司 資料儲存裝置以及非揮發式記憶體控制方法

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IT1261411B (it) * 1993-03-12 1996-05-23 Texas Instruments Italia Spa Metodo e circuiteria per l'uso di memorie aventi locazioni difettose erelativa apparecchiatura di produzione.
US6804799B2 (en) 2001-06-26 2004-10-12 Advanced Micro Devices, Inc. Using type bits to track storage of ECC and predecode bits in a level two cache
US7043679B1 (en) 2002-06-27 2006-05-09 Advanced Micro Devices, Inc. Piggybacking of ECC corrections behind loads
TWI277869B (en) * 2005-08-23 2007-04-01 Via Tech Inc Architecture and method for storing data
US7676730B2 (en) * 2005-09-30 2010-03-09 Quantum Corporation Method and apparatus for implementing error correction coding in a random access memory
JP2007104708A (ja) 2006-11-27 2007-04-19 Renesas Technology Corp データ処理方法
US8135935B2 (en) * 2007-03-20 2012-03-13 Advanced Micro Devices, Inc. ECC implementation in non-ECC components
JP2009104757A (ja) 2007-10-02 2009-05-14 Panasonic Corp 半導体記憶装置
US8127185B2 (en) * 2009-01-23 2012-02-28 Micron Technology, Inc. Memory devices and methods for managing error regions
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US11119909B2 (en) * 2018-12-11 2021-09-14 Texas Instmments Incorporated Method and system for in-line ECC protection

Also Published As

Publication number Publication date
EP3895017A1 (en) 2021-10-20
JP2023169327A (ja) 2023-11-29
WO2020123471A1 (en) 2020-06-18
US12204443B2 (en) 2025-01-21
EP3895017B1 (en) 2026-04-15
US20210406171A1 (en) 2021-12-30
US11119909B2 (en) 2021-09-14
US20250165393A1 (en) 2025-05-22
CN112867993A (zh) 2021-05-28
JP7354253B2 (ja) 2023-10-02
JP7754612B2 (ja) 2025-10-15
US20200183826A1 (en) 2020-06-11
EP3895017A4 (en) 2022-06-22
JP2022520150A (ja) 2022-03-29
CN112867993B (zh) 2024-09-03
US20230393975A1 (en) 2023-12-07
US11726907B2 (en) 2023-08-15

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