JPWO2020070580A1 - 半導体装置、および半導体装置の作製方法 - Google Patents
半導体装置、および半導体装置の作製方法 Download PDFInfo
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- JPWO2020070580A1 JPWO2020070580A1 JP2020550946A JP2020550946A JPWO2020070580A1 JP WO2020070580 A1 JPWO2020070580 A1 JP WO2020070580A1 JP 2020550946 A JP2020550946 A JP 2020550946A JP 2020550946 A JP2020550946 A JP 2020550946A JP WO2020070580 A1 JPWO2020070580 A1 JP WO2020070580A1
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Abstract
Description
以下では、本発明の一態様に係るトランジスタ200を有する半導体装置の一例、およびその作製方法について説明する。
図1A、図1B、および図1Cは、本発明の一態様に係るトランジスタ200、およびトランジスタ200周辺の上面図および断面図である。
図1に示すように、トランジスタ200は、絶縁体214上の絶縁体216と、絶縁体216に埋め込まれるように配置された導電体205(導電体205a、および導電体205b)と、絶縁体216上、および導電体205上の絶縁体222と、絶縁体222上の絶縁体224と、絶縁体224上の酸化物230aと、酸化物230a上の酸化物230bと、酸化物230b上の酸化物243aおよび酸化物243bと、酸化物243a上の導電体242aと、酸化物243b上の導電体242bと、酸化物230b上の酸化物230cと、酸化物230c上の絶縁体250と、絶縁体250上に位置し、酸化物230cと重なる導電体260(導電体260a、および導電体260b)と、絶縁体224の上面の一部、酸化物230aの側面、酸化物230bの側面、酸化物243aの側面、酸化物243bの側面、導電体242aの側面、導電体242aの上面、導電体242bの側面、および導電体242bの上面と接する絶縁体272と、絶縁体272上の絶縁体273と、を有する。また、酸化物230cは、酸化物243aの側面、酸化物243bの側面、導電体242aの側面および導電体242bの側面とそれぞれ接する。導電体260は、導電体260aおよび導電体260bを有し、導電体260bの底面および側面を包むように導電体260aが配置される。ここで、図1Bに示すように、導電体260の上面は、絶縁体250の上面および酸化物230cの上面と略一致して配置される。また、絶縁体282は、導電体260、酸化物230c、絶縁体250、および絶縁体280のそれぞれの上面と接する。
以下では、半導体装置に用いることができる構成材料について説明する。
トランジスタ200を形成する基板としては、例えば、絶縁体基板、半導体基板、または導電体基板を用いればよい。絶縁体基板としては、例えば、ガラス基板、石英基板、サファイア基板、安定化ジルコニア基板(イットリア安定化ジルコニア基板など)、樹脂基板などがある。また、半導体基板としては、例えば、シリコン、ゲルマニウムを材料とした半導体基板、または炭化シリコン、シリコンゲルマニウム、ヒ化ガリウム、リン化インジウム、酸化亜鉛、酸化ガリウムからなる化合物半導体基板などがある。さらには、前述の半導体基板内部に絶縁体領域を有する半導体基板、例えば、SOI(Silicon On Insulator)基板などがある。導電体基板としては、黒鉛基板、金属基板、合金基板、導電性樹脂基板などがある。または、金属の窒化物を有する基板、金属の酸化物を有する基板などがある。さらには、絶縁体基板に導電体または半導体が設けられた基板、半導体基板に導電体または絶縁体が設けられた基板、導電体基板に半導体または絶縁体が設けられた基板などがある。または、これらの基板に素子が設けられたものを用いてもよい。基板に設けられる素子としては、容量素子、抵抗素子、スイッチ素子、発光素子、記憶素子などがある。
絶縁体としては、絶縁性を有する酸化物、窒化物、酸化窒化物、窒化酸化物、金属酸化物、金属酸化窒化物、金属窒化酸化物などがある。
導電体としては、アルミニウム、クロム、銅、銀、金、白金、タンタル、ニッケル、チタン、モリブデン、タングステン、ハフニウム、バナジウム、ニオブ、マンガン、マグネシウム、ジルコニウム、ベリリウム、インジウム、ルテニウム、イリジウム、ストロンチウム、ランタンなどから選ばれた金属元素、または上述した金属元素を成分とする合金か、上述した金属元素を組み合わせた合金等を用いることが好ましい。例えば、窒化タンタル、窒化チタン、タングステン、チタンとアルミニウムを含む窒化物、タンタルとアルミニウムを含む窒化物、酸化ルテニウム、窒化ルテニウム、ストロンチウムとルテニウムを含む酸化物、ランタンとニッケルを含む酸化物などを用いることが好ましい。また、窒化タンタル、窒化チタン、チタンとアルミニウムを含む窒化物、タンタルとアルミニウムを含む窒化物、酸化ルテニウム、窒化ルテニウム、ストロンチウムとルテニウムを含む酸化物、ランタンとニッケルを含む酸化物は、酸化しにくい導電性材料、または、酸素を吸収しても導電性を維持する材料であるため、好ましい。また、リン等の不純物元素を含有させた多結晶シリコンに代表される、電気伝導度が高い半導体、ニッケルシリサイドなどのシリサイドを用いてもよい。
酸化物230として、酸化物半導体として機能する金属酸化物を用いることが好ましい。以下では、本発明に係る酸化物230に適用可能な金属酸化物について説明する。
酸化物半導体(金属酸化物)は、単結晶酸化物半導体と、それ以外の非単結晶酸化物半導体と、に分けられる。非単結晶酸化物半導体としては、例えば、CAAC−OS、多結晶酸化物半導体、nc−OS、擬似非晶質酸化物半導体(a−like OS:amorphous−like oxide semiconductor)、および非晶質酸化物半導体などがある。
ここで、金属酸化物中における各不純物の影響について説明する。
次に、図1に示す、本発明に係るトランジスタ200を有する半導体装置について、作製方法を図3乃至図12を用いて説明する。また、図3乃至図12において、各図の(A)は上面図を示す。また、各図の(B)は、(A)に示すA1−A2の一点鎖線で示す部位に対応する断面図であり、トランジスタ200のチャネル長方向の断面図でもある。また、各図の(C)は、(A)にA3−A4の一点鎖線で示す部位に対応する断面図であり、トランジスタ200のチャネル幅方向の断面図でもある。なお、各図の(A)の上面図では、図の明瞭化のために一部の要素を省いている。
以下では、本発明の一態様に係るマイクロ波処理装置について説明する。
本実施の形態では、半導体装置の一形態を、図16および図17を用いて説明する。
本発明の一態様である容量素子を使用した、半導体装置(記憶装置)の一例を図16に示す。本発明の一態様の半導体装置は、トランジスタ200はトランジスタ300の上方に設けられ、容量素子100はトランジスタ300、およびトランジスタ200の上方に設けられている。なお、トランジスタ200として、先の実施の形態で説明したトランジスタ200を用いることができる。
トランジスタ300は、基板311上に設けられ、ゲートとして機能する導電体316、ゲート絶縁体として機能する絶縁体315、基板311の一部からなる半導体領域313、およびソース領域またはドレイン領域として機能する低抵抗領域314a、および低抵抗領域314bを有する。トランジスタ300は、pチャネル型、あるいはnチャネル型のいずれでもよい。
容量素子100は、トランジスタ200の上方に設けられる。容量素子100は、第1の電極として機能する導電体110と、第2の電極として機能する導電体120、および誘電体として機能する絶縁体130とを有する。
各構造体の間には、層間膜、配線、およびプラグ等が設けられた配線層が設けられていてもよい。また、配線層は、設計に応じて複数層設けることができる。ここで、プラグまたは配線としての機能を有する導電体は、複数の構造をまとめて同一の符号を付与する場合がある。また、本明細書等において、配線と、配線と電気的に接続するプラグとが一体物であってもよい。すなわち、導電体の一部が配線として機能する場合、および導電体の一部がプラグとして機能する場合もある。
なお、トランジスタ200に、酸化物半導体を用いる場合、酸化物半導体の近傍に過剰酸素領域を有する絶縁体が設けることがある。その場合、該過剰酸素領域を有する絶縁体と、該過剰酸素領域を有する絶縁体に設ける導電体との間に、バリア性を有する絶縁体を設けることが好ましい。
本発明の一態様である半導体装置を使用した、記憶装置の一例を図17に示す。図17に示す記憶装置は、図16で示したトランジスタ200、トランジスタ300、および容量素子100を有する半導体装置に加え、トランジスタ400を有している。
トランジスタ400は、トランジスタ200と、同じ層に形成されており、並行して作製することができるトランジスタである。トランジスタ400は、第1のゲートとして機能する導電体460(導電体460a、および導電体460b)と、第2のゲートとして機能する導電体405と、ゲート絶縁層として機能する絶縁体222、および絶縁体450と、チャネル形成領域を有する酸化物430cと、ソースとして機能する導電体442a、酸化物443a、酸化物431a、および酸化物431bと、ドレインとして機能する導電体442b、酸化物443b、酸化物432a、および酸化物432bと、プラグとして機能する導電体440(導電体440a、および導電体440b)、および導電体440のバリア絶縁膜として機能する絶縁体441(絶縁体441a、および絶縁体441b)と、を有する。
以下では、大面積基板を半導体素子ごとに分断することによって、複数の半導体装置をチップ状で取り出す場合に設けられるダイシングライン(スクライブライン、分断ライン、又は切断ラインと呼ぶ場合がある)について説明する。分断方法としては、例えば、まず、基板に半導体素子を分断するための溝(ダイシングライン)を形成した後、ダイシングラインにおいて切断し、複数の半導体装置に分断(分割)する場合がある。
本実施の形態では、図18および図19を用いて、本発明の一態様に係る、酸化物を半導体に用いたトランジスタ(以下、OSトランジスタと呼ぶ場合がある)、および容量素子が適用されている記憶装置(以下、OSメモリ装置と呼ぶ場合がある)について説明する。OSメモリ装置は、少なくとも容量素子と、容量素子の充放電を制御するOSトランジスタを有する記憶装置である。OSトランジスタのオフ電流は極めて小さいので、OSメモリ装置は優れた保持特性をもち、不揮発性メモリとして機能させることができる。
図18AにOSメモリ装置の構成の一例を示す。記憶装置1400は、周辺回路1411、およびメモリセルアレイ1470を有する。周辺回路1411は、行回路1420、列回路1430、出力回路1440、コントロールロジック回路1460を有する。
図19A乃至図19Cに、DRAMのメモリセルの回路構成例を示す。本明細書等において、1OSトランジスタ1容量素子型のメモリセルを用いたDRAMを、DOSRAM(Dynamic Oxide Semiconductor Random Access Memory)と呼ぶ場合がある。図19Aに示す、メモリセル1471は、トランジスタM1と、容量素子CAと、を有する。なお、トランジスタM1は、ゲート(フロントゲートと呼ぶ場合がある)、及びバックゲートを有する。
図19D乃至図19Hに、2トランジスタ1容量素子のゲインセル型のメモリセルの回路構成例を示す。図19Dに示す、メモリセル1474は、トランジスタM2と、トランジスタM3と、容量素子CBと、を有する。なお、トランジスタM2は、フロントゲート(単にゲートと呼ぶ場合がある)、及びバックゲートを有する。本明細書等において、トランジスタM2にOSトランジスタを用いたゲインセル型のメモリセルを有する記憶装置を、NOSRAM(Nonvolatile Oxide Semiconductor RAM)と呼ぶ場合がある。
本実施の形態では、図20を用いて、本発明の半導体装置が実装されたチップ1200の一例を示す。チップ1200には、複数の回路(システム)が実装されている。このように、複数の回路(システム)を一つのチップに集積する技術を、システムオンチップ(System on Chip:SoC)と呼ぶ場合がある。
本実施の形態では、先の実施の形態に示す半導体装置を用いた記憶装置の応用例について説明する。先の実施の形態に示す半導体装置は、例えば、各種電子機器(例えば、情報端末、コンピュータ、スマートフォン、電子書籍端末、デジタルカメラ(ビデオカメラも含む)、録画再生装置、ナビゲーションシステムなど)の記憶装置に適用できる。なお、ここで、コンピュータとは、タブレット型のコンピュータや、ノート型のコンピュータや、デスクトップ型のコンピュータの他、サーバシステムのような大型のコンピュータを含むものである。または、先の実施の形態に示す半導体装置は、メモリカード(例えば、SDカード)、USBメモリ、SSD(ソリッド・ステート・ドライブ)等の各種のリムーバブル記憶装置に適用される。図21にリムーバブル記憶装置の幾つかの構成例を模式的に示す。例えば、先の実施の形態に示す半導体装置は、パッケージングされたメモリチップに加工され、様々なストレージ装置、リムーバブルメモリに用いられる。
本実施の形態では、本発明の一態様の半導体装置を適用可能な電子機器の具体例について図22を用いて説明する。
本発明の一態様に係るGPU又はチップは、様々な電子機器に搭載することができる。電子機器の例としては、例えば、テレビジョン装置、デスクトップ型もしくはノート型のパーソナルコンピュータ、コンピュータ用などのモニタ、デジタルサイネージ(Digital Signage:電子看板)、パチンコ機などの大型ゲーム機などの比較的大きな画面を備える電子機器の他、デジタルカメラ、デジタルビデオカメラ、デジタルフォトフレーム、携帯電話機、携帯型ゲーム機、携帯情報端末、音響再生装置、などが挙げられる。また、本発明の一態様に係る集積回路又はチップを電子機器に設けることにより、電子機器に人工知能を搭載することができる。
図22Aには、情報端末の一種である携帯電話(スマートフォン)が図示されている。情報端末5500は、筐体5510と、表示部5511と、を有しており、入力用インターフェースとして、タッチパネルが表示部5511に備えられ、ボタンが筐体5510に備えられている。
図22Bには、デスクトップ型情報端末5300が図示されている。デスクトップ型情報端末5300は、情報端末の本体5301と、ディスプレイ5302と、キーボード5303と、を有する。
図22Cは、電化製品の一例である電気冷凍冷蔵庫5800を示している。電気冷凍冷蔵庫5800は、筐体5801、冷蔵室用扉5802、冷凍室用扉5803等を有する。
図22Dは、ゲーム機の一例である携帯ゲーム機5200を示している。携帯ゲーム機5200は、筐体5201、表示部5202、ボタン5203等を有する。
本発明の一態様のGPU又はチップは、移動体である自動車、及び自動車の運転席周辺に適用することができる。
本発明の一態様のGPU又はチップは、放送システムに適用することができる。
Claims (7)
- 第1の導電体と、第1の絶縁体および第2の絶縁体と、第1の酸化物および第2の酸化物と、を有する半導体装置の作製方法において、
基板上に前記第1の酸化物を形成し、
前記第1の酸化物上に、前記第1の絶縁体を形成し、
前記第1の絶縁体に、前記第1の酸化物に達する開口を形成し、
前記開口において、前記第1の酸化物および前記第1の絶縁体に接するように、第1の酸化膜を成膜し、
前記第1の酸化膜上に、第1の絶縁膜を成膜し、
前記第1の絶縁膜上からマイクロ波処理を行い、
前記第1の絶縁膜及び前記第1の酸化物のいずれか一方または双方に対して、加熱処理を行い、
前記第1の絶縁膜上に、第1の導電膜を成膜し、
前記第1の酸化膜の一部、前記第1の絶縁膜の一部、および前記第1の導電膜の一部を、前記第1の絶縁体の上面が露出するまで除去して、前記第2の酸化物、前記第2の絶縁体、および前記第1の導電体を形成し、
前記マイクロ波処理は、減圧下かつ、酸素を含むガスを用いて行い、
前記加熱処理は、減圧下で行う、
半導体装置の作製方法。 - 第1の導電体と、第1の絶縁体および第2の絶縁体と、第1の酸化物および第2の酸化物と、を有する半導体装置の作製方法において、
基板上に前記第1の酸化物を形成し、
前記第1の酸化物上に、前記第1の絶縁体を形成し、
前記第1の絶縁体上からマイクロ波処理を行い、
前記第1の絶縁体及び前記第1の酸化物のいずれか一方または双方に対して、加熱処理を行い、
前記第1の絶縁体に、前記第1の酸化物に達する開口を形成し、
前記開口において、前記第1の酸化物および前記第1の絶縁体に接するように、第1の酸化膜を成膜し、
前記第1の酸化膜上に、第1の絶縁膜を成膜し、
前記第1の絶縁膜上に、第1の導電膜を成膜し、
前記第1の酸化膜の一部、前記第1の絶縁膜の一部、および前記第1の導電膜の一部を、前記第1の絶縁体の上面が露出するまで除去して、前記第2の酸化物、前記第2の絶縁体、および前記第1の導電体を形成し、
前記マイクロ波処理は、減圧下かつ、酸素を含むガスを用いて行い、
前記加熱処理は、減圧下で行う、
半導体装置の作製方法。 - 第1の導電体と、第1の絶縁体乃至第3の絶縁体と、第1の酸化物および第2の酸化物と、を有する半導体装置の作製方法において、
基板上に前記第1の酸化物を形成し、
前記第1の酸化物上に、前記第1の絶縁体を形成し、
前記第1の絶縁体に、前記第1の酸化物に達する開口を形成し、
前記開口において、前記第1の酸化物および前記第1の絶縁体に接するように、第1の酸化膜を成膜し、
前記第1の酸化膜上に、第1の絶縁膜を成膜し、
前記第1の絶縁膜上に、第1の導電膜を成膜し、
前記第1の酸化膜の一部、前記第1の絶縁膜の一部、および前記第1の導電膜の一部を、前記第1の絶縁体の上面が露出するまで除去して、前記第2の酸化物、前記第2の絶縁体、および前記第1の導電体を形成し、
前記第1の導電体上に、前記第3の絶縁体を形成し、
前記第3の絶縁体上からマイクロ波処理を行い、
前記第1の絶縁体及び前記第1の酸化物のいずれか一方または双方に対して、加熱処理を行い、
前記マイクロ波処理は、減圧下かつ、酸素を含むガスを用いて行い、
前記加熱処理は、減圧下で行う、
半導体装置の作製方法。 - 請求項1乃至請求項3のいずれか一項において、
前記マイクロ波処理の圧力は、133Pa以上である、
半導体装置の作製方法。 - 請求項1乃至請求項4のいずれか一項において、
前記加熱処理の温度は、350℃以上500℃以下である、
半導体装置の作製方法。 - 請求項1乃至請求項5のいずれか一項において、
前記マイクロ波処理と、前記加熱処理は、連続して行う、
半導体装置の作製方法。 - 請求項6において、
前記連続して行う処理は、2回以上10回以下である、
半導体装置の作製方法。
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