JPWO2019198416A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JPWO2019198416A1 JPWO2019198416A1 JP2020513131A JP2020513131A JPWO2019198416A1 JP WO2019198416 A1 JPWO2019198416 A1 JP WO2019198416A1 JP 2020513131 A JP2020513131 A JP 2020513131A JP 2020513131 A JP2020513131 A JP 2020513131A JP WO2019198416 A1 JPWO2019198416 A1 JP WO2019198416A1
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Abstract
Description
最初に本開示の実施態様を列記して説明する。以下の説明では、同一または対応する要素には同一の符号を付し、それらについて同じ説明は繰り返さない。
以下、本開示の実施形態について詳細に説明するが、本実施形態はこれらに限定されるものではない。
まず、第1の実施形態について説明する。第1の実施形態は、複数のトレンチSiC−MOSFETを備えた、耐圧が1.2kV程度の半導体装置に関する。図1は、第1の実施形態に係る半導体装置に含まれる層のレイアウトを示す図である。図2Aは、第1の実施形態に係る半導体装置に含まれる素子領域の構成を示す断面図である。図2Bは、第1の実施形態に係る半導体装置に含まれる終端領域の構成を示す断面図である。図2Bは、図1中のI−I線に沿った断面図に相当する。なお、図の縮尺は、各部を認識しやすいように適宜調整してあり、特に素子領域と終端領域との間で横方向の縮尺は統一されたものではない。また、層等の端部とは、特に限定しない限り、当該層等の素子領域から離間する側の端部をいう。
次に、半導体装置100の製造方法について説明する。図3A〜図3Rは、第1の実施形態に係る半導体装置100の製造方法を示す断面図である。
図4に示すように、JTE層152は、ソースパッド電極129のフィールドプレート部129Aの端部の下方に位置し、アクセプタ不純物を第1の実効濃度で含有する第1のJTE層152Aと、第1のJTE層152Aより第2の半導体層155の端部側に位置し、第1の実効濃度より低い第2の実効濃度でアクセプタ不純物を含有する第2のJTE層152Bと、を有することが好ましい。逆バイアス印加時において第1のJTE層152Aの空乏化を抑制し、フィールドプレート部129Aの端部に接する層間絶縁膜124への電界集中を抑制することができる。例えば、第1のJTE層152Aはアクセプタ不純物としてAlを含有し、その実効アクセプタ濃度は2×1017cm−3〜1×1019cm−3であり、第2のJTE層152Bはアクセプタ不純物としてAlを含有し、その実効アクセプタ濃度は1×1017cm−3〜5×1018cm−3である。この変形例では、埋め込みJTE層151の実効アクセプタ濃度が第2のJTE層152B及びガードリング層153の実効アクセプタ濃度より高く、第1のJTE層152Aの実効アクセプタ濃度が埋め込みJTE層151の実効アクセプタ濃度より高い。第1のJTE層152Aは第1の領域の一例であり、第2のJTE層152Bは第2の領域の一例である。
まず、第2の実施形態について説明する。第2の実施形態は、複数のトレンチSiC−MOSFETを備えた、耐圧が1.2kV程度の半導体装置に関する。図5は、第2の実施形態に係る半導体装置に含まれる層のレイアウトを示す図である。図6Aは、第2の実施形態に係る半導体装置に含まれる素子領域の構成を示す断面図である。図6Bは、第2の実施形態に係る半導体装置に含まれる終端領域の構成を示す断面図である。図6Bは、図5中のI−I線に沿った断面図に相当する。なお、図の縮尺は、各部を認識しやすいように適宜調整してあり、特に素子領域と終端領域との間で横方向の縮尺は統一されたものではない。また、層等の端部とは、特に限定しない限り、当該層等の素子領域から離間する側の端部をいう。
次に、半導体装置200の製造方法について説明する。図7A〜図7Fは、第2の実施形態に係る半導体装置200の製造方法を示す断面図である。
図8に示すように、第1の実施形態と同様に、JTE層152は、第1のJTE層152A及び第2のJTE層152Bを有することが好ましい。逆バイアス印加時において第1のJTE層152Aの空乏化を抑制し、フィールドプレート部129Aの端部に接する層間絶縁膜124への電界集中を抑制することができる。
101:SiC基板
102:n−ドリフト層
103、104:シールド領域
105:電流拡散層
110:第1の半導体層
110A:第1の面
110B:第2の面
111:n+ドリフト層
112:ボディ層
113:n+ソースコンタクト層
114:p+ソースコンタクト層
121:トレンチ
122:ゲート絶縁膜
123:ゲート電極
124:層間絶縁膜
125:開口部
126:バリアメタル膜
127、128:オーミック電極
129:ソースパッド電極
129A:フィールドプレート部
130:パッシベーション膜
151:埋め込みJTE層
152:JTE層
152A:第1のJTE層
152B:第2のJTE層
153:ガードリング層
155:第2の半導体層
191:素子領域
192:終端領域
200:半導体装置
201:SiC基板
203、204:シールド領域
205:電流拡散層
206:n−バッファ層
207:n+ドリフト層
208:pピラー
210:第1の半導体層
210A:第1の面
210B:第2の面
251:埋め込みJTE層
256:p型半導体層
260:スーパージャンクション構造
291:素子領域
292:終端領域
Claims (10)
- 複数の半導体素子が形成される素子領域を含む第1導電型の第1の半導体層と、
前記第1の半導体層の第1の面を含むように形成され、平面視で前記素子領域を包囲する環状の第2導電型の第2の半導体層と、
前記第1の半導体層内に前記第2の半導体層よりも前記第1の面から離れて形成され、前記第2の半導体層との間で前記第1の半導体層の一部を挟む第2導電型の第3の半導体層と、
前記第2の半導体層及び前記第3の半導体層を互いに電気的に接続する第2導電型の第4の半導体層と、
平面視で前記第2の半導体層の内側で前記第4の半導体層に電気的に接続された第1の電極と、
を有し、
前記第2の半導体層に含まれる第2導電型の不純物の実効濃度は、前記第1の半導体層に含まれる第1導電型の不純物の実効濃度より高く、
前記第3の半導体層に含まれる第2導電型の不純物の実効濃度は、前記第2の半導体層に含まれる第2導電型の不純物の実効濃度よりも高い半導体装置。 - 前記第2の半導体層は、
前記第4の半導体層に電気的に接続された第1の環状層と、
前記第1の環状層から離間して形成され、平面視で前記第1の環状層を包囲する第2の環状層と、
を有する請求項1に記載の半導体装置。 - 平面視で、前記第3の半導体層の外縁は、前記第2の半導体層の外縁よりも前記素子領域側に位置する請求項1又は2に記載の半導体装置。
- 前記第2の半導体層からみて前記第3の半導体層が位置する方向を下方としたとき、前記第4の半導体層の下に形成された第2導電型の第5の半導体層を有し、
平面視で、前記第5の半導体層の外縁は、前記第4の半導体層の外縁よりも前記素子領域側に位置する請求項1〜請求項3のいずれか1項に記載の半導体装置。 - 前記第1の半導体層を覆う絶縁膜を有し、
前記第1の電極は、前記絶縁膜の上から前記第2の半導体層の一部を覆うフィールドプレート部を含む請求項1〜請求項4のいずれか1項に記載の半導体装置。 - 前記第2の半導体層からみて前記第3の半導体層が位置する方向を下方としたとき、
前記第2の半導体層は、
前記フィールドプレート部の端部の下方に位置し、第1の実効濃度で第2導電型の不純物を含有する第1の領域と、
前記第1の領域より当該第2の半導体層の端部側に位置し、前記第1の実効濃度より低い第2の実効濃度で第2導電型の不純物を含有する第2の領域と、
を有する請求項5に記載の半導体装置。 - 複数の半導体素子が形成される素子領域を含む第1導電型の第1の半導体層と、
前記第1の半導体層の第1の面を含むように形成され、平面視で前記素子領域を包囲する環状の第2導電型の第2の半導体層と、
前記第1の半導体層内に前記第2の半導体層よりも前記第1の面から離れて形成され、前記第2の半導体層との間で前記第1の半導体層の一部を挟む第2導電型の第3の半導体層と、
前記第2の半導体層及び前記第3の半導体層を互いに電気的に接続する第2導電型の第4の半導体層と、
平面視で前記第2の半導体層の内側で前記第4の半導体層に電気的に接続された第1の電極と、
前記第1の半導体層内に形成され、前記第1の半導体層とスーパージャンクション構造を構成する複数の第2導電型の柱状半導体層と、
を有し、
平面視で、前記第3の半導体層の外縁は、前記第2の半導体層の外縁よりも前記素子領域側に位置し、
前記複数の柱状半導体層の少なくとも一部は前記第3の半導体層に電気的に接続され、
前記第2の半導体層に含まれる第2導電型の不純物の実効濃度は、前記第1の半導体層に含まれる第1導電型の不純物の実効濃度より高く、
前記第3の半導体層に含まれる第2導電型の不純物の実効濃度は、前記第2の半導体層に含まれる第2導電型の不純物の実効濃度よりも高い半導体装置。 - 前記複数の柱状半導体層の一部は、平面視で前記第3の半導体層の外縁の外側に位置し、前記第3の半導体層から電気的に独立している請求項7に記載の半導体装置。
- 第1の主面と前記第1の主面とは反対側の第2の主面を有するSiC基板と、
前記第2の主面上に形成された第2の電極と、
を有し、
前記第1の主面上に前記第1の半導体層が形成されている請求項1〜請求項8のいずれか1項に記載の半導体装置。 - 複数の半導体素子が形成される素子領域を含むn型のドリフト層と、
前記ドリフト層の第1の面を含むように形成され、平面視で前記素子領域を包囲する環状のp型の接合終端拡張層と、
前記ドリフト層の前記第1の面を含むように前記接合終端拡張層から離間して形成され、平面視で前記接合終端拡張層を包囲するp型のガードリング層と、
前記ドリフト層内に前記接合終端拡張層及び前記ガードリング層よりも前記第1の面から離れて形成され、前記接合終端拡張層及び前記ガードリング層との間で前記ドリフト層の一部を挟むp型の埋め込み接合終端拡張層と、
前記接合終端拡張層及び前記埋め込み接合終端拡張層を互いに電気的に接続するp型のコンタクト層と、
平面視で前記接合終端拡張層の内側で前記コンタクト層に電気的に接続された第1の電極と、
第1の主面と前記第1の主面とは反対側の第2の主面を有するSiC基板と、
前記第2の主面上に形成された第2の電極と、
を有し、
前記第1の主面上に前記ドリフト層が形成され、
平面視で、前記埋め込み接合終端拡張層の外縁は、前記ガードリング層の外縁よりも前記素子領域側に位置し、
前記接合終端拡張層及び前記ガードリング層に含まれるアクセプタ不純物の実効濃度は、前記ドリフト層に含まれるドナー不純物の実効濃度より高く、
前記埋め込み接合終端拡張層に含まれるアクセプタ不純物の実効濃度は、前記接合終端拡張層及び前記ガードリング層に含まれるアクセプタ不純物の実効濃度よりも高い半導体装置。
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