JPWO2018211398A1 - 半導体装置及び電子機器 - Google Patents
半導体装置及び電子機器 Download PDFInfo
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- JPWO2018211398A1 JPWO2018211398A1 JP2019518599A JP2019518599A JPWO2018211398A1 JP WO2018211398 A1 JPWO2018211398 A1 JP WO2018211398A1 JP 2019518599 A JP2019518599 A JP 2019518599A JP 2019518599 A JP2019518599 A JP 2019518599A JP WO2018211398 A1 JPWO2018211398 A1 JP WO2018211398A1
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- oxide
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- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 1
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- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
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Images
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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Abstract
Description
本実施の形態では、本発明の一態様に係る半導体装置について説明する。本発明の一態様に係る半導体装置は、半導体基板に形成されたトランジスタを有する層と、OSトランジスタを有する層と、が積層された構造を有する。
図1に、半導体装置10の構成例を示す。半導体装置10は、層20と、層20の上方に積層された層30を有する。層20は制御回路21を有し、層30は記憶回路MEMを有する。なお、層20と層30の間には、層間絶縁層を設けることができる。
Random Access Memory)、SRAM(Static Random Access Memory)などの揮発性メモリ、又は、フラッシュメモリ、磁気記憶装置(ハードディスクドライブ、磁気メモリなど)、ROM(Read Only Memory)などの不揮発性メモリを用いることができる。また、揮発性メモリと不揮発性メモリの両方を用いて構成することもできる。
図1には、層20上に記憶回路MEMを有する層30が1層設けられた構成例を示しているが、層20上に2層以上の層30を積層することもできる。図3に、層20上にN層(Nは2以上の整数)の層30(層30_1乃至30_N)が積層された構成を示す。層30_1乃至30_Nはそれぞれ、記憶回路MEM_1乃至記憶回路MEM_Nを有する。なお、記憶回路MEM_1乃至記憶回路MEM_Nの構成及び機能は、図1における記憶回路MEMと同様である。
図1には、層30に記憶回路MEMが設けられた構成例を示しているが、層30に設けられる回路は記憶回路MEMに限定されない。また、層30には機能の異なる複数の回路が設けられていてもよい。図5に、層30がNOSRAM、DOSRAM、FPGA、及びアナログ演算回路を有する構成例を示す。また、層20は制御回路25、制御回路26、制御回路27、及び制御回路28を有し、制御回路25、制御回路26、制御回路27、及び制御回路28はバスBUSと接続されている。
半導体装置10は、撮像装置としての機能を有していてもよい。図6に、撮像装置としての機能を有する半導体装置10の構成例を示す。図6に示す半導体装置10は、記憶回路MEMを有する層30(図1参照)の上方に、さらに層40が積層された構造を有する。
本実施の形態では、上記実施の形態で説明した半導体装置の具体的な構成例について、図7乃至図19を用いて説明する。
図7乃至図11は、本発明の一態様に係る、トランジスタ300(トランジスタ300a、トランジスタ300b、およびトランジスタ300c)、トランジスタ700、メモリセル600、を有する記憶装置の上面図および断面図である。ここで、メモリセル600は、トランジスタ200、トランジスタ500、および容量素子100を有する。
以下では、半導体装置に用いることができる構成材料について説明する。以下において、特段の記載を行わない場合、トランジスタ200に用いることができる構成材料は、トランジスタ500およびトランジスタ700に用いることができるものとする。
Layer Deposition)法などを用いて行うことができる。
絶縁体としては、絶縁性を有する酸化物、窒化物、酸化窒化物、窒化酸化物、金属酸化物、金属酸化窒化物、金属窒化酸化物などがある。
導電体としては、アルミニウム、クロム、銅、銀、金、白金、タンタル、ニッケル、チタン、モリブデン、タングステン、ハフニウム、バナジウム、ニオブ、マンガン、マグネシウム、ジルコニウム、ベリリウム、インジウム、ルテニウムなどから選ばれた金属元素を1種以上含む材料を用いることができる。また、リン等の不純物元素を含有させた多結晶シリコンに代表される、電気伝導度が高い半導体、ニッケルシリサイドなどのシリサイドを用いてもよい。
酸化物230として、酸化物半導体として機能する金属酸化物(以下、酸化物半導体ともいう。)を用いることが好ましい。以下では、本発明に係る酸化物230に適用可能な金属酸化物について説明する。
以下では、本発明の一態様で開示されるトランジスタに用いることができるCAC(Cloud−Aligned Composite)−OSの構成について説明する。
matrix composite)と呼称することもできる。
酸化物半導体(金属酸化物)は、単結晶酸化物半導体と、それ以外の非単結晶酸化物半導体と、に分けられる。非単結晶酸化物半導体としては、例えば、CAAC−OS(c−axis aligned crystalline oxide semiconductor)、多結晶酸化物半導体、nc−OS(nanocrystalline oxide semiconductor)、擬似非晶質酸化物半導体(a−like OS:amorphous−like oxide semiconductor)および非晶質酸化物半導体などがある。
続いて、上記金属酸化物をトランジスタのチャネル形成領域に用いる場合について説明する。
ここで、金属酸化物中における各不純物の影響について説明する。
以下では、図13乃至図19を用いて、本発明の一態様に係る半導体装置の一例について説明する。
本実施の形態では、上記実施の形態で説明した半導体装置が搭載された電子機器の例について説明する。
Claims (9)
- 第1の層と、前記第1の層の上方の第2の層と、を有し、
前記第1の層は、制御回路を有し、
前記第2の層は、記憶回路を有し、
前記制御回路は、前記記憶回路の動作を制御する機能を有し、
前記記憶回路は、複数のメモリセルと、駆動回路と、を有し、
前記メモリセルは、第1のトランジスタと、第2のトランジスタと、容量素子と、を有し、
前記第1のトランジスタのソース又はドレインの一方は、前記第2のトランジスタのゲート及び前記容量素子と電気的に接続され、
前記制御回路は、半導体基板に形成されたトランジスタを有し、
前記第1のトランジスタと前記第2のトランジスタは、チャネル形成領域に金属酸化物を有する半導体装置。 - 請求項1において、
前記駆動回路は、第1の駆動回路と、第2の駆動回路と、を有し、
前記第1の駆動回路は、前記メモリセルを選択する機能を有し、
前記第2の駆動回路は、前記メモリセルにデータを書き込む機能と、前記メモリセルに記憶されたデータを読み出す機能と、を有し、
前記第1の駆動回路及び前記第2の駆動回路は、前記制御回路と電気的に接続され、
前記第1の駆動回路及び前記第2の駆動回路は、チャネル形成領域に金属酸化物を有するトランジスタを有する半導体装置。 - 請求項1又は2において、
前記第1のトランジスタと第2のトランジスタの極性は同一である半導体装置。 - 請求項1又は2において、
前記第1のトランジスタと前記第2のトランジスタは同一の絶縁層上に形成されている半導体装置。 - 請求項1又は2において、
前記制御回路は、クロック生成回路と、タイミングコントローラと、を有する半導体装置。 - 請求項1又は2において、
第1の層は、プロセッサと、周辺回路と、電源回路と、を有し、
前記プロセッサ、前記周辺回路、及び前記電源回路は、前記半導体基板に形成されたトランジスタを有する半導体装置。 - 請求項1又は2に記載の半導体装置を有する電子機器。
- 請求項1又は2において、前記第2の層の上方に更に第3の層を有し、
前記第3の層は、受光部を有する半導体装置。 - 第1の層は更に、第2の制御回路を有し、
第2の制御回路は、受光部に電気的に接続されている半導体装置。
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