JPWO2017149580A1 - Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device - Google Patents

Abstract

An object of the present invention is to provide an excellent effect of preventing current deterioration in a silicon carbide bipolar device having a mesa structure.
In the present invention, the first region where the concentration of the p-type impurity is higher than the concentration of the n-type impurity formed inside the mesa structure, and the n-type impurity concentration than the concentration of the p-type impurity along the side surface of the mesa structure. By providing the second region having a higher type impurity concentration, the above-described problem is solved.

Description

  The present invention relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device, and more particularly to a silicon carbide bipolar element having a mesa structure and a method for manufacturing the same.

The most important issue in the implementation of a sustainable society, the depletion of energy resources are excessive emissions of greenhouse gases such as CO _2. For this reason, a power converter having excellent energy efficiency and low CO ₂ emission has become important. Many of the power conversion devices are configured by a power module in which an insulated gate bipolar transistor (IGBT) as a switching element and a PiN diode (PND) as a rectifying element are connected in parallel. For this reason, the loss reduction of the semiconductor element is directly linked to energy saving of the power converter.

  As a technique for reducing the loss of a semiconductor element, a method of forming an element using 4H type silicon carbide (4H—SiC, hereinafter referred to as SiC) has been attracting attention. However, the current silicon carbide bipolar device has a problem of deterioration of energization in which the voltage increases when current flows in the forward direction. The cause is that during the epitaxial growth or device manufacturing process, BPD (Basal Plane Dislocation) enters the silicon carbide crystal, and when forward current flows, the BPD expands due to recombination of electrons and holes, resulting in a stacking fault area. This is because of the increase. In particular, BPD is likely to occur on the mesa wall in the mesa processing process of the bipolar element. In the technique disclosed in Patent Document 1, in a silicon carbide bipolar semiconductor device having a mesa structure, an n-type layer is formed by forming a p-type layer or a high-resistance amorphous layer on a mesa wall portion or a mesa peripheral portion. An energization deterioration preventing layer is provided that spatially separates the pn junction interface between the drift layer and the p-type charge injection layer and the surface of the mesa wall portion or the mesa peripheral portion.

JP 2007-165604 A

  However, in the technique disclosed in Patent Document 1, since the mesa wall portion is p-type, holes can be generated in the vicinity of the mesa wall portion. Since holes can be generated in the vicinity of the mesa wall, the effect of preventing conduction deterioration is limited by recombination of electrons and holes.

  Therefore, an object of the present invention is to provide an excellent effect of preventing current deterioration in a silicon carbide bipolar device having a mesa structure.

  In the present invention, the first region where the concentration of the p-type impurity is higher than the concentration of the n-type impurity formed inside the mesa structure, and the n-type impurity concentration than the concentration of the p-type impurity along the side surface of the mesa structure. By providing the second region having a higher type impurity concentration, the above-described problem is solved.

  According to the present invention, it is possible to obtain an excellent effect of preventing current deterioration and to provide a highly reliable silicon carbide semiconductor device.

It is a top view of n-type SiC-PND which concerns on Example 1 of this invention. It is sectional drawing of n-type SiC-PND which concerns on Example 1 of this invention. FIG. 6 is a cross sectional view of a process for manufacturing the silicon carbide semiconductor device of Example 1; FIG. 6 is a cross sectional view of a process for manufacturing the silicon carbide semiconductor device of Example 1; FIG. 6 is a cross sectional view of a process for manufacturing the silicon carbide semiconductor device of Example 1; FIG. 6 is a cross sectional view of a process for manufacturing the silicon carbide semiconductor device of Example 1; It is a figure which shows the measurement result of a time-dependent change of a forward voltage. 6 is a cross sectional view of a silicon carbide semiconductor device of Example 2. FIG. 6 is a cross sectional view of a silicon carbide semiconductor device of Example 3. FIG. It is a top view of n-type SiC-PND which concerns on Example 4 of this invention. It is a top view of n-type SiC-PND which concerns on Example 4 of this invention. FIG. 7 is a main part sectional view of a silicon carbide semiconductor device of Example 4; FIG. 7 is a main part sectional view of a silicon carbide semiconductor device of Example 4; It is sectional drawing of GTO which concerns on Example 5 of this invention. It is a figure which shows the example of application of the silicon carbide semiconductor device of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, in the embodiments described below, a silicon carbide PiN diode (SiC-PND) or a silicon carbide gate turn-off thyristor (SiC-GTO) among silicon carbide bipolar elements having a mesa structure will be described as an example. Is not limited to SiC-PND or SiC-GTO. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  An n-type SiC-PND 100 that is a silicon carbide semiconductor device of the present embodiment will be described with reference to FIGS. FIG. 1 is a top view of the n-type SiC-PND 100 of the present embodiment. FIG. 2 is a cross-sectional view of the SiC-PND 100 of the present embodiment at a location corresponding to the broken line A-A ′ in FIG. 1.

  As shown in FIG. 2, the n-type SiC-PND 100 of this embodiment is a silicon carbide semiconductor layer having a lower impurity concentration than the n-type bulk 4H-SiC substrate 101 on the n-type bulk 4H-SiC substrate 101. An n-type drift layer 102 is formed. Further, a hole injection layer 103 which is a silicon carbide layer is formed on the n-type drift layer 102.

The n-type bulk 4H—SiC substrate 101 is an n-type single crystal SiC layer containing nitrogen (N), phosphorus (P), or the like as an impurity, and can be manufactured by, for example, a sublimation method. The impurity concentration of the n-type bulk 4H—SiC substrate 101 is, for example, 1 × 10 ¹⁶ cm ⁻³ or more and less than 2 × 10 ²⁰ cm ⁻³ . The thickness of the n-type bulk 4H—SiC substrate 101 is, for example, not less than 100 μm and less than 1000 μm.

The n-type drift layer 102 can be formed by, for example, an epitaxial growth method. The concentration of impurities such as nitrogen (N) and phosphorus (P) contained in the n-type drift layer 102 is, for example, 1 × 10 ¹³ cm ⁻³ or more and less than 1 × 10 ¹⁸ cm ⁻³ .

The hole injection layer 103 is a silicon carbide layer containing p-type impurities such as aluminum (Al) and boron (B). The concentration of the p-type impurity in the hole injection layer 103 is, for example, 1 × 10 ¹⁷ cm ⁻³ or more and less than 1 × 10 ²¹ cm ⁻³ . In the hole injection layer 103, the concentration of the p-type impurity is higher than the concentration of the n-type impurity. The hole injection layer 103 is a p-type semiconductor layer and is in pn junction with the n-type drift layer 102. The hole injection layer 103 can be formed by, for example, an epitaxial growth method. In the epitaxial growth method, a p-type impurity can be selectively introduced into the hole injection layer 103. The hole injection layer 103 can also be formed by ion implantation of p-type impurities into the n-type semiconductor layer. The thickness of the hole injection layer 103 is, for example, not less than 0.5 μm and less than 30 μm.

As shown in FIG. 2, the hole injection layer 103 and the energization path from the hole injection layer 103 to the n-type drift layer 102 are provided in the mesa structure. As shown in FIGS. 1 and 2, a p-type electric field relaxation layer 104 is formed around the mesa structure including under the side surface of the mesa structure. As shown in FIG. 2, the p-type field relaxation layer 104 is in contact with the hole injection layer 103. The p-type field relaxation layer 104 can be formed by implanting p-type impurity ions, and the impurity concentration is, for example, 1 × 10 ¹⁴ cm ⁻³ or more and less than 5 × 10 ¹⁸ cm ⁻³ . When a reverse voltage is applied by the p-type field relaxation layer 104, a depletion layer spreads in the p-type field relaxation layer 104, and the electric field concentration at the end of the hole injection layer 103 can be relaxed. The pressure resistance performance of the SiC-PND 100 can be improved.

In the present application, the side portion of the mesa structure is referred to as a mesa wall portion 108, and a partial region on the surface of the p-type field relaxation layer 104 from the lower end portion of the mesa wall portion 108 is referred to as a mesa lower end peripheral portion 109. A part of the surface of the hole injection region 103 from the upper end of the region is called a mesa upper end peripheral portion 111. The width W _n1 of the mesa lower end peripheral portion 109 is not less than 1 nm and less than 100 μm, and can be set to 10 μm, for example. The width W _n2 of the mesa upper end peripheral portion 111 is 1 nm or more and less than 100 μm, and can be set to 5 μm, for example.

The n-type SiC-PND 100 includes an n-type current prevention layer 110 along the mesa upper end peripheral portion 111, the mesa wall portion 108, and the mesa lower end peripheral portion 109. In the n-type current blocking layer 110, the n-type impurity concentration is higher than the p-type impurity concentration. The thickness T _n of the n-type current prevention layer 110 is not less than 1 nm and less than 2 μm, and can be, for example, 100 nm. The n-type current blocking layer 110 can be formed by counter doping with n-type impurities. Since the n-type current prevention layer 110 is an n-type semiconductor layer, it is pn-junction with the hole injection layer 103 and the p-type field relaxation layer 104 of the p-type semiconductor layer. Since the n-type current prevention layer 110 is formed along the mesa upper end peripheral part 111, the mesa wall part 108, and the mesa lower end peripheral part 109, generation of holes can be prevented in the entire periphery of the mesa wall part 108. .

On the top of the mesa structure, an anode electrode 106 is provided in contact with the hole injection layer 103. A cathode electrode 107 is provided on the back surface of the n-type bulk 4H—SiC substrate 101. A passivation film 105 is provided on the surface of the n-type SiC-PND 100 except where the anode electrode 106 is provided. The passivation film 105 can be formed of SiO ₂ or silicon nitride.

  A method for manufacturing the n-type SiC-PND 100 of this embodiment will be described with reference to cross-sectional views of the manufacturing process shown in FIGS. As shown in FIG. 3A, an n-type silicon carbide layer serving as an n-type drift layer 102 having an impurity concentration lower than that of the n-type bulk 4H-SiC substrate 101 is formed on the n-type bulk 4H-SiC substrate 101. A silicon carbide wafer is prepared, and a p-type silicon carbide layer to be the hole injection layer 103 is formed on the n-type semiconductor layer. Next, as shown in FIG. 3B, a mesa structure is formed on the prepared silicon carbide wafer by removing the p-type silicon carbide layer and the n-type silicon carbide layer in the surrounding portions by dry etching.

  After that, as shown in FIG. 3C, for example, aluminum is ion-implanted as a p-type impurity around the mesa structure from the bottom surface and side surface of the mesa structure by, for example, a mask process, to thereby form the p-type field relaxation layer 104. Form. Here, the p-type electric field relaxation layer 104 is formed to extend below the hole injection layer 103 so as to be in contact with the hole injection layer 103. Next, as shown in FIG. 3D, for example, nitrogen as an n-type impurity is ionized by a mask process on the mesa wall portion 108 and the peripheral portion of the mesa upper end peripheral portion 111 and the mesa lower end peripheral portion 109. By implantation, an n-type current prevention layer 110 that is an n-type semiconductor layer is formed. Here, when the p-type electric field relaxation layer 104 is formed to extend below the hole injection layer 103 so as to be in contact with the hole injection layer 103, ion implantation is also performed from the mesa wall portion 108. Around the portion 108, a portion having a p-type impurity concentration that is the sum of the p-type impurity concentration of the hole injection layer 103 and the p-type impurity concentration of the p-type field relaxation layer 104 is formed. Therefore, when the n-type current blocking layer 110 is formed, an n-type impurity having a concentration higher than the sum of the p-type impurity concentration of the hole injection layer 103 and the p-type impurity concentration of the p-type field relaxation layer 104 is added. inject. The n-type impurity concentration of the n-type current blocking layer 110 is higher than the n-type impurity concentration of the n-type drift layer 102.

  Thereafter, annealing is performed to activate the implanted ions. Next, the anode electrode 106, the passivation film 105, and the cathode electrode 107 are formed to obtain the structure shown in FIG.

  The effect of the present invention is shown in FIG. In FIG. 4, the time-dependent change of the forward voltage due to the energization of the SiC-PND provided with the n-type current prevention layer 110 is indicated by a solid line, and as a comparative example, the energization of the SiC-PND without the n-type current prevention layer 110 provided. The change over time in the forward voltage is shown by broken lines. From FIG. 4, in the diode in which the n-type current prevention layer 110 of the comparative example is not provided, the forward voltage increases by energization, whereas when the n-type current prevention layer 110 is provided, the mesa wall portion In the vicinity of 108, no holes are generated due to the n-type current blocking layer 110, so that the expansion of the BPD is suppressed and the forward voltage hardly increases. Thus, according to the present invention, it is possible to obtain an excellent effect of preventing energization deterioration and to provide a highly reliable silicon carbide semiconductor device.

FIG. 5 shows a semiconductor device of this example. The difference from the n-type SiC-PND 100 of the first embodiment of the semiconductor device shown in FIG. 5 is that a p-type resistance reduction layer 501 is formed under the anode electrode 106. The impurity concentration of the p-type resistance reduction layer 501 is higher than the impurity concentration of the hole injection layer 103, and is, for example, 1 × 10 ¹⁷ cm ⁻³ or more and less than 1 × 10 ²² cm ⁻³ . The p-type resistance reduction layer 501 can be formed by ion implantation of, for example, aluminum as a p-type impurity. The outer peripheral portion of the p-type resistance reduction layer 501 may overlap with the n-type current prevention layer 110, but may be separated. By forming the p-type resistance reduction layer 501 having a high concentration of p-type impurities, the contact resistance of the anode electrode 106 can be reduced.

FIG. 6 shows a semiconductor device of this example. The difference from the n-type SiC-PND 100 of the first embodiment of the semiconductor device shown in FIG. 6 is that an n-type BPD reduction layer 601 is formed between the n-type bulk 4H-SiC substrate 101 and the n-type drift layer 102. Is a point. The thickness of the n-type BPD reduction layer 601 is, for example, 0.5 μm or more and less than 50 μm, and the impurity concentration is, for example, 1 × 10 ¹⁵ cm ⁻³ or more and less than 1 × 10 ²⁰ cm ⁻³ . By the n-type BPD reduction layer 601, a part of the BPD existing in the n-type bulk substrate 1 is changed to TED (Threading Edge Dislocation), and the BPD in the n-type drift layer 102 and the hole injection layer 103 is greatly reduced. can do.

  In this example, a modification of the termination structure of the silicon carbide semiconductor device of Examples 1 to 3 is shown. 7A and 7B are top views of the silicon carbide semiconductor device of this example.

  FIG. 7A shows an example of a FLR (Field Limiting Ring) structure. FIG. 8A shows a cross-sectional view of the main part at a location corresponding to the broken line B-B ′ in FIG. As shown in FIG. 8A, a p-type semiconductor region 701a, a p-type semiconductor region 701b, and a p-type semiconductor region 701c are provided in a ring shape outside the p-type field relaxation layer 104, and an FLR structure is formed. Is formed. Since the p-type electric field relaxation layer 104 is surrounded by the FLR structure, the electric field can be more effectively relaxed.

  FIG. 7B is an example of a JTE (Junction Termination Extension) structure. FIG. 8B shows a cross-sectional view of the main part at a location corresponding to the broken line C-C ′ in FIG. As shown in FIG. 8B, on the outside of the p-type field relaxation layer 104, a p-type semiconductor region 701d having a lower p-type impurity concentration than the p-type field relaxation layer 104, and a p-type semiconductor region 701d. A p-type semiconductor region 701e having a low impurity concentration and a p-type semiconductor region 701f having a lower p-type impurity concentration than the p-type semiconductor region 701d are provided, and a JTE structure is formed. Since the p-type electric field relaxation layer 104 is connected to the JTE structure, the electric field can be more effectively relaxed.

  In this embodiment, an example of a gate turn-off thyristor (GTO) to which the present invention is applied is shown. FIG. 9 shows a cross-sectional structure of the SiC-GTO of this example.

  In the SiC-GTO of this embodiment, a p-type field stop layer 1001 is formed on an n-type bulk 4H-SiC substrate 101. A p-type drift layer 1002 is formed on the p-type field stop layer 1001. An n-type conductive layer 1003 is formed on the p-type drift layer 1002. A hole injection layer 103 is formed on the n-type conductive layer 1003. An n-type conductive layer 1004 is formed on the outer periphery of the mesa structure of the n-type conductive layer 1003. A gate electrode 1005 is formed on the n-type conductive layer 1004.

The n-type bulk 4H—SiC substrate 101 is an n-type single crystal SiC layer containing nitrogen (N), phosphorus (P), or the like formed by, for example, a sublimation method. The thickness of the n-type bulk 4H—SiC substrate 101 is, for example, not less than 100 μm and less than 1000 μm. The impurity concentration of the n-type bulk 4H—SiC substrate 101 is, for example, 1 × 10 ¹⁶ cm ⁻³ or more and less than 2 × 10 ²⁰ cm ⁻³ .

The p-type field stop layer 1001 is a layer containing a p-type impurity such as aluminum (Al) or boron (B) formed by an epitaxial growth method, for example. The concentration of the p-type impurity in the p-type field stop layer 1001 is, for example, 1 × 10 ¹⁵ cm ⁻³ or more and less than 1 × 10 ¹⁹ cm ⁻³ .

The p-type drift layer 1002 can be formed by, for example, an epitaxial growth method. The concentration of the p-type impurity in the p-type drift layer 1002 is, for example, 1 × 10 ¹² cm ⁻³ or more and less than 1 × 10 ¹⁸ cm ⁻³ .

The n-type conductive layer 1003 can be formed by, for example, an epitaxial growth method. The n-type impurity concentration of the n-type conductive layer 1003 is, for example, 1 × 10 ¹⁵ cm ⁻³ or more and less than 1 × 10 ¹⁹ cm ⁻³ .

The hole injection layer 103 can be formed by, for example, an epitaxial growth method. The thickness of the hole injection layer 103 is, for example, not less than 0.5 μm and less than 30 μm, and the impurity concentration is, for example, not less than 1 × 10 ¹⁷ cm ^{−3 and} less than 1 × 10 ²¹ cm ⁻³ .

  The n-type conductive layer 1004 can be formed by ion implantation of n-type impurities, for example.

  Similar to the first embodiment, the energization path from the hole injection layer 103 to the n-type conductive layer 1003 is inside the mesa structure. On the top of the mesa structure, an anode electrode 106 is provided in contact with the hole injection layer 103. A cathode electrode 107 is provided on the back surface of the n-type bulk 4H—SiC substrate 101.

  Similar to the first embodiment, the n-type current prevention layer 110 is provided along the mesa upper end peripheral portion 111, the mesa wall portion 108, and the mesa lower end peripheral portion 109. In the n-type current blocking layer 110, the n-type impurity concentration is higher than the p-type impurity concentration. The thickness of the n-type current prevention layer 110 is not less than 1 nm and less than 2 μm, and can be, for example, 100 nm. The n-type current blocking layer 110 can be formed by counter doping with n-type impurities.

  FIG. 10 shows an application example of the silicon carbide semiconductor device shown in the first to fourth embodiments. As shown in FIG. 10, the power conversion device of this embodiment can be used for, for example, a railway vehicle.

  FIG. 10 is a block diagram showing an example of a three-phase motor system applied to a railway vehicle. Electric power is supplied to the railway vehicle from the overhead line RT via the panda graph PG. The high-voltage AC voltage of the overhead line RT is, for example, 25 kV or 15 kV. This high-voltage AC voltage is stepped down to an AC voltage of, for example, 3.3 kV by the insulated main transformer MTR. The stepped-down AC voltage is forward converted to a DC voltage of 3.3 kV by the converter AC / DC. Thereafter, the DC voltage is converted into an AC voltage by the inverter DC / AC via the capacitor CL, and a desired three-phase AC voltage is output to the three-phase motor M3, thereby driving the three-phase motor M3. Reference sign WHL indicates a wheel.

  Here, the n-type SiC-PND 100 of Examples 1 to 4 can be applied to the free-wheeling diode FRD connected in parallel to the IGBT of the converter AC / DC that constitutes the three-phase motor system of the railway vehicle in FIG. By applying the n-type SiC-PND 100, the leakage current is reduced, so that it is possible to provide a highly efficient power converter with low loss.

  Further, since the power conversion device has a small loss due to the effect of the present invention, the number of heat radiation fins can be reduced, and the volume of the three-phase motor system can be reduced. As a result, for example, the floor of the railway vehicle can be reduced by downsizing the underfloor parts including the three-phase motor system. In addition, for example, by downsizing the underfloor parts, it is possible to secure a space where a storage battery SB can be newly installed in a part of the railway vehicle. Therefore, when the vehicle is decelerated, power is transferred to the overhead line RT via the wheels WHL. In addition to returning, it is also possible to store power in the storage battery SB. As a result, the regeneration efficiency of the railway vehicle can be improved. In other words, the life cycle cost of the railway system can be reduced.

  100: n-type SiC-PND, 101: n-type bulk 4H-SiC substrate, 102: n-type drift layer, 103: hole injection layer, 104: p-type electric field relaxation layer, 105: passivation film, 106: anode electrode, 107 : Cathode electrode, 108: mesa wall portion, 109 mesa lower end peripheral portion, 110: n-type current prevention layer, 111: mesa upper end peripheral portion.

Claims (15)

A first region having a p-type impurity concentration higher than an n-type impurity concentration formed inside the mesa structure;
A second region having a higher n-type impurity concentration than a p-type impurity concentration along a side surface of the mesa structure;
A silicon carbide semiconductor device comprising: The silicon carbide semiconductor device according to claim 1,
A silicon carbide semiconductor device, wherein an anode electrode is formed on the mesa structure. The silicon carbide semiconductor device according to claim 1,
A silicon carbide semiconductor device comprising a third region connected to the first region, the third region having a higher p-type impurity concentration than the n-type impurity concentration under the side surface. The silicon carbide semiconductor device according to claim 3,
The silicon carbide semiconductor device, wherein the second region is in contact with the first region and the third region. The silicon carbide semiconductor device according to claim 3,
The silicon carbide semiconductor device, wherein the third region is surrounded by an FLR structure. The silicon carbide semiconductor device according to claim 3,
The silicon carbide semiconductor device, wherein the third region is connected to a JTE structure. The silicon carbide semiconductor device according to claim 1,
A silicon carbide semiconductor device comprising an n-type drift layer forming a pn junction with the first region. The silicon carbide semiconductor device according to claim 1,
A silicon carbide semiconductor device comprising a gate electrode outside the mesa structure. A p-type first semiconductor region formed inside the mesa structure;
Along the side surface of the mesa structure, an n-type second semiconductor region;
A silicon carbide semiconductor device comprising: The silicon carbide semiconductor device according to claim 9,
A silicon carbide semiconductor device, wherein an anode electrode is formed on the mesa structure. The silicon carbide semiconductor device according to claim 9,
A silicon carbide semiconductor device comprising a third semiconductor region connected to the first semiconductor region, the p-type impurity concentration being higher than the n-type impurity concentration under the side surface. The silicon carbide semiconductor device according to claim 11,
The silicon carbide semiconductor device, wherein the second semiconductor region is in contact with the first semiconductor region and the third semiconductor region. The silicon carbide semiconductor device according to claim 9,
A silicon carbide semiconductor device comprising a gate electrode outside the mesa structure. Preparing a wafer having a second silicon carbide layer containing a p-type impurity at a second concentration on the first silicon carbide layer containing an n-type impurity at a first concentration;
Forming a mesa structure including the second silicon carbide layer on the wafer surface;
Injecting p-type impurities at a third concentration into the side and bottom surfaces of the mesa structure;
Injecting an n-type impurity at a fourth concentration into the side surface of the mesa structure;
The method for manufacturing a silicon carbide semiconductor device, wherein the fourth concentration is higher than a sum of the first concentration and the second concentration. A method for manufacturing a silicon carbide semiconductor device according to claim 14,
A method of manufacturing a silicon carbide semiconductor device, comprising forming a cathode electrode on a back side of the wafer.

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