JP2009010120A - Silicon carbide bipolar semiconductor device - Google Patents

Silicon carbide bipolar semiconductor device Download PDF

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JP2009010120A
JP2009010120A JP2007169263A JP2007169263A JP2009010120A JP 2009010120 A JP2009010120 A JP 2009010120A JP 2007169263 A JP2007169263 A JP 2007169263A JP 2007169263 A JP2007169263 A JP 2007169263A JP 2009010120 A JP2009010120 A JP 2009010120A
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silicon carbide
highly doped
charge injection
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JP5249532B2 (en
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Toshiyuki Mitsuyanagi
俊之 三柳
Shuichi Tsuchida
秀一 土田
Isao Kamata
功穂 鎌田
Ryusuke Ishii
竜介 石井
Koji Nakayama
浩二 中山
Yoshitaka Sugawara
良孝 菅原
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Central Research Institute of Electric Power Industry
Kansai Electric Power Co Inc
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Kansai Electric Power Co Inc
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Abstract

<P>PROBLEM TO BE SOLVED: To suppress a stacking fault and an area magnification thereof which make a defective nucleus existing near a front surface of an element as a starting point, and thereby to suppress an increase in forward voltage, in a silicon carbide bipolar semiconductor device with a mesa structure. <P>SOLUTION: The silicon carbide bipolar semiconductor device is constituted by laminating the following in order: a first conductivity-type silicon carbide single crystal substrate; a first conductivity-type silicon carbide drift layer; a second conductivity-type silicon carbide charge injection layer; and a second conductivity-type high doping layer with a doping density higher than that of the silicon carbide charge injection layer. This device is also characterized in that there is provided the mesa structure from the silicon carbide drift layer to an element surface at the high doping layer side, and the thickness of the high doping layer is 15 nm to 1.5 μm, and the maximum doping density in the high doping layer is 1×10<SP>20</SP>cm<SP>-3</SP>to 2×10<SP>21</SP>cm<SP>-3</SP>. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、バイポーラ型半導体装置に関し、特に、炭化珪素バイポーラ型半導体に関する。   The present invention relates to a bipolar semiconductor device, and more particularly to a silicon carbide bipolar semiconductor.

炭化珪素(SiC)などのワイドギャップ半導体材料は、シリコン(Si)に比べて絶縁破壊強度が約10倍高いなど各種の優れた特性を有しており、高い耐電圧特性を必要とする高耐圧パワー半導体装置に好適な材料として注目されている。   Wide-gap semiconductor materials such as silicon carbide (SiC) have various excellent characteristics such as about 10 times higher dielectric breakdown strength than silicon (Si), and high breakdown voltage that requires high withstand voltage characteristics. It attracts attention as a suitable material for power semiconductor devices.

pnダイオードやバイポーラトランジスタ、GTO、GCTなどのバイポーラ半導体素子は、ショットキーダイオードやMOSFETなどのユニポーラ半導体素子に比べてビルトイン電圧が高いが、少数キャリアの注入によるドリフト層の伝導度変調により抵抗が大幅に小さくなる。したがって、電力用途などの高電圧大電流領域では、損失を小さくするためにバイポーラ半導体素子が用いられている。   Bipolar semiconductor elements such as pn diodes, bipolar transistors, GTO, and GCT have higher built-in voltages than unipolar semiconductor elements such as Schottky diodes and MOSFETs, but their resistance is greatly increased by conductivity modulation of the drift layer by minority carrier injection. Becomes smaller. Therefore, bipolar semiconductor elements are used to reduce loss in high voltage and large current regions such as power applications.

SiCでこれらのバイポーラ半導体素子を構成すると、Si素子に比べて格段に優れた性能を実現できる。例えば、SiCで構成したpnダイオードは、10kVの高耐圧素子の場合、Siで構成したpnダイオードに比べて順方向電圧が約1/3と低く、オフ時の速度に相当する逆回復時間が約1/20以下と高速であり、電力損失を約1/5以下に低減でき省エネルギー化に大きく貢献できる。   When these bipolar semiconductor elements are made of SiC, it is possible to achieve performance that is significantly superior to Si elements. For example, in the case of a pn diode composed of SiC, in the case of a high breakdown voltage element of 10 kV, the forward voltage is about 1/3 lower than that of a pn diode composed of Si, and the reverse recovery time corresponding to the off-time speed is about The speed is as high as 1/20 or less, and the power loss can be reduced to about 1/5 or less, which can greatly contribute to energy saving.

SiC pnダイオード以外のSiCバイポーラ素子、例えばSiCnpnトランジス
タ、SiC SIAFET、SiC SIJFETなどについても同様に電力損失が低減されることが報告されている(非特許文献1)。この他、ドリフト層として反対極性をもつp型半導体層を用いたSiCGTOなども報告されている(非特許文献2)。
It has also been reported that power loss is similarly reduced for SiC bipolar elements other than SiC pn diodes, such as SiC npn transistors, SiC SIAFETs, and SiC SIJFETs (Non-Patent Document 1). In addition, SiCGTO using a p-type semiconductor layer having an opposite polarity as a drift layer has also been reported (Non-Patent Document 2).

SiCを用いた従来のpnダイオードとしては、プレーナ構造の高耐圧ダイオード(非特許文献3)、メサ構造を形成したもの(非特許文献4)などがある。図4は、メサ構造を形成したpnダイオードの概略を示した断面図である。このpnダイオードでは、電荷を注入するp+型電荷注入層4とn-型ドリフト層3との間のpn接合をエピタキシャル成長技術で形成した後、素子分離を行うために反応性イオンエッチング等によりメサ構造10を形成している。このメサ構造10は、例えば、n-型ドリフト層3の全面に形成した厚さ約3μmのp+型電荷注入層4の両端部分を深さ4μmまでメサエッチングで除去することにより形成することができる。図4においては、素子表面の保護を目的とした酸化膜7、p+型電荷注入層4の上に設けられたアノード電極8、n+基板の裏面に設けられたカソード電極9が示されている。メサ構造10を形成した後、電界集中を緩和するための電界緩和構造6を形成することで、高耐圧(例えば8.3kV)のpnダイオードが得られる。
国際公開 03/038876号パンフレット 松波弘之編著 「半導体SiC技術と応用」 日刊工業新聞社 2003年3月31日 218−221頁 マテリアルスサイエンス フォーラム(Materials Science Forum) ボリューム389−393 2000年 1349−1352頁 International Conference on Silicon Carbide, III-Nitride and Related Materialsの予稿集 1997年 136−137頁 マテリアルスサイエンス フォーラム(Materials Science Forum)ボリューム483−485 2005年 969−972頁 ジャーナルオブ アプライド フィジックス(Journal of Applied Physics) ボリューム95 No.3 2004年 1485−1488頁 ジャーナルオブ アプライド フィジックス(Journal of Applied Physics) ボリューム92 No.8 2004年 4699−4704頁 ジャーナルオブ クリスタル グロウス(Journal of Crystal Growth) ボリューム262 2004年 130−138頁 ジャーナルオブ アプライド フィジックス(Journal of Applied Physics) ボリューム96 No.9 2004年 4916−4922頁
As conventional pn diodes using SiC, there are a planar high-voltage diode (Non-patent Document 3), a mesa-structured diode (Non-patent Document 4), and the like. FIG. 4 is a cross-sectional view schematically showing a pn diode having a mesa structure. In this pn diode, a pn junction between the p + type charge injection layer 4 for injecting charges and the n type drift layer 3 is formed by an epitaxial growth technique, and then mesa is formed by reactive ion etching or the like for element isolation. A structure 10 is formed. The mesa structure 10 can be formed, for example, by removing both end portions of the p + type charge injection layer 4 having a thickness of about 3 μm formed on the entire surface of the n type drift layer 3 to a depth of 4 μm by mesa etching. it can. In FIG. 4, an oxide film 7 for protecting the device surface, an anode electrode 8 provided on the p + type charge injection layer 4, and a cathode electrode 9 provided on the back surface of the n + substrate are shown. Yes. After the mesa structure 10 is formed, a pn diode having a high breakdown voltage (for example, 8.3 kV) can be obtained by forming the electric field relaxation structure 6 for relaxing the electric field concentration.
International Publication No. 03/038876 Pamphlet Edited by Hiroyuki Matsunami “Semiconductor SiC Technology and Applications” Nikkan Kogyo Shimbun, March 31, 2003, pages 218-221 Materials Science Forum Volume 389-393 2000 1349-1352 Proceedings of International Conference on Silicon Carbide, III-Nitride and Related Materials 1997, 136-137 Materials Science Forum Volume 483-485 2005 969-972 Journal of Applied Physics Volume 95 No. 3 2004 pages 1485-1488 Journal of Applied Physics Volume 92 No. 8 2004 4699-4704 Journal of Crystal Growth Volume 262 2004 130-138 Journal of Applied Physics Volume 96 No. 9 2004 4916-4922

図4のようなメサ構造を設けたpnダイオードでは、プレーナ構造のpnダイオードのように第2導電型電荷注入層であるp+型電荷注入層4をイオン打ち込みにより形成する
のではなく、エピタキシャル成長法により形成しているので、p+型電荷注入層4とその
周辺に形成される結晶欠陥は比較的少ない。そのため、このようなpnダイオードは、順バイアス時の電荷の注入効率が比較的高く、オン電圧が比較的小さい。
In the pn diode having the mesa structure as shown in FIG. 4, the p + type charge injection layer 4 as the second conductivity type charge injection layer is not formed by ion implantation unlike the planar structure pn diode, but the epitaxial growth method is used. Therefore, there are relatively few crystal defects formed in the p + type charge injection layer 4 and its periphery. Therefore, such a pn diode has a relatively high charge injection efficiency during forward bias and a relatively low on-voltage.

一方、図4のようなメサ構造を設けたpnダイオードの素子表面(例えば図4におけるp+型電荷注入層4の表面)は、ウエハのハンドリングや酸化処理、エッチング処理等の
プロセス工程の影響を受け易く、素子表面付近ではバルク内部に比べて図5に示すような欠陥核23が局部的に発生し易い。これらの欠陥核23は、通電時に発生する電子21と正孔22の再結合エネルギーによって積層欠陥(stacking fault)24へと変換される(上記の非特許文献5〜7)。この積層欠陥24は、三角形等の形状を有する面状の欠陥として発生し、その面積は通電時間の増加に伴って拡大する。
On the other hand, the element surface of the pn diode having the mesa structure as shown in FIG. 4 (for example, the surface of the p + type charge injection layer 4 in FIG. 4) is affected by process steps such as wafer handling, oxidation treatment, and etching treatment. The defect nucleus 23 as shown in FIG. 5 is likely to be locally generated near the element surface as compared with the inside of the bulk. These defect nuclei 23 are converted into stacking faults 24 by the recombination energy of electrons 21 and holes 22 generated during energization (Non-Patent Documents 5 to 7 above). The stacking fault 24 occurs as a planar defect having a shape such as a triangle, and its area increases with an increase in energization time.

ここで、図5を参照しながら具体的に説明すると、一般に電子・正孔対は、第1導電型ドリフト層であるn-型ドリフト層3からの電子21と第2導電型電荷注入層であるp+型電荷注入層4からの正孔22とが出会うpn界面11付近で形成され易い。しかし一部の電子21はp+型電荷注入層4の表面付近まで到達し、そこで正孔22と出会う場合があ
る。このとき、電子・正孔対が生成される際に放出されるエネルギーが、p+型電荷注入
層4の表面付近に多く局在する欠陥核23に与えられ、この欠陥核23を起点として積層欠陥24が発生し、さらに積層欠陥の面積拡大が進行する。
Here, a specific description will be given with reference to FIG. 5. Generally, the electron-hole pair is composed of electrons 21 from the n -type drift layer 3, which is the first conductivity type drift layer, and the second conductivity type charge injection layer. It is easy to form near the pn interface 11 where holes 22 from a certain p + type charge injection layer 4 meet. However, some of the electrons 21 reach the vicinity of the surface of the p + type charge injection layer 4 and may encounter holes 22 there. At this time, the energy released when the electron / hole pairs are generated is given to the defect nuclei 23 localized in the vicinity of the surface of the p + -type charge injection layer 4. Defects 24 are generated, and the area of stacking faults further increases.

積層欠陥24の領域は、通電時に高抵抗領域として作用するため、積層欠陥24の面積拡大に伴ってバイポーラ素子の順方向電圧が増加することになる。その結果、電力損失の増大を招くこととなる。   Since the region of the stacking fault 24 acts as a high resistance region when energized, the forward voltage of the bipolar element increases as the area of the stacking fault 24 increases. As a result, the power loss increases.

また、図4に示されるpnダイオードと導電型が反対のpnダイオード、すなわち、p型が第1導電型でn型が第2導電型であるpnダイオードにおいても、一部の正孔がn+
型電荷注入層4の表面付近まで到達し、そこで電子と出会う場合がある。このとき、電子・正孔対が生成される際に放出されるエネルギーが、n+型電荷注入層4の表面付近に多く局在する欠陥核に与えられ、この欠陥核を起点として積層欠陥が発生し、さらに積層欠陥の面積拡大が進行する。したがって、この場合にも、図4に示されるpnダイオードの場合と同様に電力損失の増大を招くこととなる。
Also, in the pn diode having a conductivity type opposite to that of the pn diode shown in FIG. 4, that is, a pn diode in which the p-type is the first conductivity type and the n-type is the second conductivity type, some holes are n +
In some cases, it reaches the vicinity of the surface of the type charge injection layer 4 and encounters electrons there. At this time, the energy released when the electron / hole pairs are generated is given to the defect nuclei localized in the vicinity of the surface of the n + -type charge injection layer 4, and the stacking faults start from the defect nuclei. And the area expansion of stacking faults proceeds. Therefore, in this case as well, the power loss increases as in the case of the pn diode shown in FIG.

本発明は、メサ構造をもつ炭化珪素バイポーラ型半導体装置において、上に述べた積層欠陥の発生およびその面積拡大を抑制し、これにより順方向電圧の増加を抑制することを目的としている。   An object of the present invention is to suppress the occurrence of the above-described stacking fault and its area expansion in a silicon carbide bipolar semiconductor device having a mesa structure, thereby suppressing an increase in forward voltage.

そこで、本発明者らは、上述の課題を解決するために鋭意検討した結果、炭化珪素バイポーラ型半導体装置の第2導電型電荷注入層の表層に高ドーピング層を形成し、ドリフト層からの電子(または正孔)のうち該電界注入層において捕捉できなかった電子(または正孔)を該高ドーピング層にて捕捉し、積層欠陥の発生およびその面積拡大を抑制することによって、電力損失の小さい炭化珪素バイポーラ型半導体装置を得る方法を見出し、本発明を完成させるに至った。   Therefore, as a result of intensive studies to solve the above-described problems, the present inventors formed a highly doped layer on the surface layer of the second conductivity type charge injection layer of the silicon carbide bipolar semiconductor device, and formed electrons from the drift layer. (Or holes) of electrons (or holes) that could not be trapped in the electric field injection layer are trapped in the highly doped layer, thereby suppressing generation of stacking faults and area expansion, thereby reducing power loss. A method for obtaining a silicon carbide bipolar semiconductor device has been found and the present invention has been completed.

本発明の炭化珪素バイポーラ型半導体装置は、
第1導電型炭化珪素単結晶基板、エピタキシャル成長法により形成される第1導電型炭化珪素ドリフト層、エピタキシャル成長法により形成される第2導電型炭化珪素電荷注入層、および該炭化珪素電荷注入層よりもドーピング密度が高い第2導電型の高ドーピング層が、この順序にて積層してなり、
前記炭化珪素ドリフト層から前記高ドーピング層側の素子表面に至るメサ構造を有し、
前記高ドーピング層の厚さが15nm〜1.5μmであり、かつ、前記高ドーピング層における最大ドーピング密度が1×1020cm-3〜2×1021cm-3であることを特徴とする。
The silicon carbide bipolar semiconductor device of the present invention is
Than the first conductivity type silicon carbide single crystal substrate, the first conductivity type silicon carbide drift layer formed by the epitaxial growth method, the second conductivity type silicon carbide charge injection layer formed by the epitaxial growth method, and the silicon carbide charge injection layer A highly doped layer of the second conductivity type having a high doping density is laminated in this order,
Having a mesa structure from the silicon carbide drift layer to the element surface on the highly doped layer side;
The thickness of the high doping layer is 15 nm to 1.5 μm, and the maximum doping density in the high doping layer is 1 × 10 20 cm −3 to 2 × 10 21 cm −3 .

また、前記高ドーピング層は、イオン打ち込みにより形成することが好ましい。さらに、イオン打込みに際して、アルミニウム、窒素または燐をイオン種として用いることが好ましい。   The highly doped layer is preferably formed by ion implantation. Furthermore, it is preferable to use aluminum, nitrogen or phosphorus as the ion species in the ion implantation.

本発明の炭化珪素バイポーラ型半導体装置によれば、積層欠陥の発生およびその面積拡大が抑制され、これにより順方向電圧の増加を抑制することができる。   According to the silicon carbide bipolar semiconductor device of the present invention, the occurrence of stacking faults and the expansion of the area thereof are suppressed, thereby suppressing an increase in forward voltage.

以下、図1を参照しながら、本発明に係る炭化珪素バイポーラ型半導体装置(pnダイオード)およびその製造方法の一例を説明する。なお、同図は説明用のものであり、半導体装置の実際の寸法等は、本明細書の記載、および従来技術に基づいて当業者が理解する所による。   Hereinafter, an example of a silicon carbide bipolar semiconductor device (pn diode) and a method for manufacturing the same according to the present invention will be described with reference to FIG. This figure is for explanation, and the actual dimensions and the like of the semiconductor device will be understood by those skilled in the art based on the description in this specification and the prior art.

以下、第1導電型がn型、第2導電型がp型の場合を中心に説明する。
本発明の炭化珪素バイポーラ型半導体装置は、第1導電型炭化珪素単結晶基板、エピタキシャル成長法により形成される第1導電型炭化珪素ドリフト層、エピタキシャル成長法により形成される第2導電型炭化珪素電荷注入層、および該炭化珪素電荷注入層よりもドーピング密度が高い第2導電型の高ドーピング層が、この順序にて積層してなり、
前記炭化珪素ドリフト層から前記高ドーピング層側の素子表面に至るメサ構造を有し、
前記高ドーピング層の厚さが15nm〜1.5μmであり、かつ、前記高ドーピング層における最大ドーピング密度が1×1020cm-3〜2×1021cm-3であることを特徴としている。
Hereinafter, the case where the first conductivity type is n-type and the second conductivity type is p-type will be mainly described.
A silicon carbide bipolar semiconductor device of the present invention includes a first conductivity type silicon carbide single crystal substrate, a first conductivity type silicon carbide drift layer formed by an epitaxial growth method, and a second conductivity type silicon carbide charge injection formed by an epitaxial growth method. A layer, and a second conductivity type highly doped layer having a higher doping density than the silicon carbide charge injection layer, are laminated in this order,
Having a mesa structure from the silicon carbide drift layer to the element surface on the highly doped layer side;
The thickness of the high doping layer is 15 nm to 1.5 μm, and the maximum doping density in the high doping layer is 1 × 10 20 cm −3 to 2 × 10 21 cm −3 .

<各導電層>
第1導電型炭化珪素基板(n+基板)2は、昇華法(改良レーリー法)やCVD法等に
より得られたSiCバルク結晶をスライスして得られたn型のSiC単結晶基板である。
<Each conductive layer>
First conductivity type silicon carbide substrate (n + substrate) 2 is an n-type SiC single crystal substrate obtained by slicing a SiC bulk crystal obtained by a sublimation method (modified Rayleigh method), a CVD method or the like.

第1導電型ドリフト層(n-型ドリフト層)3は、このn+基板2の上に、エピタキシャル成長法によってn+基板2と同一の結晶型であるn-型のSiC単結晶膜を成長させることにより形成する。このn-型ドリフト層3は、窒素等をドーパントとして含有している
。高い耐電圧を得るためには第1導電型層のドーピング密度を低くする必要があることから、本発明の半導体装置において、n-型ドリフト層3のドナー密度は、好ましくは1×
1014〜6×1014cm-3である。
The first conductive type drift layer (n - -type drift layer) 3, on the n + substrate 2, n is the same crystal type and the n + substrate 2 by an epitaxial growth method - growing type SiC single crystal film To form. The n type drift layer 3 contains nitrogen or the like as a dopant. In order to obtain a high withstand voltage, it is necessary to reduce the doping density of the first conductivity type layer. Therefore, in the semiconductor device of the present invention, the donor density of the n type drift layer 3 is preferably 1 ×.
10 14 to 6 × 10 14 cm −3 .

このn-型ドリフト層3の上に、第2導電型電荷注入層(p+型電荷注入層)4を形成する。このp+型電荷注入層4は、硼素、アルミニウム等をドーパントとして含有している
。このp+型電荷注入層4は、エピタキシャル成長法によってp+型のSiC単結晶膜を成長させることにより形成する。本発明において、このp+型電荷注入層4のアクセプタ密
度は、好ましくは1×1018〜5×1019cm-3である。
A second conductivity type charge injection layer (p + type charge injection layer) 4 is formed on the n − type drift layer 3. The p + type charge injection layer 4 contains boron, aluminum, or the like as a dopant. The p + type charge injection layer 4 is formed by growing a p + type SiC single crystal film by an epitaxial growth method. In the present invention, the acceptor density of the p + type charge injection layer 4 is preferably 1 × 10 18 to 5 × 10 19 cm −3 .

次に、この第2導電型電荷注入層(p+型電荷注入層)4の上部表層に高ドーピング密
度を有する第2導電型高ドーピング層(p++型高ドーピング層)5を形成する。図2に示すように、n-型ドリフト層3からpn界面11を通過してp+型電荷注入層4に進入した電子21は、その大部分が、該電荷注入層4において正孔22に捕えられるが、その電子21の一部は該電荷注入層4において正孔22に捕えられることなく、さらに素子表面付近に向けて移動する。ここで、p++型高ドーピング層5を設けることにより、該電荷注入層4において正孔22に捕えられなかった電子21を、素子表面付近に到達する前にp++型高ドーピング層5に存在する正孔22にてより確実に捕えることができる。そのため、p+型電荷注入層4の表面付近に多く局在する欠陥核23の付近で電子・正孔対が生じる
ことが抑制され、積層欠陥24の発生および面積拡大を大幅に抑制することができ、順方向電圧の増加が抑制され、損失が小さくなる。
Next, a second conductivity type high doping layer (p ++ type high doping layer) 5 having a high doping density is formed on the upper surface layer of the second conductivity type charge injection layer (p + type charge injection layer) 4. As shown in FIG. 2, most of the electrons 21 that have entered the p + -type charge injection layer 4 through the pn interface 11 from the n -type drift layer 3 become holes 22 in the charge injection layer 4. Although trapped, a part of the electrons 21 are not trapped by the holes 22 in the charge injection layer 4 and further move toward the surface of the device. Here, by providing the p ++ type highly doped layer 5, the electrons 21 not captured by the holes 22 in the charge injection layer 4 are allowed to reach the p ++ type highly doped layer 5 before reaching the vicinity of the device surface. Can be more reliably captured by the holes 22 present in the. Therefore, the generation of electron / hole pairs in the vicinity of the defect nuclei 23 localized in the vicinity of the surface of the p + type charge injection layer 4 is suppressed, and the generation of the stacking fault 24 and the area expansion can be significantly suppressed. The increase of the forward voltage is suppressed, and the loss is reduced.

かかる観点から、p++型高ドーピング層5のドーピング密度は、p+型電荷注入層4に
比べて十分に高い必要があるため、その最小値を1×1020cm-3とすることが好ましい。一方、p型導電層のドーパントの一つであるアルミニウムのSiCに対する固溶限界は約2×1021cm-3であることから、その最大値を2×1021cm-3とすることが好ましい(非特許文献8)。
From this point of view, the doping density of the p ++ type highly doped layer 5 needs to be sufficiently higher than that of the p + type charge injection layer 4, so the minimum value thereof may be 1 × 10 20 cm −3. preferable. On the other hand, since the solid solubility limit of SiC, which is one of the dopants of the p-type conductive layer, with respect to SiC is about 2 × 10 21 cm −3 , the maximum value is preferably 2 × 10 21 cm −3. (Non-patent document 8).

このp++型高ドーピング層5の形成に際し、p+型電荷注入層4に硼素やアルミニウム
等をドーパントとして導入するが、高温熱処理下においてより安定したドーピング密度プロファイルを示すことからアルミニウムを導入することが特に好ましい。
In forming this p ++ type highly doped layer 5, boron, aluminum or the like is introduced into the p + type charge injection layer 4 as a dopant, but aluminum is introduced because it shows a more stable doping density profile under high temperature heat treatment. It is particularly preferred.

また、本発明においては、p++型高ドーピング層5の厚さを、p++型高ドーピング層5に含まれるドーパントの総数とp+型電荷注入層4のドーパント総数との関係から規定す
ることができる。ここでは、規定にあたっての条件を簡明にするため、p++型高ドーピング層5に含まれるドーパントの総数がp+型電荷注入層4のドーパント総数に比べ、同等
以上となるように設定した場合、すなわちp++型高ドーピング層5のドーピング密度と厚さの積(ドーズ量)がp+型電荷注入層4のドーピング密度と厚さの積(ドーズ量)に比
べ大きくなるように設定した場合について、p++型高ドーピング層5の厚さを検討する。この条件においては、電子を捕捉するという効果において、p++型高ドーピング層5はp+型電荷注入層4と同等以上の能力を有することになる。
Furthermore, provision in the present invention, the thickness of the p ++ type highly doped layer 5, the relationship between the dopant total of the total number and the p + -type charge injection layer 4 of the dopant contained in the p ++ type highly doped layer 5 can do. Here, in order to simplify the conditions for the definition, the total number of dopants contained in the p ++ type highly doped layer 5 is set to be equal to or greater than the total number of dopants in the p + type charge injection layer 4 That is, the product (dose amount) of the doping density and thickness of the p ++ type highly doped layer 5 is set to be larger than the product (dose amount) of the doping density and thickness of the p + type charge injection layer 4. For the case, the thickness of the p ++ type highly doped layer 5 is considered. Under these conditions, the p ++ type highly doped layer 5 has an ability equal to or higher than that of the p + type charge injection layer 4 due to the effect of trapping electrons.

例えば、p+型電荷注入層4の厚さを3μmとした場合、p+型電荷注入層4のドーズ量は3×1014〜1.5×1016cm-2となる。これに対し、p++型高ドーピング層5のドーピング密度が1×1020cm-3の場合、p+型電荷注入層4と同等のドーズ量を得るた
めには、p++型高ドーピング層5の厚さを30nm〜1.5μmとする必要がある。一方、p++型高ドーピング層5のドーピング密度を2×1021cm-3とした場合、p+型電荷
注入層4と同等以上のドーズ量を得るためには、p++型高ドーピング層5の厚さを1.5nm〜75nm以上とすれば良い。
For example, when the thickness of the p + type charge injection layer 4 is 3 μm, the dose of the p + type charge injection layer 4 is 3 × 10 14 to 1.5 × 10 16 cm −2 . In contrast, if the doping density of the p ++ type highly doped layer 5 is 1 × 10 20 cm -3, in order to obtain an equivalent dose of the p + -type charge injection layer 4, p ++ type highly doped The thickness of the layer 5 needs to be 30 nm to 1.5 μm. On the other hand, when the doping density of the p ++ type highly doped layer 5 and 2 × 10 21 cm -3, in order to obtain a p + -type charge injection layer 4 and the same or higher dose, p ++ type highly doped The thickness of the layer 5 may be 1.5 nm to 75 nm or more.

本発明において、p++型高ドーピング層5は、イオン打ち込みにより形成することができる。この場合、イオン打込み可能な最低エネルギーは10keV程度であるため、p++
型高ドーピング層5の厚さが15nm未満となるようなp++型高ドーピング層5を得ることは困難である。また、電極金属との合金化反応で消費されるSiCの厚さを考慮して、p++型高ドーピング層5の厚さが50nm以上であることが望ましい。
In the present invention, the p ++ type highly doped layer 5 can be formed by ion implantation. In this case, the minimum energy that can be implanted is about 10 keV, so p ++
It is difficult to obtain a p ++ type highly doped layer 5 in which the type highly doped layer 5 has a thickness of less than 15 nm. In consideration of the thickness of SiC consumed in the alloying reaction with the electrode metal, it is desirable that the thickness of the p ++ type highly doped layer 5 be 50 nm or more.

一方、高ドーピング密度のイオン注入層を厚くする場合にはドーズ量が大きくなり、かえって欠陥を生じさせるおそれがある。したがって、p++型高ドーピング層5の厚さが500nm以下であることが望ましい。 On the other hand, when the ion implantation layer having a high doping density is made thick, the dose is increased, which may cause defects. Therefore, it is desirable that the thickness of the p ++ type highly doped layer 5 is 500 nm or less.

以上の検討より、高ドーピング層5の最大ドーピング密度は1×1020〜2×1021cm-3とすることが好ましい。また、厚さについては、15nm〜1.5μmとすることが好ましいが、50nm〜500nmとすることが特に好ましい。 From the above examination, it is preferable that the maximum doping density of the high doping layer 5 is 1 × 10 20 to 2 × 10 21 cm −3 . The thickness is preferably 15 nm to 1.5 μm, and particularly preferably 50 nm to 500 nm.

なお、本発明において、「第2導電型高ドーピング層(p++型高ドーピング層)5の厚さ」とは、この第2導電型高ドーピング層(p++型高ドーピング層)5が第2導電型電荷注入層(p+型電荷注入層)4の表面からイオンを打ち込んで形成される場合には、深さ
方向へのドーピング密度分布(多段イオン打ち込み(注入)法の場合には、最大のイオン打ち込みエネルギーにより形成されるドーピング密度分布)において、該表面から最大のドーピング密度を与える位置までの距離(深さ)をいう。
In the present invention, the “thickness of the second conductivity type highly doped layer (p ++ type highly doped layer) 5” means that the second conductivity type highly doped layer (p ++ type highly doped layer) 5 is In the case where ions are implanted from the surface of the second conductivity type charge injection layer (p + type charge injection layer) 4, the doping density distribution in the depth direction (in the case of the multistage ion implantation (implantation) method) , The distance (depth) from the surface to the position giving the maximum doping density in the doping density distribution formed by the maximum ion implantation energy).

<メサ構造>
本発明に係る炭化珪素バイポーラ型半導体装置のメサ構造は、例えば、以下の方法により形成することができる。
<Mesa structure>
The mesa structure of the silicon carbide bipolar semiconductor device according to the present invention can be formed, for example, by the following method.

上記p++型高ドーピング層5の上に例えばCVD法(Chemical Vapour Deposition)により厚さ10μm程度の酸化ケイ素膜を形成する。この酸化ケイ素膜上にフォトリソグラフィー技術によりメサ形状に対応したフォトレジスト膜を形成する。続いてフッ化水素酸により、フォトレジスト膜のない部分すなわち露出した酸化ケイ素膜を除去する。この作業によりp++型高ドーピング層5の表面にはメサ形状に対応した酸化ケイ素膜が形成される。この酸化ケイ素膜をマスクとして、露出しているp++型高ドーピング層5の領域を例えば反応性イオンエッチング(RIE)によりp++型高ドーピング層5から、p+型電荷注入層4、n-型ドリフト層3の一部に至るまで除去し、高さ幅4μmのメサ構造10を形成する。尚、RIE用のマスクは酸化ケイ素膜に限らず、アルミニウムやニッケル等でも良い。 A silicon oxide film having a thickness of about 10 μm is formed on the p ++ type highly doped layer 5 by, for example, a CVD method (Chemical Vapor Deposition). A photoresist film corresponding to the mesa shape is formed on the silicon oxide film by photolithography. Subsequently, the portion without the photoresist film, that is, the exposed silicon oxide film is removed with hydrofluoric acid. By this operation, a silicon oxide film corresponding to the mesa shape is formed on the surface of the p ++ type highly doped layer 5. Using this silicon oxide film as a mask, the exposed region of the p ++ type highly doped layer 5 is, for example, formed by reactive ion etching (RIE) from the p ++ type highly doped layer 5 to the p + type charge injection layer 4, The mesa structure 10 having a height width of 4 μm is formed by removing up to a part of the n -type drift layer 3. The RIE mask is not limited to the silicon oxide film, and may be aluminum, nickel, or the like.

次に、メサ周辺部での電界集中を緩和するために、電界緩和構造6を形成することが望ましい。この電界緩和構造6は、例えば、以下の手順により形成することができる。
++型高ドーピング層5およびp+型電荷注入層4の上に例えばCVD法により厚さ2
μm程度の酸化ケイ素膜を形成する。この酸化ケイ素膜上にフォトリソグラフィー技術により電界緩和構造の形状に対応したフォトレジスト膜を形成する。続いてフッ化水素酸により、フォトレジスト膜のない、すなわち電界緩和構造となる部分の酸化ケイ素膜を除去する。この作業によりp++型高ドーピング層5およびp+型電荷注入層4の表面には電界
緩和構造の形状に対応した酸化ケイ素膜が形成される。この酸化ケイ素膜をマスクとして、硼素やアルミニウムをドーパントとしたイオン打込みにより、電界緩和構造6を形成する。
Next, it is desirable to form the electric field relaxation structure 6 in order to alleviate the electric field concentration around the mesa. The electric field relaxation structure 6 can be formed by the following procedure, for example.
A thickness of 2 is formed on the p ++ type highly doped layer 5 and the p + type charge injection layer 4 by, eg, CVD.
A silicon oxide film of about μm is formed. A photoresist film corresponding to the shape of the electric field relaxation structure is formed on the silicon oxide film by photolithography. Subsequently, the portion of the silicon oxide film that does not have a photoresist film, that is, a portion that has an electric field relaxation structure is removed by hydrofluoric acid. By this operation, a silicon oxide film corresponding to the shape of the electric field relaxation structure is formed on the surfaces of the p ++ type highly doped layer 5 and the p + type charge injection layer 4. Using this silicon oxide film as a mask, the electric field relaxation structure 6 is formed by ion implantation using boron or aluminum as a dopant.

この電界緩和構造6の厚さは、好ましくは10nm〜1μm、さらに好ましくは、100
nm〜1μmである。また、この電界緩和構造6のドーピング密度は、好ましくは、1×1016〜1×1018cm-3である。
The thickness of the electric field relaxation structure 6 is preferably 10 nm to 1 μm, more preferably 100 nm.
nm to 1 μm. The doping density of the electric field relaxation structure 6 is preferably 1 × 10 16 to 1 × 10 18 cm −3 .

イオン打込み後、Ar等の雰囲気中で1600℃〜1800℃の熱処理にて注入イオン
を活性化させることが好ましい。
<電極>
本発明にかかる炭化珪素バイポーラ型半導体装置に用いるアノード電極8およびカソード電極9の形成は、例えば、以下の方法により行うことができる。
After ion implantation, it is preferable to activate the implanted ions by heat treatment at 1600 ° C. to 1800 ° C. in an atmosphere of Ar or the like.
<Electrode>
The anode electrode 8 and the cathode electrode 9 used in the silicon carbide bipolar semiconductor device according to the present invention can be formed, for example, by the following method.

まず、素子表面を保護するための酸化膜を形成する。例えば熱酸化法により厚さ40nm程度の酸化膜を形成する。
続いて、フォトリソグラフィー技術およびフッ酸を使用して不要な酸化ケイ素膜を除去し、SiCを露出させる。次にスパッタリング法等を用いて、カソード電極9にはn+
板2の下面にニッケル(厚さ350nm程度)の金属薄膜を、アノード電極8にはp++型高ドーピング層5の上面にニッケル(厚さ50nm程度)の金属薄膜をそれぞれ形成する。その後、アノード電極8に関してはフォトリソグラフィー技術およびエッチング液を使用して不要なニッケルを除去する。さらにこれらの電極は金属薄膜を形成した後、熱処理を行うことで合金化され、オーミック電極となる。
First, an oxide film for protecting the element surface is formed. For example, an oxide film having a thickness of about 40 nm is formed by a thermal oxidation method.
Subsequently, an unnecessary silicon oxide film is removed by using a photolithography technique and hydrofluoric acid to expose SiC. Next, using a sputtering method or the like, a metal thin film of nickel (about 350 nm thick) is formed on the lower surface of the n + substrate 2 for the cathode electrode 9, and nickel is formed on the upper surface of the p ++ type highly doped layer 5 for the anode electrode 8. Metal thin films having a thickness of about 50 nm are formed. Thereafter, unnecessary nickel is removed from the anode electrode 8 by using a photolithography technique and an etching solution. Furthermore, after forming a metal thin film, these electrodes are alloyed by heat treatment to form ohmic electrodes.

さらに、ボンディングによる機械的応力の緩和や、アノード電極8の広がり抵抗の影響を低減する目的として、スパッタリング法等を用いてアノード電極8の表面にチタニウム(厚さ50nm程度)およびアルミニウム(厚さ1μm程度)の金属薄膜を形成しても良い。   Further, for the purpose of alleviating mechanical stress due to bonding and reducing the influence of spreading resistance of the anode electrode 8, titanium (thickness: about 50 nm) and aluminum (thickness: 1 μm) are formed on the surface of the anode electrode 8 using a sputtering method or the like. A metal thin film may be formed.

また本発明において、SiC単結晶の結晶型、結晶面などは、特に限定されるものではなく、各種のものについて本発明の効果を得ることができる。
以上のとおり、n型が第1導電型でp型が第2導電型である炭化珪素バイポーラ型半導体装置について説明したが、本発明にかかる炭化珪素バイポーラ型半導体装置は、導電型が反対、すなわち、p型が第1導電型でn型が第2導電型である炭化珪素バイポーラ型半導体装置であってもよい。この場合には、本発明にかかる炭化珪素バイポーラ型半導体装置において、p+型基板2、p-型ドリフト層3、n+型電荷注入層4、および、n++型高
ドーピング層5がこの順序にて積層されている。なお、この場合においては、n++型高ドーピング層5の形成の際にn+型電荷注入層4に導入されるイオンは、窒素や燐であり、また、電界緩和構造6の形成のためにp-型ドリフト層3に導入されるイオンについても同様である。
In the present invention, the crystal type and crystal plane of the SiC single crystal are not particularly limited, and the effects of the present invention can be obtained for various types.
As described above, the silicon carbide bipolar semiconductor device in which the n-type is the first conductivity type and the p-type is the second conductivity type has been described. However, the silicon carbide bipolar semiconductor device according to the present invention has the opposite conductivity type, A silicon carbide bipolar semiconductor device in which the p-type is the first conductivity type and the n-type is the second conductivity type may be used. In this case, in the silicon carbide bipolar semiconductor device according to the present invention, the p + type substrate 2, the p type drift layer 3, the n + type charge injection layer 4, and the n ++ type highly doped layer 5 They are stacked in order. In this case, the ions introduced into the n + type charge injection layer 4 when the n ++ type highly doped layer 5 is formed are nitrogen and phosphorus, and the electric field relaxation structure 6 is formed. The same applies to ions introduced into the p -type drift layer 3.

以下、実施例により本発明を説明するが、本発明はこれらの実施例に限定されるものではなく、その要旨を逸脱しない範囲内において各種の変形、変更が可能である。
[実施例]
以下、実施例により本発明を説明するが、本発明はこの実施例に限定されるものではない。
Hereinafter, the present invention will be described by way of examples. However, the present invention is not limited to these examples, and various modifications and changes can be made without departing from the scope of the present invention.
[Example]
EXAMPLES Hereinafter, although an Example demonstrates this invention, this invention is not limited to this Example.

[実施例1]
図1に示すpnダイオードを作製した。
(1)導電層の形成
まず、昇華法(改良レーリー法)より得られたSiCバルク結晶をスライスして得られたn型の4H−SiC単結晶基板であるn+基板2(ドナー密度7×1018cm-3、厚さ
400μm)の上に、エピタキシャル成長法によってn+基板2と同一の結晶型であるn-型のSiC単結晶膜を成長させて、厚さ60μmのn-型ドリフト層3を形成した。本n-型ドリフト層3は窒素をドーパントとして含有しており、n-型ドリフト層3のドナー密
度は1×1014〜6×1014cm-3とした。
[Example 1]
The pn diode shown in FIG. 1 was produced.
(1) Formation of Conductive Layer First, an n + substrate 2 (donor density 7 ×) which is an n-type 4H—SiC single crystal substrate obtained by slicing a SiC bulk crystal obtained by a sublimation method (improved Rayleigh method) 10 18 cm -3, on the thickness of 400 [mu] m), the same crystal form and the n + substrate 2 by an epitaxial growth method by growing a n- type SiC single crystal film, having a thickness of 60 [mu] m n- type drift layer 3 was formed. This n − -type drift layer 3 contains nitrogen as a dopant, and the donor density of the n − -type drift layer 3 is 1 × 10 14 to 6 × 10 14 cm −3 .

続いて、n-型ドリフト層3の上にエピタキシャル成長法によってp+型のSiC単結晶膜を成長させて、厚さ3μmのp+型導電層4を形成した。p+型導電層4はアルミニウム
をドーパントとして含有しており、p+型導電層4のアクセプタ密度は1×1018〜5×
1019cm-3の範囲にあった。
Then, by growing a p + -type SiC single crystal layer by epitaxial growth method on the n- type drift layer 3 was formed p + type conductive layer 4 having a thickness of 3 [mu] m. The p + type conductive layer 4 contains aluminum as a dopant, and the acceptor density of the p + type conductive layer 4 is 1 × 10 18 to 5 ×.
It was in the range of 10 19 cm −3 .

+型導電層4を形成した後、アルミニウムをイオン打込みすることでp++型高ドーピ
ング層5を形成した。イオン打込み条件は、20〜150keVの打込みエネルギーにて、合計ドーズ量が2.3×1016cm-2となるような多段注入とし、深さが250nm、ドーピング密度が1×1021cm-3のボックスプロファイルを形成した。
After the p + type conductive layer 4 was formed, the p ++ type highly doped layer 5 was formed by ion implantation of aluminum. The ion implantation conditions are multistage implantation with a total dose of 2.3 × 10 16 cm −2 at an implantation energy of 20 to 150 keV, a depth of 250 nm, and a doping density of 1 × 10 21 cm −3. A box profile was formed.

(2)メサ構造の形成
前記p++型高ドーピング層5の上にCVD法により厚さ10μm程度の酸化ケイ素膜を形成した。この酸化ケイ素膜上にフォトリソグラフィー技術によりメサ形状に対応したフォトレジスト膜を形成した。続いてフッ化水素酸により、フォトレジスト膜のない部分すなわち露出した酸化ケイ素膜を除去した。この酸化ケイ素膜をマスクとして、露出しているp++型高ドーピング層5の領域を反応性イオンエッチング(RIE)によりp++型高ドーピング層5から、p+型電荷注入層4、およびn-型ドリフト層3の一部に至るまで除去し、高さ幅4μmのメサ構造10を形成した。
(2) Formation of Mesa Structure A silicon oxide film having a thickness of about 10 μm was formed on the p ++ type highly doped layer 5 by the CVD method. A photoresist film corresponding to the mesa shape was formed on the silicon oxide film by photolithography. Subsequently, the portion without the photoresist film, that is, the exposed silicon oxide film was removed with hydrofluoric acid. Using this silicon oxide film as a mask, the exposed region of the p ++ type highly doped layer 5 is subjected to reactive ion etching (RIE) from the p ++ type highly doped layer 5 to the p + type charge injection layer 4, and The mesa structure 10 having a height width of 4 μm was formed by removing a part of the n -type drift layer 3.

(3)電界緩和構造の形成
メサ周辺部での電界集中を緩和するために、pn接合界面からメサコーナー部の外側50μm程度に至る範囲にわたり、n-型導電層3にアルミニウムをドーパントとしてイオン打込みにより電界緩和構造6を形成した。本イオン打込みは、15〜350keVの多段打込みエネルギーにてドーズ量が3.2×1014cm-2となるような条件で実施した。この条件において打込まれたアルミニウムのドーピング密度についての深さ方向のプロファイルは、打込み表面付近から深さ500nmにかけて6×1018cm-3となるようなボックスプロファイルである。イオン打込み後、Ar等の雰囲気中で1600℃〜1800℃の熱処理にて注入イオンを活性化させた。
(3) Formation of electric field relaxation structure In order to alleviate electric field concentration at the mesa peripheral part, ion implantation is performed using aluminum as a dopant in the n − type conductive layer 3 over a range from the pn junction interface to the outside of the mesa corner part of about 50 μm. Thus, the electric field relaxation structure 6 was formed. This ion implantation was performed under the condition that the dose amount was 3.2 × 10 14 cm −2 at a multistage implantation energy of 15 to 350 keV. The profile in the depth direction with respect to the doping density of aluminum implanted under these conditions is a box profile that becomes 6 × 10 18 cm −3 from the vicinity of the implantation surface to a depth of 500 nm. After the ion implantation, the implanted ions were activated by heat treatment at 1600 ° C. to 1800 ° C. in an atmosphere such as Ar.

次に、素子表面を保護するため、p++型高ドーピング層5の存在する側の素子表面全体に厚さ約40nmの酸化膜7を形成した。
続いて前述同様、フォトリソグラフィー技術およびフッ酸を使用して不要な酸化ケイ素膜を除去し、p++型高ドーピング層5の表面を露出させた。次にスパッタリング法等を用いて、n+基板2の下面にカソード電極9としてニッケル(厚さ350nm)の金属薄膜
を、p++型高ドーピング層5の上面にアノード電極8としてニッケル(厚さ50nm)の金属薄膜をそれぞれ形成した。アノード電極8についてはフォトリソグラフィー技術およびエッチング溶液を使用して不要なニッケルを除去した。さらにこれらの電極は金属薄膜を形成した後、熱処理を行うことで合金化し、オーミック電極とした。
Next, in order to protect the element surface, an oxide film 7 having a thickness of about 40 nm was formed on the entire element surface on the side where the p ++ type highly doped layer 5 exists.
Subsequently, as described above, an unnecessary silicon oxide film was removed by using a photolithography technique and hydrofluoric acid to expose the surface of the p ++ type highly doped layer 5. Next, using a sputtering method or the like, a metal thin film of nickel (thickness 350 nm) is formed as the cathode electrode 9 on the lower surface of the n + substrate 2, and nickel (thickness) is formed as the anode electrode 8 on the upper surface of the p ++ type highly doped layer 5. 50 nm) metal thin films were respectively formed. For the anode electrode 8, unnecessary nickel was removed by using a photolithography technique and an etching solution. Furthermore, after forming a metal thin film, these electrodes were alloyed by heat treatment to form ohmic electrodes.

さらにアノード電極8の表面にチタニウム(厚さ50nm)およびアルミニウム(厚さ1μm)の金属薄膜をこの順番で積層した。
(4)得られたpnダイオードの通電試験
得られたpnダイオードに対して、以下の通電試験を行った。高融点半田を用いてpnダイオードのカソード電極を銅板上に貼り付け、超音波ボンディング装置を用いてアノード電極にアルミニウムワイヤをボンディングした。銅板とアルミニウムワイヤに電流源を接続し、順方向に100A/cm2の直流電流を通電劣化させた後、このpnダイオード
のエレクトロルミネッセンス像(EL像)を取得し、これら通電劣化とEL像の取得とを繰り返すことで、積層欠陥24の動きや形状の経時変化を観察し、積層欠陥24の起点となる欠陥核23の個数を評価した。評価結果を図3に示す。
Further, a metal thin film of titanium (thickness 50 nm) and aluminum (thickness 1 μm) was laminated on the surface of the anode electrode 8 in this order.
(4) Energization test of the obtained pn diode The following energization test was performed on the obtained pn diode. A cathode electrode of a pn diode was pasted on a copper plate using a high melting point solder, and an aluminum wire was bonded to the anode electrode using an ultrasonic bonding apparatus. After connecting a current source to the copper plate and the aluminum wire and deteriorating the direct current of 100 A / cm 2 in the forward direction, an electroluminescence image (EL image) of this pn diode was obtained. By repeating the acquisition, the movement and shape change of the stacking fault 24 was observed, and the number of defect nuclei 23 serving as the starting point of the stacking fault 24 was evaluated. The evaluation results are shown in FIG.

[比較例1]
++型高ドーピング層5を形成するためのイオン打込み工程を行わず、これ以外の工程
は実施例と同様のプロセスを適用して、比較用のpnダイオードを作製した。
[Comparative Example 1]
The ion implantation process for forming the p ++ type highly doped layer 5 was not performed, and a process similar to the example was applied to the other processes, and a comparative pn diode was manufactured.

その後、実施例1と同様の通電試験をこの比較用のpnダイオードに対して行い、図3に示す評価結果を得た。
図3に示すように、p++型高ドーピング層5を導入しないpnダイオード(比較例1)では、p+型電荷注入層4の表層近傍に認められた欠陥核23の個数が1個以下の素子が
57%(13個/23個)であったのに対し、p++型高ドーピング層5を導入したpnダイオード(実施例1)では前記欠陥核の個数が1個以下の素子が90%(18個/20個)であった。以上のように、p++型高ドーピング層5を導入することで、p+型電荷注入層4の表層近傍の欠陥核23を起点とした積層欠陥の拡大を抑制可能であることが確認できた。
Thereafter, the same energization test as in Example 1 was performed on the comparative pn diode, and the evaluation results shown in FIG. 3 were obtained.
As shown in FIG. 3, in the pn diode (Comparative Example 1) in which the p ++ type highly doped layer 5 is not introduced, the number of defect nuclei 23 found near the surface layer of the p + type charge injection layer 4 is 1 or less. The number of the defect nuclei in the pn diode (Example 1) in which the p ++ type highly doped layer 5 was introduced was 1% or less, compared with 57% (13/23). It was 90% (18/20). As described above, it can be confirmed that the introduction of the p ++ type highly doped layer 5 can suppress the expansion of stacking faults starting from the defect nucleus 23 in the vicinity of the surface layer of the p + type charge injection layer 4. It was.

なお、Joseph.J.SUMAKERISらは、p+型電荷注入層とn-型ドリフト層の間に、ドーピング密度が1×1017〜1×1019cm-3、厚さが約1.5μmのp+
型バッファ層を設け、n-ドリフト層から拡散してきた電子を正孔と再結合させるための
発明を行っている(上記特許文献1)。一方、本発明は、p+型電荷注入層の表層にp++
型高ドーピング層を設けることにより、少数キャリアである電子を再結合させ、かつp++型高ドーピング層のドーピング密度を1×1020〜2×1021cm-3と高くすることにより、p++型高ドーピング層の厚さを1.5μm以下に薄くすることができ、さらにこのp++型高ドーピング層を用いてオーミックコンタクトを形成することにより、低抵抗のアノード電極を得ることが期待できる。また、上記特許文献1では、表層付近を起点とした積層欠陥の抑制効果を定量的に評価していない。このような点において、本発明はJoseph.J.SUMAKERISらのものと明らかに違う。
In addition, Joseph. J. et al. SUMAKERIS et al, between p + -type charge injection layer and the n- type drift layer, a doping density of 1 × 10 17 ~1 × 10 19 cm -3, a thickness of about 1.5 [mu] m p +
A type buffer layer is provided, and an invention for recombining electrons diffused from the n drift layer with holes is performed (Patent Document 1). On the other hand, in the present invention, p ++ is formed on the surface layer of the p + type charge injection layer.
By providing the type highly doped layer, the electrons which are minority carriers are recombined, and by increasing the doping density of the p ++ type highly doped layer to 1 × 10 20 to 2 × 10 21 cm −3 , p The thickness of the ++ type highly doped layer can be reduced to 1.5 μm or less, and an ohmic contact can be formed using the p ++ type highly doped layer to obtain a low resistance anode electrode. I can expect. Moreover, in the said patent document 1, the suppression effect of the stacking fault from the surface layer vicinity is not evaluated quantitatively. In this respect, the present invention relates to Joseph. J. et al. It is clearly different from those of SUMAKERIS and others.

本実施例ではpnダイオードを例として説明したが、これ以外の炭化珪素バイポーラ型半導体装置、例えばサイリスタ、ゲートターンオフサイリスタ(GTO)、絶縁ゲートバイポーラトランジスタ(IGBT)、バイポーラ接合トランジスタ(BJT)などにも本発明を適用できる。   In the present embodiment, a pn diode has been described as an example, but other silicon carbide bipolar semiconductor devices such as a thyristor, a gate turn-off thyristor (GTO), an insulated gate bipolar transistor (IGBT), a bipolar junction transistor (BJT), etc. The present invention can be applied.

本発明の炭化珪素バイポーラ型半導体装置の一態様における模式断面図である。It is a schematic cross section in one mode of a silicon carbide bipolar semiconductor device of the present invention. 本発明の炭化珪素バイポーラ型半導体装置の作用を説明するための図である。It is a figure for demonstrating the effect | action of the silicon carbide bipolar semiconductor device of this invention. 実施例および比較例で作成されたpnダイオードの評価結果を示す図である。It is a figure which shows the evaluation result of the pn diode produced by the Example and the comparative example. メサ構造を形成した従来のpnダイオードの断面図である。It is sectional drawing of the conventional pn diode which formed the mesa structure. 従来のpnダイオードにおける積層欠陥の生成機構を説明する図である。It is a figure explaining the production | generation mechanism of the stacking fault in the conventional pn diode.

符号の説明Explanation of symbols

1: pnダイオード
2: n+基板
3: n-型ドリフト層
4: p+型電荷注入層
5: p++型高ドーピング層
6: 電界緩和構造
7: 酸化膜
8: アノード電極
9: カソード電極
10: メサ構造
11: pn接合界面
21: 電子
22: 正孔
23: 欠陥核
24: 積層欠陥
1: pn diode 2: n + substrate 3: n type drift layer 4: p + type charge injection layer 5: p ++ type highly doped layer 6: electric field relaxation structure 7: oxide film 8: anode electrode 9: cathode electrode 10: mesa structure 11: pn junction interface 21: electron 22: hole 23: defect nucleus 24: stacking fault

Claims (3)

第1導電型炭化珪素単結晶基板、エピタキシャル成長法により形成される第1導電型炭化珪素ドリフト層、エピタキシャル成長法により形成される第2導電型炭化珪素電荷注入層、および該炭化珪素電荷注入層よりもドーピング密度が高い第2導電型の高ドーピング層が、この順序にて積層してなり、
前記炭化珪素ドリフト層から前記高ドーピング層側の素子表面に至るメサ構造を有し、
前記高ドーピング層の厚さが15nm〜1.5μmであり、かつ、前記高ドーピング層における最大ドーピング密度が1×1020cm-3〜2×1021cm-3であることを特徴とする炭化珪素バイポーラ型半導体装置。
Than the first conductivity type silicon carbide single crystal substrate, the first conductivity type silicon carbide drift layer formed by the epitaxial growth method, the second conductivity type silicon carbide charge injection layer formed by the epitaxial growth method, and the silicon carbide charge injection layer A highly doped layer of the second conductivity type having a high doping density is laminated in this order,
Having a mesa structure from the silicon carbide drift layer to the element surface on the highly doped layer side;
Carbonization characterized in that the thickness of the highly doped layer is 15 nm to 1.5 μm and the maximum doping density in the highly doped layer is 1 × 10 20 cm −3 to 2 × 10 21 cm −3. Silicon bipolar semiconductor device.
前記高ドーピング層がイオン打ち込みにより形成されていることを特徴とする請求項1に記載の炭化珪素バイポーラ型半導体装置。   2. The silicon carbide bipolar semiconductor device according to claim 1, wherein the highly doped layer is formed by ion implantation. 前記高ドーピング層がアルミニウム、窒素または燐をイオン打ち込みすることにより形成されていることを特徴とする請求項1または2に記載の炭化珪素バイポーラ型半導体装置。   The silicon carbide bipolar semiconductor device according to claim 1, wherein the highly doped layer is formed by ion implantation of aluminum, nitrogen, or phosphorus.
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011101021A (en) * 2009-11-09 2011-05-19 Abb Technology Ag Fast recovery diode
DE112016004981T5 (en) 2015-10-30 2018-07-19 Mitsubishi Electric Corporation SILICON CARBIDE SEMICONDUCTOR DEVICE
US10453924B2 (en) 2016-07-29 2019-10-22 Fuji Electric Co., Ltd. Silicon carbide semiconductor substrate, method of manufacturing silicon carbide semiconductor substrate, semiconductor device and method of manufacturing semiconductor device
JP2020155660A (en) * 2019-03-22 2020-09-24 富士電機株式会社 Semiconductor device and method of inspecting semiconductor device
JP2021073737A (en) * 2021-02-10 2021-05-13 株式会社日立製作所 Semiconductor device and power converter

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002261295A (en) * 2001-03-05 2002-09-13 Shikusuon:Kk Schottky, p-n junction diode, and pin junction diode and their manufacturing method
JP2006295061A (en) * 2005-04-14 2006-10-26 Kansai Electric Power Co Inc:The Bipolar semiconductor device, method for recovering forward voltage thereof, and method for reducing stacking fault

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002261295A (en) * 2001-03-05 2002-09-13 Shikusuon:Kk Schottky, p-n junction diode, and pin junction diode and their manufacturing method
JP2006295061A (en) * 2005-04-14 2006-10-26 Kansai Electric Power Co Inc:The Bipolar semiconductor device, method for recovering forward voltage thereof, and method for reducing stacking fault

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011101021A (en) * 2009-11-09 2011-05-19 Abb Technology Ag Fast recovery diode
DE112016004981T5 (en) 2015-10-30 2018-07-19 Mitsubishi Electric Corporation SILICON CARBIDE SEMICONDUCTOR DEVICE
US10134920B2 (en) 2015-10-30 2018-11-20 Mitsubishi Electric Corporation Silicon carbide semiconductor device
US10453924B2 (en) 2016-07-29 2019-10-22 Fuji Electric Co., Ltd. Silicon carbide semiconductor substrate, method of manufacturing silicon carbide semiconductor substrate, semiconductor device and method of manufacturing semiconductor device
JP2020155660A (en) * 2019-03-22 2020-09-24 富士電機株式会社 Semiconductor device and method of inspecting semiconductor device
JP7334435B2 (en) 2019-03-22 2023-08-29 富士電機株式会社 Semiconductor device and semiconductor device inspection method
JP2021073737A (en) * 2021-02-10 2021-05-13 株式会社日立製作所 Semiconductor device and power converter
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