JP6557925B2 - Semiconductor element - Google Patents

Description

  The present invention relates to a power semiconductor element, and more particularly to a high-performance semiconductor element having bipolar characteristics and reverse conduction characteristics.

At present, Si-MOSFETs and Si-BJTs (bipolar transistors) made of silicon (Si) are mainly used as power semiconductor elements for power converters, and Si-IGBTs for medium to high power applications. Si-GTO (gate turn-off thyristor) is used. In recent years, wide-gap semiconductor materials having a wider band gap than Si, such as silicon carbide (SiC) and gallium nitride (GaN), have attracted attention as semiconductor materials suitable for high voltage and low loss applications. Has been. For example, SiC has an excellent characteristic that the dielectric breakdown electric field strength is about 10 times higher than that of Si. As a result, when the structure is almost the same, in principle, about 10 times that of Si-MOSFET. It is expected that a SiC-MOSFET having a high breakdown voltage or an ultra-low loss of about 1/1000 can be realized. As a result, in medium power and high power applications, SiC-MOSFETs, SiC-BJTs, SiC-JFETs (junction FETs) are used instead of Si-IGBTs, and there is a trend to achieve significant power savings. Furthermore, ultra-high withstand voltage and large current SiC-IGBT and SiC-GTO are also being studied from the viewpoint of achieving significant power saving in ultra-high power applications for the power business.

In general, MOSFETs, BJTs, and JFETs can flow forward current from around zero volts when forward voltage is applied, but thyristors such as GTO and IGBTs have built-in voltages (about 0 for Si and collector and anode voltages). Since forward current cannot flow unless the voltage is about 2.7 V or more for .7V and SiC, MOSFETs have significantly lower on-loss and faster switching speed in the low-voltage region near the built-in voltage. Therefore, the total loss is small. However, since the on-resistance in the linear region is almost constant, if a large current is passed during overload operation of the power converter, the on-voltage increases, the heat generation increases significantly, and the element is damaged. There is.
On the other hand, when the IGBT or thyristor exceeds the built-in voltage, the on-resistance is drastically reduced due to the conductivity modulation effect. Therefore, when the forward voltage is 3 to 5 V or more, the loss is significantly smaller than that of the MOSFET or the like. Accordingly, the loss can be reduced even when an equivalent large current is passed during the overload operation of the power conversion device, so that the overload capability can be increased. However, since the switching speed is slower than that of a MOSFET or the like, the disadvantage that the switching loss is large is unavoidable. Therefore, there is a disadvantage that the total loss is large at a low on-voltage, for example, below 5V.

In order to improve these device characteristics, in recent years, improvement studies using semiconductor devices having bipolar characteristics and so-called reverse conduction characteristics that do not have a blocking ability against reverse voltage have been promoted. Hereinafter, these semiconductor elements are collectively referred to as bipolar reverse conducting semiconductor elements. As an example of studying improvement of a bipolar reverse conducting semiconductor element, there is an improvement example in which, for example, a Si-IGBT having a bipolar characteristic is made into a reverse conducting element structure, the turn-off speed is shortened, the switching loss is reduced, and the total loss is reduced. As typical examples, there are development examples of the Si reverse conducting IGBT of Conventional Example 1 shown in FIG. 8 and Conventional Example 2 shown in FIG. 9, which are disclosed in Non-Patent Documents 1 and 2, respectively. Similar attempts have been made in the GTO, and various reverse conducting GTOs have been developed.

In the short-circuit collector Si-IGBT of the conventional example 1, the n ⁻ drift layer is short-circuited to the collector electrode by the n ⁺ short circuit provided in the p collector layer, and the carrier in the n ⁻ drift layer is connected to the n ⁺ short circuit at the time of turn-off. Therefore, the turn-off time is shortened and the loss is reduced.
The Si reverse conducting IGBT of Conventional Example 2 is composed of a reverse conducting Si-IGBT region and a pilot IGBT region. In the Si reverse conducting IGBT region, the n drift layer is short-circuited to the collector electrode by the n ⁺ short-circuit portion provided in the p collector layer as in the conventional example 1, and the carriers in the n drift layer at the time of turn-off are the n ⁺ short-circuit portion. By eliminating this, the turn-off time is shortened and loss is reduced. However, a conventional reverse conducting IGBT has a snapback phenomenon in which a negative resistance appears when it is turned on. This causes a disturbance in circuit operation to which this element is applied, possibly leading to damage or destruction of the element or circuit. was there. In Conventional Example 2, a pilot IGBT region is provided, and the width of this collector is made larger than the width of the collector of the reverse conducting IGBT region, so that the pilot IGBT region is turned on prior to the reverse conducting IGBT region, and the snapback phenomenon is caused. Suppressed.

Each of these disclosed IGBTs is named with a unique name, but any of them is an element that does not have a blocking capability against a reverse voltage because the n drift layer is short-circuited to the collector electrode by the n ⁺ short-circuit portion. In the following, both are simply referred to as reverse conducting IGBTs.

Hajime AKIYAMA, 5 others, Ict of Shorted Collector on Characters of IGBTS of The 2nd International Symposium on Power Semiconductor Devices & ICs), April 1990, p. 131-136 Liutauras Strasta, 2 others, A Comparison of Charge Dynamics in the Leverth Conducting RCIGBT and Bimode Insulated Gate Transistor (BIG) Insulated Gate Transistor BiGT), Proceedings of the Twenty Second International Symposium on Power Semiconductor Devices and ICs (Proceedings of The 22nd International Symposium) ium on Power Semiconductor Devices & ICs), 6 May 2010, p. 391-394

  Typical examples of the bipolar reverse conducting semiconductor element include a reverse conducting IGBT, a reverse conducting GTO, a reverse conducting electrostatic induction thyristor, a reverse conducting MCT (MOS control thyristor), a reverse conducting EST (emitter switch thyristor), and the like. These bipolar reverse conducting semiconductor elements are composed of a first functional element unit that performs a bipolar operation in a saturation region and a second functional element unit that performs a unipolar operation in a linear region, such as a reverse conducting IGBT, and a reverse conducting GTO. As described above, the first functional element unit that performs a bipolar switching operation and the second functional element unit that performs a bipolar operation in a saturation region are roughly divided into elements that are merged. Here, the fusion means that both functional element portions share a plurality of semiconductor layers, semiconductor regions, electrodes, and the like constituting the element.

By the way, it is difficult for these conventional bipolar reverse conducting semiconductor elements to achieve both low on-resistance and high mechanical strength. A bipolar reverse conducting semiconductor element is generally formed by connecting both a collector region (or an anode region) and a short-circuit region to a collector electrode (or an anode electrode) on one main surface of the element, and also on the other main surface of the element. Since the emitter region (or cathode region) is formed in contact with the emitter electrode (or cathode electrode), it is necessary to reduce the thickness of the device manufacturing wafer and the device itself in order to reduce the on-resistance. As a result, the mechanical strength is lowered, and it is damaged by various stresses during manufacture and mounting.
On the other hand, in order to increase the mechanical strength of the wafer and the element itself so as to withstand various stresses during manufacture, it is necessary to increase the thickness of the wafer for manufacturing the element and the thickness of the element itself. Of course, this thickness varies depending on the manufacturing and mounting processes, but is usually about 300 μm or more unless special measures are taken with an increase in cost. In the case of a bipolar reverse conducting semiconductor device, an emitter is formed on the front surface and a collector and a short-circuit region are formed on the back surface as in the conventional reverse conducting IGBT device described above. When the thickness of the wafer and the device is increased, the drift layer becomes thicker. Since the thickness of the emitter and the collector is usually 10 μm or less, for example, the remaining approximately 280 μm or more becomes the drift layer. In a high breakdown voltage element of about 3 kV or more, the thickness of the drift layer needs to be increased to about 280 μm or more in order to relax the electric field. Therefore, in the case of the drift thickness of 280 μm or more, it is possible to obtain an appropriate on-resistance corresponding to the withstand voltage while ensuring high mechanical strength. However, in the semiconductor market with the most demand such as automobiles and home appliances, the element withstand voltage is medium to small withstand voltage, for example, about 1.7 kV or less, and a reasonable drift thickness is about 170 μm or less in terms of withstand voltage. . If the thickness is necessary from the viewpoint of mechanical strength, that is, a thickness of about 300 μm, the drift thickness of 120 μm as a difference unnecessarily increases the on-resistance.

In the case of SiC-IGBT, the dielectric breakdown electric field strength is about 10 times higher than that of Si. Therefore, the drain thickness corresponding to the withstand voltage is about 1/10 that of Si. On the other hand, from the viewpoint of mechanical strength, the thickness of the wafer at the time of manufacture and the thickness of the element itself are required to be approximately 300 μm or more. Since the thickness of the emitter region and the collector region is usually several μm or less, the remaining about 170 μm excluding these will unnecessarily increase the on-resistance. In the case of an SiC element having a low withstand voltage of, for example, 3 kV or less, the appropriate drift thickness is about 30 μm or less, and the semiconductor portion that increases the on-resistance unnecessarily becomes thick at about 260 μm or more.
As described above, the prior art has a first problem that it is difficult to achieve both the low on-resistance of the large and small withstand voltage bipolar reverse conducting semiconductor element and the high mechanical strength of the element itself or the element manufacturing wafer.

By the way, in a power semiconductor element suitable for a power converter, in the following, the current required for steady operation of the power converter is defined as steady operating current, the maximum steady operating current is defined as rated output current, and overload operation is performed. The required current is defined as overload current. Since the overload current needs to be equal to or lower than the absolute maximum rated current of the element in order to avoid thermal destruction of the element, the maximum overload current can be regarded as synonymous with the absolute maximum rated current of the power semiconductor element, and has the same current value. When the magnification of the absolute maximum rated current with respect to the rated output current is defined as an overload factor and expressed as N, the rated output current is (absolute maximum rated current / N).
In general, power converters such as inverters are required to have an overload capability capable of withstanding an overload current of 125% (1.25 times) or 150% (1.5 times) of the rated output current for 60 seconds. For this reason, the power semiconductor element is required to have an absolute maximum rated current that is 1.25 to 1.5 times the rated output current, that is, N is 1 to 1.5. At present, in order to cope with an N overload of 1.25 to 1.5, it is not easy with a single element, and many devices and modules are often connected in parallel to increase the size and weight of the apparatus.
However, there are many strict various needs for power semiconductor devices in view of the current society and the future. For example, an electric vehicle or the like may be several tens of A or less during normal constant speed operation, but a remarkably large output is required when overcoming an obstacle or during a dash. Similarly, a wind power generation facility requires a significantly larger output during work than when moving in a strong wind or a gust of wind compared to the normal time, and a self-propelled large robot for work in the future compared to when moving. Furthermore, a large / medium capacity uninterruptible power supply requires a much larger output for a short period of time compared to the normal operation, and for a few minutes until the system switching at the substation is completed in the event of a power failure. These are required to be installed in a space as small as possible and to be lightweight. Therefore, in order to cover the above conventional needs, N is required to be about 1 to 4, and preferably about 1.5 to 4 for power semiconductor elements that should meet these needs. It is essential that the module has a small number of elements. At maximum overload with most heat generation, that is, when the absolute maximum rated current is applied, considering the restrictions and limitations of cooling capacity, N is 1 to 1 with a relatively low on-voltage of several volts or less to avoid thermal destruction. It is necessary to have a low loss of about 1 / 2.7 compared with the current device corresponding to 1.5, and therefore, the low loss of 1 / 1.5 or less, which is lower than the current level during steady operation, is about 1/4 at maximum. It is necessary to have a very low loss.

However, although it is surmised that the bipolar reverse conducting semiconductor elements listed above have the potential to meet the above needs, they have not been realized. In other words, the conventional bipolar reverse conducting semiconductor element can be expected to have a remarkably low resistance due to the conductivity modulation effect above the built-in voltage, but both the normal operation and the overload operation are performed in the bipolar operation function unit, and the element is short-circuited. The region was for quickly discharging the remaining electrons in the drift from the device so as not to urge the injection of holes from the p collector region indefinitely. For this reason, the width of the short-circuit region is small and the resistance is not low, and a current having a steady operation current level that is less than the built-in voltage cannot flow. As described above, the conventional bipolar reverse conducting semiconductor element is suitable for overload operation, but is extremely unsuitable as an element to be operated at a constant current level with a low loss at a built-in voltage or less, which is not suitable. This is the second problem to be solved.

  Further, the conventional bipolar reverse conducting semiconductor element has a snapback phenomenon in the output characteristics, and a negative resistance is generated when it is turned on. This is a phenomenon caused by the fact that the voltage between the main electrodes of the second functional element portion immediately before turning on the first functional element portion is higher than the voltage between the main electrodes immediately after turning on the first functional element portion. Hereinafter, the voltage between the main electrodes immediately before turning on is referred to as a snapback voltage and is described as Vsb. Further, the current between the main electrodes at Vsb is called a snapback current and is described as Isb. By the way, these bipolar reverse conducting semiconductor elements have a short time from immediately before turning on to immediately after turning on, that is, turn-on time (more precisely, turn-on rise time). Therefore, if there is a snapback phenomenon, a sudden voltage change ( (Hereinafter referred to as dVsb / dt) and a steep current change (hereinafter referred to as dIsb / dt) occur. As a result, steep jump currents (C · dVsb / dt) are generated by various capacitors including parasitic capacitors existing in the circuit, and steep jump voltages (L · dIsb / dt) are generated by various reactors including parasitic reactors. Due to this, a large transient phenomenon is induced. For this reason, there is a problem in that a circuit using this bipolar reverse conducting semiconductor element is greatly disturbed to cause a malfunction, and in some cases, the element or circuit is damaged or destroyed.

In the conventional example 2, in order to suppress this, a pilot IGBT region having no snapback phenomenon is provided in the element to suppress the snapback phenomenon. Hereinafter, this is referred to as a pilot IGBT effect. However, in order to sufficiently suppress the snapback phenomenon, the area of the pilot IGBT region must be increased, so that the area of the pilot IGBT region in the IGBT chip area is considerably increased. For example, in the case of Conventional Example 2, when read from the data of the above literature, Vsb in the snapback phenomenon that occurs when the p collector width of the 3.3 kV Si reverse conducting IGBT cell is 180 μm is 21 V, and dVsb / dt is 280 V. / Μs is calculated, which causes a large disturbance and malfunction in the applied circuit. On the other hand, by providing a pilot IGBT and increasing its p collector width to about 720 μm or more, which is about four times or more, Vsb can be reduced to 0.7 V or less of the built-in voltage, thereby preventing the occurrence of the snapback phenomenon. However, although the snapback phenomenon can be largely suppressed, the area occupied by the pilot IGBT is increased and the area of the reverse conducting IGBT region is reduced, so that the function of the original reverse conducting IGBT that eliminates the remaining carriers at turn-off is considerably impaired. End up. In the case of the above-described conventional example 2, this is the third problem to be solved for an important bipolar reverse conducting semiconductor element in the present situation where the chip size of the element is normally set to a small area of about 15 mm × 15 mm or less from the viewpoint of economy such as yield. It is a problem.

An object of the present invention is to solve the above-mentioned problems of the prior art and to provide a bipolar reverse conducting semiconductor element that can achieve both low on-resistance and high mechanical strength. Also, a bipolar reverse conducting semiconductor that can flow a large overload current up to the absolute maximum rated current with low loss during overload operation, and can flow a steady operation current with extremely low loss within the range below the built-in voltage during steady operation. An object is to provide an element. It is another object of the present invention to provide a bipolar reverse conducting semiconductor element that can suppress the snapback phenomenon with a small area.

In the following, for easy understanding, in describing the features of the means, what each semiconductor layer or semiconductor region is functionally equivalent to will be described in parentheses.
In order to solve the above problems and achieve the object of the present invention, a semiconductor device according to the present invention includes:
In a bipolar reverse conducting semiconductor element having a first functional element portion (IGBT) that performs a bipolar operation and a second functional element portion (MOSFET) that performs a unipolar operation in a linear region or a bipolar operation in a saturation region, When the voltage is less than the built-in voltage of the operation function element (IGBT), the second function element (MOSFET) of the reverse conducting semiconductor element outputs the rated output current necessary for steady operation of the power converter, and exceeds the built-in voltage. Then, a 1st functional element part (IGBT) outputs the overload current required for the overload operation | movement of the said power converter device, It is characterized by the above-mentioned.
In the semiconductor element according to the present invention, in the above-described invention, when the bipolar reverse conducting semiconductor device sets the overload factor N as the ratio of the maximum overload current, that is, the absolute maximum rated current, to the rated output current, It is a value of ˜4.

The semiconductor element according to the present invention is
The first conductivity type first semiconductor layer (drain layer) and the first conductivity type first semiconductor layer (drain) A second semiconductor layer of the second conductivity type (p buried collector layer) provided on the front surface of the second layer and a plurality of layers penetrating the second semiconductor layer of the second conductivity type (p buried collector layer). The second conductivity type second semiconductor region (second short-circuit region), the second conductivity type second semiconductor layer (p buried collector layer), and the first conductivity type second semiconductor region (second semiconductor region). 2 short circuit region) is provided with a first conductive type third semiconductor layer (n buffer layer) on the front surface of the first conductive type third semiconductor layer (n buffer layer). Provides a second semiconductor layer (drift layer) of the first conductivity type,
A part of the second conductive type second semiconductor layer (p buried collector layer) has a first conductive type second semiconductor layer (drift layer) and the first conductive type second semiconductor layer on the front surface. A third semiconductor region (p trench collector) of the second conductivity type penetrating through the three semiconductor layers (n buffer layer) and a fourth semiconductor region of the first conductivity type (n trench buffer region) of the first conductivity type The fourth semiconductor region (n trench buffer region) is in contact with the first conductivity type second semiconductor layer (n drift layer) and the second conductivity type third semiconductor region (p trench collector), respectively. Provided,
Further, a plurality of second conductive type first semiconductor regions (p body regions) are selectively provided on the front surface of the first conductive type second semiconductor layer (drift layer), and the second conductive type second semiconductor layer (drift layer) is selectively provided. A first conductivity type third semiconductor region (emitter region) is selectively provided on the front surface of each of the conductivity type first semiconductor regions (p body regions),
  Each first conductivity type third semiconductor region (emitter region) and each first conductivity type second semiconductor layer (drift layer) of each second conductivity type first semiconductor region (p body region). A control electrode is provided on the surface of the portion sandwiched between the two via an insulating film,
    Further, a third main electrode (emitter electrode) is provided in contact with each of the second conductivity type first semiconductor region (p body region) and the first conductivity type third semiconductor region (emitter layer). ,
A second main electrode (collector electrode) is provided in contact with the back surface of the first conductivity type first semiconductor layer (drain layer), and is formed on the surface of the second conductivity type third semiconductor region (p trench collector). A bipolar reverse conducting semiconductor element provided with a first main electrode in contact therewith, wherein the second main electrode (collector electrode) and the first main electrode are electrically connected;
  Each semiconductor layer and each semiconductor region are formed of a wide gap semiconductor.

The semiconductor element according to the present invention is the above-described invention,
The first conductive type first semiconductor layer (drain layer), the second conductive type second semiconductor layer (p buried collector layer), and the second conductive type second semiconductor layer (p buried collector layer). ) A number of the first-conductivity-type second semiconductor regions (second short-circuit regions),
A plurality of first conductivity type first semiconductor regions penetrating the second conductivity type first semiconductor layer (p buried collector conductive layer) and the second conductivity type first semiconductor layer (p buried collector conductive layer). (First short-circuit region)
The second conductivity type first semiconductor layer (p buried collector conductive layer) is the second conductivity type second semiconductor layer (p buried collector layer) and the first conductivity type first semiconductor region ( The first short-circuit region has substantially the same planar shape as the first conductivity type second semiconductor region (second short-circuit region) and is provided so as to face and face each other.

The semiconductor element according to the present invention is the above-described invention,
A second conductive type third semiconductor region in which the first conductive electrode of the first functional element unit is left directly or left after all or part of the second conductive type third semiconductor region (p trench collector) is deleted. The second conductive type second semiconductor layer (buried collector layer) or the second conductive type first semiconductor layer (p buried collector conductive layer) via the (p trench collector) It is provided in electrical contact.

The semiconductor element according to the present invention is the above-described invention,
A first conductivity type first semiconductor layer (drain layer) and a second conductivity type second semiconductor layer (p-buried) provided on the front surfaces of the first conductivity type first semiconductor layer (drain layer) And a plurality of first conductivity type second semiconductor regions (second short circuit regions) penetrating the second conductivity type second semiconductor layer (p buried collector layer), and further comprising the second conductivity type. The first conductive type third semiconductor layer (n buffer) is formed on the front surfaces of the second semiconductor layer (p buried collector layer) of the type and the second semiconductor region (second short circuit region) of the first conductive type. A first conductive type second semiconductor layer (drift layer) on the front surface of the first conductive type third semiconductor layer (n buffer layer),
A part of the second conductive type second semiconductor layer (p buried collector layer) has a first conductive type second semiconductor layer (drift layer) and the first conductive type second semiconductor layer on the front surface. A third semiconductor region (p trench collector) of the second conductivity type penetrating through the three semiconductor layers (n buffer layer) and a fourth semiconductor region of the first conductivity type (n trench buffer region) of the first conductivity type The fourth semiconductor region (n trench buffer region) is in contact with the first conductivity type second semiconductor layer (n drift layer) and the second conductivity type third semiconductor region (p trench collector), respectively. Provided,
In addition, a plurality of second conductivity type first semiconductor regions (p body regions) and a plurality of trench gates are alternately selected on the front surface of the first conductivity type second semiconductor layer (drift layer). The first conductive type third semiconductor region (emitter region) is in contact with the trench gate at the front surface of each of the second conductive type first semiconductor regions (p body regions). Are provided selectively.
The trench gate has an insulating film extending on a side surface of the trench and a control electrode in contact with the insulating film, and the first conductive type third semiconductor region (emitter region) and the first conductive type second semiconductor. Of the first semiconductor region (p body region) of the second conductivity type sandwiched between layers (drift layer) The control electrode is provided on the end face through the insulating film,
    Furthermore, a third main electrode (emitter electrode) is provided in contact with the second conductive type first semiconductor region (p body region) and the first conductive type third semiconductor region (emitter layer),
A second main electrode (collector electrode) is provided in contact with the back surface of the first conductivity type first semiconductor layer (drain layer), and the second conductivity type third semiconductor region (p trench collector) A bipolar reverse conducting semiconductor element in which a first main electrode is provided in contact with the first surface, and the second main electrode (collector electrode) and the first main electrode are electrically connected;
  Each semiconductor layer and each semiconductor region are formed of a wide gap semiconductor.

The semiconductor element according to the present invention is the above-described invention,
The bipolar reverse conducting semiconductor element is a reverse conducting GTO,
The upper portion of the cell is a second conductive type first semiconductor region (p base region) provided on the front surface of the first conductive type second semiconductor layer (n drift layer) and the respective front surfaces thereof. A plurality of first conductivity type third semiconductor regions (n emitter regions) selectively provided on the surface,
The third main electrode (emitter electrode) is provided in contact with the third semiconductor region (emitter region) of the first conductivity type,
The control electrode is provided in contact with the first semiconductor region (p base region) of the second conductivity type.

The semiconductor element according to the present invention is the above-described invention,
The first conductivity type first semiconductor layer (drain layer) is made of Si semiconductor,
A first conductivity type second semiconductor layer (drift layer), a second conductivity type second semiconductor layer (p buried collector layer), a first conductivity type second semiconductor region (second short-circuit region), a second conductivity type The type third semiconductor region (p-trench collector) is formed of a 3C-SiC semiconductor.

The semiconductor element according to the present invention is the above-described invention,
A bipolar reverse conducting semiconductor element includes a first conductivity type second semiconductor layer (drift layer), a second conductivity type second semiconductor layer (p buried collector layer), and a first conductivity type second semiconductor region (second semiconductor layer). A third semiconductor layer (n buffer layer) of the first conductivity type is provided between the first short circuit region and the short circuit region.

The semiconductor element according to the present invention is the above-described invention,
A bipolar reverse conducting semiconductor element includes a first conductivity type second semiconductor layer (drift layer), a second conductivity type second semiconductor layer (p buried collector layer), and a first conductivity type second semiconductor region (second semiconductor layer). Short circuit region) A third semiconductor layer (n buffer layer) of the first conductivity type is further provided between the third semiconductor region (p trench collector).

The semiconductor element according to the present invention is the above-described invention,
The first conductive type second semiconductor layer (drift layer) of the bipolar reverse conducting semiconductor element has a super junction structure.

The semiconductor element according to the present invention is the above-described invention,
First conductive type fourth semiconductor region provided between the first conductive type second semiconductor layer (drift layer) and the second conductive type third semiconductor region (p-trench collector). On the upper part of the (n trench buffer region), a second insulating film is formed on the first conductivity type second semiconductor layer (drift layer) and the second conductivity type third semiconductor region (p trench collector). It is provided in contact with each other.

The semiconductor element according to the present invention is the above-described invention,
The first conductive type first semiconductor layer (drain layer) is formed of a Si semiconductor.

In the following, the effects brought about by the above means will be described. In order to simplify the complicated explanation due to the mixture of the names of the parts unique to each bipolar reverse conducting semiconductor element, a representative example of a bipolar reverse conducting semiconductor element will be described. A description will be given by taking an n-channel type reverse conducting IGBT as an example and adding it in parentheses. Since the first main electrode (first collector electrode) and the second main electrode on the back surface of the element (second collector electrode, which is also the drain electrode of the MOSFET function unit) are electrically connected, the complexity is reduced. In order to avoid this, it will be simply referred to as a collector electrode in the following description unless it is necessary to explain it separately.

According to the present invention, a bipolar reverse conducting semiconductor element having a larger N than the conventional element can be realized by the above configuration. This is because the rated output current required for steady-state operation of the power conversion device is supplied to the second functional element portion (MOSFET) of the bipolar reverse conducting semiconductor element at a voltage lower than the built-in voltage of the first bipolar operation functional element portion (IGBT). When the voltage exceeds the built-in voltage, the first functional element unit (IGBT) outputs the overload current necessary for the overload operation of the power converter. In other words, this is because the conventional bipolar reverse conducting semiconductor element cannot be energized and is output to the second functional element part (MOSFET) at a voltage equal to or lower than the built-in voltage that caused a large loss. In addition, the loss of the second functional element portion (MOSFET) is remarkably reduced by applying a trench gate structure, a super junction structure, or a SiC semiconductor.
Moreover, 1.5-4 can be achieved as N exceeding a conventional need by this, Naturally, the bipolar reverse conduction semiconductor element which also covers the conventional needs with N of about 1-1.5 is realizable.

According to the present invention, a bipolar reverse conducting semiconductor element that can achieve both low on-resistance and high mechanical strength can be realized by the above configuration. This is because the mechanical strength realization region and the electrical property realization region are separated.
That is, using a thick semiconductor substrate that can withstand various stresses received in the process of manufacturing a bipolar reverse conducting semiconductor element, a first semiconductor layer (p buried collector conductive layer) of the second conductivity type is formed on the front surface thereof. And forming a mechanical strength realization region by forming a first conductivity type first semiconductor layer (drain layer) provided with a plurality of first conductivity type first semiconductor regions (first short-circuit regions) penetrating this layer. ing.
On the other hand, a desired electrical property realization region is formed on the mechanical strength realization region. In this electrical property realization region, the upper part of the cell and the third main electrode thereon are provided on the first conductivity type second semiconductor layer (drift layer) on the second conductivity type second semiconductor layer (p buried collector layer). While forming the (emitter electrode), the second conductive type third semiconductor region (p trench collector) is in contact with the second conductive type second semiconductor layer (p buried collector layer) and the first conductive type second semiconductor layer is formed. A first main electrode (first collector electrode) is provided on the front surface of the semiconductor layer (drift layer). Here, the upper portion of the cell mainly means a JFET region between the p body region and the regions p body regions incorporated therein.
There are changes depending on the element structure. For example, in the case of a trench gate type element, the JFET region is deleted and replaced with a trench gate oxide film and a gate electrode.
Thus, the first functional element portion (IGBT) is placed between the third main electrode (emitter electrode) and the first main electrode (first collector electrode) in the characteristic realization region on the thick semiconductor substrate which is the mechanical strength realization region. It can be included. As a result, a drift layer having an appropriate thickness and an appropriate impurity concentration according to the breakdown voltage can be easily formed almost independently without being restricted by mechanical strength, and a low on-resistance can be achieved.
On the other hand, the second functional element portion (MOSFET) is also included in the electrical property realization region except for the first conductive type first semiconductor layer (drain layer) and the second main electrode (drain electrode). The first conductive type second semiconductor layer (drift layer) having an appropriate thin thickness and an appropriate impurity concentration according to the withstand voltage can achieve low on-resistance without being restricted by mechanical strength. The first conductivity type first semiconductor layer (drain layer) exists in the thick mechanical strength realization region, but it is only required to have a function as a current path. Therefore, if the impurity concentration is increased, the second functional element (MOSFET) The characteristics are not impaired, and the thickness is sufficiently thick so that the mechanical strength necessary for the mechanical strength realization region is not impaired.
The first conductive type first semiconductor layer (drain layer) connects the second main electrode (drain electrode) to the first main electrode (first collector electrode), so that the first functional element portion (IGBT). It also serves as a path for electron current in the second semiconductor layer (drift layer) of the first conductivity type at the time of turn-off. However, this layer only needs to have a function as a current path, so that it does not impair the device characteristics by making the impurity concentration sufficiently high, and it does not impair the mechanical strength necessary for the mechanical strength realization region as described above. You can avoid the problem.
Thus, the first problem can be solved by using a semiconductor element configuration in which the characteristic realization region and the strength realization region are separated.

Further, according to the present invention, with the above configuration, a large overload current up to the absolute maximum rated current of the bipolar reverse conducting semiconductor element (reverse conducting IGBT) can be caused to flow with a relatively low loss in the overload operation region. In the steady operation region, it is possible to realize a bipolar reverse conducting semiconductor element (reverse conducting IGBT) capable of flowing a steady operating current corresponding to (absolute maximum rated current / overload factor N) with extremely low loss.
In a conventional bipolar reverse conducting semiconductor element (reverse conducting IGBT), it functions only as a first functional element unit (IGBT) in both the steady operation region and the overload operation region of the power conversion device, and mainly the conductivity modulation effect. The main objective was to enjoy the low loss due to the low on-resistance caused by. For this reason, in order to reduce the adverse effect due to the snapback phenomenon, the current flowing below the voltage Vsb, that is, the on-current Isb of the second functional element section (MOSFET) is suppressed to a very small current as much as possible.
However, in the present invention, at a voltage lower than the built-in voltage at which the first functional element unit (IGBT) cannot be energized, the on-current Isb of the second functional element unit (MOSFET) is increased to the steady operating current level to achieve steady operation and extremely low Has the function of flowing loss. On the other hand, during the overload operation, the first functional element unit (IGBT) is provided with a function of flowing a large current with a low loss until reaching the absolute maximum rated current.
In this way, a steady operating current is allowed to flow through the second functional element (MOSFET) with a remarkably low loss in the voltage range below the built-in voltage without impairing the overload performance of the first functional element (IGBT). A bipolar reverse conducting semiconductor element is realized. Thereby, the second problem can be solved.

Note that the width Wn of the n short-circuit portion is increased in order to make the current of the second functional element portion (MOSFET) as large as possible a steady operating current and low loss, and to increase the generation rate of residual carriers as quickly as possible. preferable. On the other hand, in order to realize a significantly low on-resistance of the bipolar reverse conducting semiconductor element (reverse conducting IGBT), the width Wp and thickness of the buried p collector region of the first functional element portion (IGBT) are increased and the impurity concentration is increased. In addition, it is preferable to increase the width of the p-trench collector or to increase the impurity concentration. As a result of various investigations on the dependency on the width and impurity concentration and the mutual relationship between Wn and Wp, the ratio of Wn and Wp has an appropriate range, and Wn / Wp is preferably in the range of 0.5 to 2.0. I have found that.

Further, according to the present invention, the pilot IGBT portion is provided in the first functional element portion (IGBT), and the collector width is increased without increasing the occupied area in the chip so that the snapback phenomenon is effectively achieved. Is suppressed. Here, suppression of the snapback phenomenon is defined as reducing Vsb and Isb in the snapback phenomenon and reducing dVsb / dt and dIsb / dt, and will be described in accordance with this definition below. For this reason, the second-conductivity-type third semiconductor region (p-trench collector) provided to solve the above first problem also functions as a collector of the pilot IGBT portion, thereby suppressing the snapback phenomenon more effectively. doing.
That is, the second conductive type third semiconductor region (p-trench collector) functions as a current path that collects the collector current of each IGBT cell and flows it to the first main electrode (first collector electrode). It functions as a collector constituting a contact cell and a lateral bipolar semiconductor element (lateral IGBT) and is utilized as a collector for bipolar semiconductor element (pilot IGBT) function. (Therefore, it is named as a trench collector). Further, the second conductivity type third semiconductor region (p trench collector) is the second conductivity type of the pilot bipolar semiconductor element portion (pilot IGBT) provided on the back surface of the first conductivity type second semiconductor layer (drift layer). Is connected to the second semiconductor layer (p buried collector layer), and the second conductive type second semiconductor layer (p buried collector layer) at this connection portion is also used as a pilot semiconductor element (pilot IGBT) function collector. We are making use. This connection is below the field area. The field region is a region between the second conductivity type first semiconductor region (p body region) and the second conductivity type third semiconductor region (p trench collector) provided for relaxing the electric field and securing the breakdown voltage of the element. is there. Since the width needs to be at least the distance corresponding to the thickness of the first conductivity type second semiconductor layer (n drift layer), the second conductivity type third semiconductor region (p trench collector) is not provided. Compared to the case, the snapback phenomenon can be more effectively suppressed by the second conductive type second semiconductor layer (p buried collector layer) of that width.
As described above, by utilizing the second conductivity type third semiconductor region (p trench collector) and the second conductivity type second semiconductor layer (p buried collector layer) in the field region, the snapback phenomenon is more effectively prevented. When the suppression effect can be made the same, the area required for suppressing the snapback phenomenon can be further reduced accordingly. In this way, the third problem can be solved.

According to the present invention, when the first conductive type fourth semiconductor region (n trench buffer) is provided in contact with the outer periphery of the second conductive type third semiconductor region (p trench collector), the pilot is more effectively provided. It can function as a bipolar semiconductor element part (pilot IGBT).

According to the present invention, the snapback phenomenon can be further greatly suppressed by using a wide gap semiconductor. The snapback voltage Vsb in the snapback phenomenon is, for example, approximately the sum of the voltage drop at the channel resistance, the voltage drop at the drift resistance, and the built-in voltage in the case of the reverse conducting IGBT. The voltage drop across the resistor is the largest. In the case of the wide gap bipolar reverse conducting semiconductor element, the voltage drop due to the resistance of the drift layer can be remarkably reduced as compared with the Si bipolar reverse conducting semiconductor element. For example, in the case of a 4H-SiC bipolar reverse conducting semiconductor element, the resistance of the drift layer can theoretically be greatly reduced to about 1/1000 compared to the Si element when the element has the same breakdown voltage, so Vsb is greatly reduced. it can. Even if the built-in voltage is 2.7 V as compared with the Si bipolar reverse conducting semiconductor element, which is about four times larger, Vsb can be greatly reduced and the steep voltage change dVsb / dt can be greatly suppressed. This means that the snapback phenomenon can be suppressed with a small area. Therefore, the third problem can be solved more effectively.
In addition, when the strength realization region is formed of a Si semiconductor and the characteristic realization region is formed of a 3C-SiC semiconductor, the difference in crystal lattice spacing between the Si semiconductor and the 3C-SiC semiconductor is extremely small, and 3C having a good crystal quality on the Si semiconductor substrate. -Since a SiC semiconductor can be easily formed, Vsb can be reduced and the snapback phenomenon can be suppressed with a small area as described above. Furthermore, the Si single crystal substrate is less expensive than the SiC substrate, and can be easily increased in diameter and is excellent in economic efficiency. In addition, even if the crystal is high quality and has a high impurity concentration, there are few crystal defects and a low resistivity can be easily realized, which greatly contributes to a reduction in loss of the element in the characteristic realization region. Therefore, the third problem can be solved more effectively.

Further, according to the present invention, an insulating film such as SiO ₂ is provided only in the vicinity of the front surface of the element in contact with the outer periphery of the second conductivity type third semiconductor region (p trench collector), and the first deeper inside. By providing the conductive type fourth semiconductor region (n-trench buffer), the leakage current can be reduced and the adverse effect of the surface leakage current of the element front surface and the surface electric field on the breakdown voltage can be suppressed. High breakdown voltage can be achieved stably.
Further, the increase in Vsb with time in the above snapback phenomenon can be largely suppressed by an insulating film such as SiO ₂ formed in the vicinity of the surface. That is, due to the presence of an insulating film such as SiO ₂ , hole injection occurs in the vicinity of the boundary between the first conductive type fourth semiconductor region (n-trench buffer) inside the device, and the first functional device portion (IGBT portion). Can be turned on from inside the device. As a result, it is possible to avoid the adverse effects of stacking faults that are formed due to processing distortions during manufacturing existing in the vicinity of the element front surface, so that the increase in Vsb with time can be suppressed. On the other hand, even if an insulating film such as SiO ₂ is provided in the vicinity of the front surface, the voltage drop caused by the first conductive type fourth semiconductor region (n-trench buffer) inside can be utilized, so that the effect of suppressing the snapback phenomenon is great. It will not be damaged. In this way, by changing the boundary position between the insulating film and the fourth semiconductor region (n trench buffer) of the first conductivity type and bringing it closer to the front surface, the effect of suppressing the snapback phenomenon is increased. It is also possible to reduce the change with time of the snapback phenomenon as the distance from the surface increases.

According to the present invention, when the bipolar reverse conducting semiconductor element is a reverse conducting IGBT, the trench gate structure can be used to further reduce the loss during steady operation or overload.

In addition, according to the present invention, the loss during steady operation can be further greatly reduced by making the first conductivity type second semiconductor layer (drift layer) of the bipolar reverse conducting semiconductor element have a super junction structure.

As described above, according to the present invention, the absolute maximum rated current corresponding to the overload current at the time of overload can be output with low loss, and the steady operation corresponding to (absolute maximum rated current / overload ratio N) at the time of steady operation. A bipolar reverse conducting semiconductor element capable of outputting a current with significantly low loss can be realized. In addition, a bipolar reverse conducting semiconductor element that has sufficient mechanical strength and low loss characteristics to withstand various stresses during work in the wafer state at the time of manufacture and in the chip state at the time of mounting can be avoided from damage and destruction. realizable. Further, a bipolar reverse conducting semiconductor element that suppresses the snapback phenomenon with a small area can be realized, and the economy can be improved.

Typical sectional drawing of the semiconductor element concerning Example 1. FIG. Typical sectional drawing of the semiconductor element concerning Example 2. FIG. Typical sectional drawing of the semiconductor element concerning Example 3. FIG. Typical sectional drawing of the semiconductor element concerning Example 4. FIG. Manufacturing flow explanatory drawing of the semiconductor element concerning Example 4. Typical sectional drawing of the semiconductor element concerning Example 6. FIG. Schematic sectional view of a semiconductor device according to Example 7. Schematic sectional view of a semiconductor device according to Example 7. Sectional drawing of the high voltage | pressure-resistant Si reverse conduction IGBT element of the prior art example 1 Sectional drawing of the high voltage | pressure-resistant Si reverse conduction IGBT element of the prior art example 2

Exemplary embodiments of a semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings. The thickness and length of each layer and each region in the figure are not proportional to the dimensions described in the specification. Further, in this specification and the accompanying drawings, in the layers and regions having n or p, it means that electrons or holes are majority carriers, respectively, but in order to avoid the complexity of the drawings and to make it easy to see It is not necessarily described in the layer or area. Further, + and − attached to n or p mean that the impurity concentration is higher and lower than that of a layer or region where it is not attached. Numbers and arrows indicating layers and regions in the drawing are the same layer and region, and only one representative is shown for each, and others are omitted, and they are not necessarily concentrated on a specific cell and are distributed over a plurality of cells. It is easy to see by avoiding the complexity of the drawing.
In the following description of the drawings, the right and left direction of the paper surface is referred to as the horizontal direction, the up and down direction is referred to as the vertical direction, and the direction perpendicular to the paper surface is referred to as the vertical direction.

(Example 1)
FIG. 1 is a cross-sectional view schematically showing a semiconductor element according to the first embodiment. The semiconductor device of Example 1 shown in FIG. 1 has a design breakdown voltage of 1 produced using a silicon carbide having a four-layer hexagonal structure (normally written as 4H—SiC but hereinafter simply written as SiC). It is a SiC reverse conducting IGBT 100 having a planar gate structure of 2 kV class, a rated output current of 40 A, and an absolute maximum rated current of 90 A class. Therefore, the overload factor N is 2.25, and continuous energization for 60 seconds or more can be performed with a margin of 90 A absolute maximum rated current at the time of overload.

First, the detailed configuration of the present embodiment will be described.
FIG. 1 shows only a part of the active region of the SiC reverse conducting IGBT 100. The SiC reverse conducting IGBT 100 includes a breakdown voltage structure (not shown) so as to surround the active region, for example. The active region is a region through which a current flows when the semiconductor element is turned on, and the breakdown voltage structure portion is a structure portion that relaxes the electric field strength on the pn junction surface constituting the semiconductor element and realizes a desired breakdown voltage.
The chip size of the SiC reverse conducting IGBT 100 is 8.8 mm × 4.4 mm, and the active area is about 8 mm × 4 mm. The reverse conducting IGBT cell in the active region is striped and the width of the cell is about 15 microns. The width of the pressure-resistant structure portion surrounding the active region is about 0.2 mm in the horizontal direction including the dicing portion. On the other hand, the direction perpendicular to the paper surface is 0.4 mm, and the wire bonding pad for the collector electrode is provided at the end in the longitudinal direction of the cell, and the wire bonding for the emitter electrode is provided at the other end. A pad is provided. The cells in the active region constitute a group cell for every 10 cells, and p-trench collectors 115 are provided at both ends of the group cell. FIG. 1 shows about 1.35 group cells. In the right group cell, only the trench collectors at both ends and 4 out of 10 cells are shown, and 6 cells near the center are rectangular broken lines. Although it is provided in the area, it is omitted and not shown in order to avoid the figure being too complicated and too large. In the group cell on the left, only three and a half cells are shown and others are omitted. The trench collector and the nearest cell are separated to ensure a breakdown voltage of 1.2 kV, and the distance may be, for example, 15 micrometers, or surface electric field relaxation means may be provided. The thickness of the chip is about 300 μm.
In order to facilitate the explanation of the operation mechanism of the present embodiment, three current routes are indicated by dotted lines with arrows in FIG.

As shown in FIG. 1, in the SiC reverse conducting IGBT 100 of the present embodiment, the n ⁺ drain 102 having a thickness of about 270 μm is in contact with the second collector electrode 101 and the back surface is in contact with the p-type buried surface. A collector conductive layer 120 and a first short-circuit region 121 are provided, and a p-buried collector layer 103 and a second n ⁺ short-circuit region 104 penetrating this layer are provided on the front surface of the collector conductive layer 120 and the first short-circuit region 121. Is provided. An n buffer layer 105 is provided on the front surfaces of these regions 103 and 104. The impurity concentration and thickness of the p buried collector conductive layer 120 may be, for example, 1 × 10 ²¹ cm ⁻³ and 15 μm, respectively, and the resistivity is about 0.02 Ωcm. Further, the impurity concentration and the thickness of the p buried collector region 103 may be, for example, 1 × 10 ¹⁸ cm ⁻³ and 1.5 μm, respectively. The impurity concentration of the n ⁺ short-circuit portion penetrating the p buried collector conductive layer 120 may be 1 × 10 ²¹ cm ⁻³ , and the impurity concentration of the n ⁺ short-circuit portion 104 penetrating the p buried collector layer 103 is 5 It may be × 10 ¹⁹ cm ⁻³ . Further, the impurity concentration and thickness of the n buffer layer 105 may be, for example, 3 × 10 ¹⁶ cm ⁻³ and 0.8 μm, respectively. In each cell, the n ⁺ short-circuit portion 103 may be provided near the center of the cell, and its width may be 8 μm. The distance between n ⁺ short-circuited portion, which corresponds to the width of the p buried collector layer, may be 7 μm.

An n drift layer 106 is provided on the front surface of the n buffer layer 105. The n drift layer 106 is a SiC epitaxial layer. The impurity concentration of the n drift layer 106 is less than or equal to the impurity concentration of the n buffer layer 105. Specifically, the impurity concentration and thickness of the n drift layer 106 may be, for example, 1 × 10 ¹⁶ cm ⁻³ and 13 μm, respectively.

A plurality of p body regions 107 are selectively provided on the surface layer of the n drift layer 106. The impurity concentration of p body region 107 is higher than the impurity concentration of n drift layer 106. For example, the impurity concentration of p body region 107 and the thickness from the front surface of the element may be 1 × 10 ¹⁸ cm ⁻³ and 0.6 μm, respectively. The width of n drift layer 106 sandwiched between adjacent p body regions 107 may be, for example, 6 μm. The p body region 107 is a layer formed by, for example, aluminum ion implantation.

Since the SiC semiconductor has less impurity diffusion in the direction perpendicular to the depth direction than the silicon semiconductor, the semiconductor layer is shown in a rectangular shape in FIG. 1 (hereinafter, the same applies to the reverse conducting IGBT shown in each figure). The semiconductor layer is illustrated in a rectangular shape).

In the surface layer of each p body region 107, two n ⁺ emitter regions 108, two p ⁻ low-concentration channel regions 109 and a p ⁺ contact region 110 are selectively provided. The n ⁺ emitter region 108, the p ⁻ low-concentration channel region 109, and the p ^{+ contact} region 110 are semiconductor regions formed by ion implantation. The p ⁻ low concentration channel region 109 is provided at the end of the p body region 107 and is in contact with the n drift layer 106. The n ⁺ emitter region 108 is in contact with the end of the p ⁻ low-concentration channel region 109 opposite to the end in contact with the n drift layer 106.

The end of the n ⁺ emitter region 108 on the side not in contact with the p ⁻ low concentration channel region 109 is in contact with the p + contact region 110. P provided in each p body region 107 ^- low-concentration channel region 109 and ^{n +} emitter region 108, p other p body regions 107 adjacent ^- placed in a low concentration channel region 109 and ^{n +} emitter region 108 and the symmetrical Has been.

The p ⁻ low concentration channel region 109 and the n ⁺ emitter region 108 are formed in the surface layer of the p body region 107 by ion implantation. The impurity concentration of the p ⁻ low concentration channel region 109 is lower than the impurity concentration of the p body region 107. Specifically, the impurity concentration and thickness of the p ⁻ low-concentration channel region 109 may be 3 × 10 ¹⁶ cm ⁻³ and 0.3 μm, respectively, for example. The channel length may be 1.0 μm.
The impurity concentration and thickness of the n ⁺ emitter region 108 may be, for example, 5 × 10 ¹⁹ cm ⁻³ and 0.3 μm, respectively, and the horizontal width may be, for example, 2.5 μm.
The impurity concentration of the p ^{+ contact} region 110 may be 1 × 10 ¹⁹ cm ⁻³ , for example.

A gate electrode (control electrode) 112 is provided on the surface of the p ⁻ low-concentration channel region 109 via a gate insulating film 111. The thickness of the gate insulating film 111 may be about 500 angstroms. The emitter electrode 114 is in contact with the n ⁺ emitter region 108 and also in contact with the p ⁺ contact layer 110, and is in electrical contact with the p body region 107 through the p ⁺ contact layer 110. The emitter electrode 114 is insulated from the gate electrode 112 by the interlayer insulating film 113 and the gate insulating film 111. Between the emitter electrode 114 and the first collector electrode 119, an insulator (not shown) such as a high breakdown voltage / high heat resistant resin is provided and insulated from each other. This insulator may cover the entire front surface of the chip, and may be opened in a state that does not impair the withstand voltage only at a portion where wire bonding of each electrode is necessary, and a bonding pad may be provided.
The n ⁺ short-circuit portion 104 may preferably be opposed to the p body region 107 so that the center positions in the horizontal direction substantially overlap each other.

The cells are grouped, for example, in units of 10 to form a group cell, and a p ⁺ trench collector region 115 is provided between each group. The impurity concentration and thickness of the p ⁺ trench collector region 115 may be, for example, 1 × 10 ²⁰ cm ⁻³ and 16 μm, and the width may be 15 μm. An n trench buffer region 116 is provided between the n drain region 106 and the p ⁺ trench collector region 115 to prevent excessive holes from being injected from the p ⁺ trench collector region 115 to the n drain region 106. Also good. The n trench buffer layer 116 may have the same impurity concentration and thickness as the n buffer layer 105, that is, 3 × 10 ¹⁶ cm ⁻³ and 0.8 μm.
A plurality of cells between the horizontal centers of adjacent p ⁺ trench collector regions 115 are defined as group cells (supplied in the drawing), and the distance between the centers is hereinafter referred to as a group cell width. This width includes the distance between the cells at both ends of the group cell and the respective p ⁺ trench collector regions 115 facing them, that is, the width of the field region for electric field relaxation. An n-channel is formed on the front surface near the middle of the field region in order to suppress the influence of leakage current which is particularly problematic when the interface state between the front surface and the surface protective film 130 such as an oxide film is not good. A stopper 122 may be provided.

The p ⁺ trench collector region 115 is provided so as to penetrate at least the n drift layer 106 and the n buffer layer 105 and to be in contact with the p buried collector region at the end of the group cell. The p buried collector at the end of the group cell extends from the n short-circuit region 104 of the end cell to the horizontal center position of the p ⁺ trench collector region 115, and the p of the cells other than the end cell. It is wider than the buried collector 103. Hereinafter, it is referred to as a p buried end collector 117. The p ⁺ trench collector layer 115 is preferably as low a resistance as possible. The n trench buffer region 116 may have the same impurity concentration and thickness as the n buffer layer 105. For example, in order to suppress excessive hole injection from the p ⁺ trench collector region 115 and reduce the turn-off speed, It may be thicker at higher concentrations. On the other hand, in order to increase the voltage drop in the n buffer layer 105 and suppress the snackback phenomenon, the n buffer layer 105 may be made thinner at a lower concentration. That is, it is preferably set in consideration of a desired hole injection amount and a desired voltage drop.
A first collector electrode 119 is provided on the exposed surface on the main surface side of p ⁺ trench collector region 115. The width of the exposed surface of the p ⁺ trench collector region 115 may be about 15 μm. The width of the group cell is about 200 μm, for example.

The p buried collector layer 103 of each group cell is connected to the p ⁺ trench collector regions 115 at both ends in each group cell. Further, since the n ⁺ short-circuit region penetrates, the planar shape of the p buried collector layer is mesh. The horizontal width of the penetrating n ⁺ short-circuit region is constant, for example, 8 μm, but the vertical width may be 7.5 μm. The resistance of the p buried collector layer 103 can be controlled by changing the vertical width of the n ⁺ short-circuit region. For example, the resistance of the p buried collector layer 103 can be reduced by reducing the width in the vertical direction.
The p buried collector conductive layer 120 is also in a mesh shape, and in this embodiment, the shape is the same as the mesh shape of the p buried collector layer 103. However, they may be different, and the resistance of the p buried collector conductive layer 120 can be similarly controlled by independently changing the vertical width of the n short-circuit region of the p buried collector conductive layer 120. The resistance of the p buried collector layer and the resistance of the p buried collector conductive layer are connected in parallel to the p ⁺ trench collector region 115. Since the latter is thick at a high impurity concentration, it has a greater influence on the collector resistance reduction effect than the former. have.

Hereinafter, the operation of this embodiment and the mechanism for suppressing the snapback phenomenon will be described.
First, when a gate voltage of about 20 V is applied and a forward voltage is applied and increased between the collector electrode and the emitter electrode 114, the route schematically shown by dotted lines a and b in FIG. MOSFET current flows in a number of routes including the total, and the sum of these functions as, for example, a steady operation current.
At that time, the emitter electrode 114, the emitter region (functioning as a source region) 108, the channel region 109, the field region, and the n-trench buffer region 116 are also used in the cells at both ends of each cell group, even in the route schematically shown by the dotted line c in FIG. Electron current flows through the n buffer layer 105, the n short-circuit regions 104 and 121, the n drain layer 102, and the second collector electrode 101 on the p buried end collector layer 117. This electron current causes an electric field drop in the n buffer layer, but the electric field drop is maximized near the front surface of the n trench buffer 116 farthest from the short-circuit region 104. When the applied voltage between the collector electrode and the emitter electrode is increased and this electric field drop exceeds the built-in voltage of 2.7 V, holes are injected near the front surface, and the IGBT part functions as a lateral IGBT and turns on. To do. Once this IGBT portion is turned on, the resistance of this IGBT portion is greatly reduced due to the conductivity modulation effect, and a large bipolar current (a combined current of a hole current and an electron current) flows. This current spreads and the entire cell at the end is turned on to allow a larger current to flow, and the voltage drop in the n buffer layer increases in the adjacent cell due to the larger current spread, thereby increasing the p buried collector. Hole injection occurs from 103, the adjacent cell is turned on, and a larger current flows. By repeating this, adjacent cells are turned on one after another, and finally the whole is turned on. In this way, all the group cells are turned on, eventually the entire reverse conducting IGBT is turned on, and a large current corresponding to the overload current flows. The turn-on time required during this period is a short time of about several tens of nanoseconds.

When the p ⁺ trench collector region 115 peculiar to the present embodiment is not provided, the electric field drop in the half buffer layer portion on the 7 μm wide p buried collector 103 by the electron current route of a and b in FIG. Hole injection occurs from the vicinity of the central portion of the buried collector 103, and the IGBT portion is turned on. Accordingly, since the length of the buffer layer portion where the field effect is generated is as short as about 3.5 μm, the resistance in the buffer layer for generating the voltage drop is small, so that the electric field drop with a built-in voltage of 2.7 V is generated in the n buffer layer. Requires a very large electron current. The snap-back voltage Vsb of the reverse conducting IGBT is a voltage immediately before the injection of holes in the n buffer layer and the IGBT portion is turned on, and can be approximated by the following equation.

Vsb = (Voltage drop at channel resistance) + (Voltage drop at drift resistor) + (Built-in voltage)

In the case of the present embodiment of the 1.2 kV class, since the drift resistance is larger, the voltage drop in the drift layer is increased and Vsb is also increased. As a result, dIsb / dt due to the snapback phenomenon is, for example, about 4240 A / μs, and dVsb / dt is about −70 V / μs, which greatly affects the circuit.

On the other hand, when the p ⁺ trench collector region 115 peculiar to the present embodiment is provided, hole injection occurs when the voltage drop at the n buffer portion in the route indicated by the dotted line c in FIG. The width of the n buffer layer in the present embodiment is the sum of the original pilot IGBT p ⁺ the width of the n buffer on the buried collector, the p ⁺ width of the buried collector below the field region, and the width of the n trench buffer region 116. Composed. Since each of them is about 15 μm, the total is about 45 μm. Compared to the case where the p ⁺ trench collector region 115 is not provided, the built-in voltage is reached with about 13 times longer, and accordingly with a smaller electron current. Since the electron current is small in this way, Vsb is greatly reduced, and as a result, the snap phenomenon can be greatly suppressed.
In the above example, the n trench buffer layer 116 has an impurity concentration of 3 × 10 ¹⁶ cm ⁻³ and a thickness of 0.8 μm, which is the same as that of the n buffer layer 105. However, the following effects can be exhibited by changing the impurity concentration. That is, by increasing the impurity concentration with the same thickness, the resistance value of the n-trench buffer layer is decreased, or the injection of holes from the p ⁺ trench collector region 115 is suppressed, so that the snapback phenomenon occurs. The current Isb can be increased. On the other hand, Isb can be reduced by lowering. Further, by increasing the thickness, the resistance value and the hole injection can be decreased to increase Isb, and conversely, by decreasing the thickness, Isb can be decreased. Since Isb can be regarded as the upper limit value of the rated output current during steady operation, therefore, Isb can be set to a desired value according to the impurity concentration and thickness of the n trench buffer region 116 in accordance with the rated output current during steady operation. Become.

Next, a method for manufacturing the SiC reverse conducting IGBT 100 schematically shown in FIG. 1 will be described focusing on the process flow. Also, the description of the processes that normally accompany the annealing process after ion implantation, the process of removing the resist used as a photomask, and the cleaning process will be complicated and will be described with a focus on the main processes.
First, using an off-angle n ⁺ high impurity concentration SiC substrate having a thickness of about 280 μm, a resist mask having an opening that exposes the formation region of the p buried collector conductive layer 120 on the front surface is formed. A trench groove having a depth of about 11 μm is formed by plasma etching using the resist mask as a mask.
Next, a high impurity concentration p-layer having a specific resistance of about 0.02 Ωcm is formed by epitaxial growth. For this growth, not only vapor phase growth but also various growth methods such as a liquid phase epitaxial growth method can be applied. Thereafter, the p epitaxial layer on the n ⁺ SiC substrate is removed by polishing, and further precision polishing of about 1 μm is performed to form a p ⁺ buried collector conductive layer 120 having a depth of about 10 μm. At this time, the n ⁺ short-circuit region 121 is also formed at the same time.

Next, a p-layer having a thickness of 1.5 μm is formed by epitaxial growth, and a resist mask having an opening that exposes the n ⁺ short-circuit region 121 that forms the n ⁺ short-circuit region 104 is formed. The n ⁺ short-circuit region 104 is selectively formed by nitrogen ion implantation using the mask as a mask. As a result, the p buried collector region 103 and the p buried end collector region 117 are simultaneously formed on the p buried collector conductive layer 120.

Thereafter, an n buffer layer 105 and then an n drift layer 106 are sequentially formed by epitaxial growth. Next, a resist mask having an opening that exposes the formation region of the p ⁺ trench collector region 115 is formed on the surface of the n drift layer 106, and the p buried end collector region is formed by plasma etching using the resist mask as a mask. A trench groove reaching 117 is formed.

Next, in order to form the n-trench buffer region 116, nitrogen ions are selectively implanted into the trench groove surface, and then only the ion implanted layer on the trench groove bottom surface is selectively removed. Further, after forming a p ⁺ layer having a thickness enough to fill the trench groove by epitaxial growth, the p ⁺ epitaxial layer other than the trench groove is removed by polishing to smooth the wafer surface. Depending on the condition of the exposed surface, fine polishing for finishing may be performed. By performing these polishing steps, p ⁺ trench collector region 115 and n trench buffer region 116 are formed.

Next, a resist mask having an opening through which the formation region of the p body region 107 is exposed is formed on the surface of the n drift layer 106. Then, using this resist mask as a mask, aluminum which is a p-type impurity is ion-implanted into the n drift layer 106 exposed at the opening of the resist mask. At this time, in order to form the p ^- low concentration channel region 109 having an impurity concentration lower than that of the p body region 107 in the surface layer of the p body region 107 in a later process, the impurity concentration of the shallow portion of the p body region 107 is reduced. It is preferable to perform multiple ion implantations so that the impurity concentration in the deep portion is lower.

Next, a resist mask having an opening through which the p ⁺ contact formation region 110 is exposed is formed on the surface of the p body region 107, and p type impurities are ion-implanted to form the p ⁺ contact region 110.
Further, a resist mask having an opening through which the formation region of the p ⁻ low concentration channel region 109 is exposed is formed, and impurity ions are implanted to form the p ⁻ low concentration channel region 109.

In the ion implantation for forming the p ⁻ low concentration channel region 109, when the impurity concentration of the surface layer of the p body region 107 is lower than the desired impurity concentration of the p ⁻ low concentration channel region 109, the p ⁻ low concentration A p-type impurity concentration is ion-implanted so that the channel region 109 has a desired impurity concentration. On the other hand, the impurity concentration of the surface layer of the p-body region 107 is p ^- low concentration is higher than desired impurity concentration of the channel region 109, p ^- n-type so that the low concentration channel region 109 has a desired impurity concentration Impurity concentration is ion-implanted.
Next, a resist mask having an opening exposing the formation region of the n ⁺ emitter region 108 is formed, and n-type impurity ions are ion-implanted to selectively form the n ⁺ emitter region 108. Next, a gate insulating film 111 is formed on the surface, and a polycrystalline silicon gate electrode 112 is selectively formed. Next, an interlayer insulating film 113 is formed, and the gate electrode 112 is covered with the interlayer insulating film 113.

Next, the interlayer insulating film 113 and the gate insulating film 111 are selectively removed by photolithography, and a contact hole for connecting the n ⁺ emitter region 108 and the p ⁺ contact layer forming region 110 with the emitter electrode 114 and the p ⁺ A contact hole for connecting the trench collector and the first collector electrode 119 is formed. Next, a metal film is formed on the front surface including the inside of the contact hole, and further a metal film for the second collector electrode is formed on the back surface. Next, the emitter electrode 114 and the first collector electrode 109 are separately formed by photoetching of the metal film on the surface. Further, dicing is performed to complete the reverse conducting IGBT element 100 whose part is schematically shown in FIG.

In the above manufacturing method, the p buried collector conductive layer 120 is formed by being buried in the trench groove of the n ⁺ high impurity concentration SiC substrate using the epitaxial technique, but the following method may be used. That is, after epitaxially growing a high-concentration p buried collector conductive layer 120 on an n ⁺ high impurity concentration SiC substrate, a trench groove penetrating to the SiC substrate is formed, and then an n ⁺ high impurity concentration growth layer is formed by epitaxial growth. Alternatively, the n ⁺ short-circuit region 121 may be formed by embedding and polishing.
In the above manufacturing method, the p ⁺ trench collector region 115 is formed by burying it with epitaxial SiC, but various other methods can be applied. For example, after forming a buffer layer or the like in the trench groove, polycrystalline silicon having a high impurity concentration may be embedded. In this case, a method of forming a SiC epitaxial layer having a thickness of about 2 μm to 10 μm on the trench groove surface and then embedding a high impurity concentration polycrystalline Si also improves the crystallinity of the p ⁺ trench collector region 115. This is effective because hole injection can be performed efficiently. In the future, a method of embedding with a low melting point metal or a carbon-based material in place of polycrystalline Si can be expected.

Next, the characteristics of the reverse conducting IGBT 100 manufactured by the above manufacturing method will be described.
The reverse conducting IGBT 100 was mounted in a TO type high voltage package and used for an operation test. That is, the second collector electrode 101 of the reverse conducting IGBT chip is soldered to the die bonding lead frame of the package, and further, the collector pad that collects the first collector electrode provided on the reverse conducting IGBT chip and the die bonding lead described above. The frame was connected with a plurality of Al wires, and the first collector electrode 101 and the second collector electrode 119 were electrically connected. Further, the emitter electrode 114 and the emitter lead terminal were connected by a plurality of Al wires, and the gate pad on the chip in which the gate electrodes 113 were integrated and the gate lead of the package were connected by a plurality of Al wires. Subsequently, the chip and the Al wire were completely covered with a high heat-resistant resin for protection to form a three-terminal semiconductor device, and then subjected to an operation test.
In the description of the characteristics and the measurement method, the connected first collector electrode 119 and second collector electrode 101 are collectively referred to simply as a collector electrode in order to avoid complexity.

When a forward voltage is applied between the emitter electrode 114 and the collector electrode via the package lead terminal without applying a gate voltage, a leakage current flows, but a good forward blocking characteristic is exhibited, and a breakdown voltage at room temperature, that is, an avalanche breakdown Is about 1.34 kV. Moreover, the leakage current before avalanche breakdown is as good as 3.2 × 10 ⁻³ A / cm ² or less at room temperature and 4 × 10 ⁻² A / cm ² or less even at a high temperature of 250 ° C.

When a gate voltage of about 20 V, which is equal to or higher than the threshold voltage, is applied to the gate electrode 112 and then a forward voltage is applied between the collector electrode and the emitter electrode 114 and then increased, the energization current of the MOSFET portion increases almost linearly. A predetermined steady-state operating current of about 40 A was allowed to flow at 2 V. On-resistance is as low as about 55 mΩ. When the forward voltage is further increased, a snapback phenomenon appears and the IGBT part is turned on. When the forward voltage is further increased, 90 A corresponding to 225% overload current can be caused to flow at an on-voltage of about 3.2 V. Low loss during operation was achieved.
In the present embodiment, the on-resistance of the MOSFET part before the IGBT part is turned on is remarkably reduced by using a SiC semiconductor, and a remarkably low loss during steady operation is achieved. The remarkably low on-resistance of about 55 mΩ is a reasonable low value even considering the theoretical correlation between the SiC-MOSFET and the breakdown voltage.
In addition, during overload operation, the IGBT portion is turned on to reduce the loss by utilizing the conductivity modulation effect of SiC, and the p buried collector conductive layer 120 is provided and the p ⁺ trench collector region 115 is also provided in the group cell configuration. Thus, the resistance of the current path from the p buried collector region 103 to the collector electrode is remarkably reduced. As a result, the on-resistance of the IGBT portion can be reduced, the loss can be greatly reduced, the absolute maximum rated current capacity can be increased, and a large overload current during overload operation can be achieved with low loss. As described above, the reverse conducting IGBT according to the present embodiment has a low loss both in the steady state and in the overload state. On the other hand, the thickness is about 300 μm, and the SiC wafer as the base material is sufficient for the processing strain at the time of manufacturing the element. High mechanical strength to withstand. This is an effect obtained by separating the electrical property realization region and the mechanical strength realization region specific to the present invention to achieve both low on-resistance and high mechanical strength.
The time until the snapback phenomenon appears and the IGBT part is turned on is approximately 75 nanoseconds, dIsb / dt is approximately 285 A / μs, and dVsb / dt is approximately −10.3 V / μs. Therefore, the influence on the circuit operation is negligible in practical use, and the adverse effect of the snapback phenomenon can be greatly suppressed. This is an effect of the trench collector structure and the buried end collector structure peculiar to the present invention, and can be realized in a smaller area compared to the case where only the pilot IGBT of the conventional example is applied.
In this way, the snapback phenomenon can be largely suppressed by utilizing the p ⁺ trench collector region p ⁺ buried collector under the field region peculiar to the present embodiment in addition to the pilot IGBT as described above. In addition, the element area can be reduced as compared with a conventional structure using only a pilot IGBT.

As described above, according to the present embodiment, the low on-resistance and the high mechanical strength are not only low loss during overload operation, but also extremely low loss in the steady operation region, and the snap is further reduced in area. A reverse conducting IGBT capable of suppressing the back phenomenon can be realized.

(Example 2)
This example is a 4H-SiC reverse conducting IGBT semiconductor element having a withstand voltage of 1.2 kV class, a rated output current of 22 A, and an absolute maximum rated current of 50 A class, a chip size of 8.8 mm × 2.4 mm, and an active region of It is about 8 mm x 2 mm.

FIG. 2 is a cross-sectional view schematically showing the SiC reverse conducting IGBT semiconductor device according to the second example. Compared with the device of the first embodiment, the shape and structure of the cell are almost the same. However, the p ⁺ trench collector region 215, the first collector electrode 219, and the n trench buffer 216 are provided only at both ends of the chip. Except for the point that the resistivity of the buried collector conductive layer 220 is small and thick, and the width of the p buried collector corresponding to the pilot IGBT is long, there is no significant difference from the first embodiment.

In this embodiment, the p ⁺ trench collector region 215 and the n trench buffer 216 are not provided inside the element, but are provided only at both ends of the element, while the p buried collector conductive layer 220 is made thick and has a low resistivity to reduce the on-resistance. Achieved low loss.
In addition, since the p ⁺ trench collector region 215, the first collector electrode 219, and the n trench buffer 216 are not provided in large numbers inside the device, they can be provided only at both ends of the device, so that the manufacturing process can be simplified. That is, it is sufficient wire bonding to the first collector electrode 219 at the time of mounting the functional, with p ⁺ easy to width can greatly machining trenches collector territory 215, as the case may, not necessarily thick and approximately 16 [mu] m p ⁺ Only the first collector electrode 219 may be formed directly on the exposed end of the p buried collector layer 203 without forming the trench collector region 215, and the epitaxial process for forming the p ⁺ trench collector region 215 is simplified or omitted. it can. In this case, the voltage drop in the n-trench buffer 216 is reduced, but the width of the pilot IGBT part is increased to increase and cancel the voltage drop.

Thus, the manufacturing process can be greatly simplified as compared with the first embodiment. The simplified manufacturing process flow of this embodiment is the same as that of the first embodiment except for [0060] in the manufacturing process of the first embodiment described in [0057] to [0064] above. It is.

  Note that, when etching SiC until the p buried collector conductive layer 220 is exposed by plasma etching, the p buried collector layer 203 is preferably left to reduce the resistance as much as possible, but about 1.5 μm. Since it is thin, it may be removed by etching. In this case, the electrode 219 is directly provided on the p buried collector conductive layer 220 at the element end.

Next, characteristics and characteristics of the SiC reverse conducting IGBT according to the second embodiment will be described.
The reverse conducting IGBT 200 was mounted in a TO type high voltage package and used for an operation test. That is, the second collector electrode 201 of the reverse conducting IGBT chip is soldered to the die bonding lead frame of the package, and a plurality of the first collector electrode provided at the end of the reverse conducting IGBT chip and the die bonding lead frame are plural. The first collector electrode 219 and the second collector electrode 201 were electrically connected with a single Al wire. Further, the emitter electrode 214 and the emitter lead terminal were connected by a plurality of Al wires, and the gate pad on the chip in which the gate electrodes 213 were integrated and the gate lead of the package were connected by a plurality of Al wires. Next, the chip and the Al wire were completely covered with a protective high heat resistant resin to form a three-terminal semiconductor device, and then subjected to an operation test.
In the description of the characteristics and the measurement method, the connected first collector electrode 219 and second collector electrode 201 are collectively referred to simply as a collector electrode in order to avoid complexity.

When a forward voltage is applied between the emitter electrode 214 and the collector electrode without applying a gate voltage, a leakage current flows, but a good forward blocking characteristic is exhibited. It is. Moreover, the leakage current before avalanche breakdown is 1.5 × 10 ⁻³ A / cm ² or less at room temperature and 3 × 10 ⁻² A / cm ² or less even at a high temperature of 250 ° C.

Further, when a gate voltage of about 20 V, which is equal to or higher than the threshold voltage, is applied to the gate electrode 212, and then a forward voltage is applied between the collector electrode and the emitter electrode 214, the current flowing through the MOSFET portion increases almost linearly. As in Example 1, it was possible to pass a predetermined steady-state operating current of about 22 A with a forward voltage of 2.0 V. Accordingly, the on-resistance was as low as about 90 mΩ, and a remarkable low loss could be achieved. When the forward voltage is further increased, a snap phenomenon appears and the IGBT part is turned on. When the forward voltage is further increased, 50 A corresponding to an overload current of about 230% can be supplied at an on voltage of about 3.5 V. Low loss during load operation was achieved. The overload factor N is about 2.3, which is sufficiently higher than before.

The extremely low on-resistance of about 90 mΩ corresponds to a characteristic on-resistance of 14.4 mΩcm ^{2 in} consideration of the activation area of the element, and is appropriate even considering the theoretical correlation between the SiC-MOSFET and the breakdown voltage. It is a very low value. On the other hand, the thickness of the reverse conducting IGBT chip is about 300 μm, and it has high mechanical strength that the base SiC wafer can sufficiently withstand the processing strain during manufacture. This is an effect obtained by separating the electrical property realization region and the mechanical strength realization region specific to the present invention to achieve both low on-resistance and high mechanical strength.
The time until the snap phenomenon appears and the IGBT part is turned on is approximately 75 nanoseconds, ddIsb / dt is approximately 92 A / μs, and dVsb / dt is approximately −6.0 V / μs. Therefore, the influence on the circuit operation is a level that can be ignored in practice. This is an effect of the trench collector structure and the buried end collector structure peculiar to the present invention, and can be realized in a smaller area compared to the case where only the pilot IGBT of the conventional example is applied.
In this embodiment, the example in which the p ⁺ trench collector region 215, the first collector electrode 219, and the n trench buffer 216 are provided on the chip only at both ends has been described in accordance with FIG. The same effect can be obtained with a different structure.

As described above, according to the present embodiment, it is possible to realize a reverse conducting IGBT having low on-resistance and high mechanical strength and not only low loss during overload operation but also much lower loss in the steady operation region. . Furthermore, the manufacturing process can be greatly simplified as compared with the first embodiment.

Example 3
This example is a heterostructure 3C-SiC reverse conducting IGBT semiconductor element with a withstand voltage of 1.2 kV class, a rated output current of 20 A, and an absolute maximum rated current of 50 A class, the chip size is 8.8 mm × 2.4 mm, and the active region Is about 8 mm × 2 mm.

FIG. 3 is a cross-sectional view schematically showing a heterostructure 3C-SiC reverse conducting IGBT semiconductor device according to Example 3. The shape and structure of the cell are almost the same as in Example 2. Compared to the semiconductor element of the second embodiment, the n ⁺ drain 302 and the p buried collector conductive layer 321 and the first short-circuit region 320 are formed using a Si single crystal substrate having a thickness of 280 μm, and 3C is formed thereon. -The point which forms the SiC reverse conduction IGBT semiconductor element differs greatly.

  This embodiment has the following features compared to the other embodiments. First, the Si single crystal substrate is cheaper than the SiC substrate, and it is easy to increase the diameter and is excellent in economy. Further, the crystal is of high quality, and even with a high impurity concentration, there are few crystal defects and a low resistivity can be easily realized. In addition, 3C-SiC has an extremely small difference in crystal lattice spacing from Si compared to 4H-SiC, and an epitaxial growth layer with good crystal quality can be easily formed on a Si substrate, making it easy to manufacture high-performance semiconductor elements. It is.

As a result, when the impurity concentration of the p buried collector conductive layer 320 formed in the Si substrate is about 1 × 10 ²¹ cm ⁻³ , the resistivity can be greatly reduced to 0.0005 Ωcm or less, and the resistance of the IGBT is reduced. It can be lost. In addition, an epitaxial growth layer with good crystal quality can be easily formed on a Si substrate, and 3C-SiC has a high electron mobility of 900 cm ² / V seconds or more, and a high-performance MOSFET almost equivalent to 4H-SiC can be easily obtained. realizable

Next, a manufacturing flow of the 3C-SiC reverse conducting IGBT semiconductor element will be described. First, a p buried collector conductive layer 321 is selectively formed on a Si single crystal substrate having a crystal plane (100) constituting the n ⁺ drain 302. At this time, the first short-circuit region 320 is automatically formed. A 3C—SiC p-buried collector layer 303 is heteroepitaxially grown thereon, and a second n ⁺ short-circuit region 304 penetrating this layer is formed by ion implantation. Next, an n buffer layer 305 and an n drift layer 306 are sequentially formed by epitaxial growth. Further, by ion implantation, a p body region 307 is selectively formed in the n drift layer 306, and then two n ⁺ emitter regions 308 and two p ⁻ low-concentration channel regions 309 are further formed in the p body region 307. A p ⁺ contact region 310 is selectively formed. Thereafter, a gate insulating film 311 is formed, and a gate electrode 312 and an interlayer insulating film 313 made of polycrystalline Si are provided through the gate insulating film 311, and then an emitter electrode 314, a first collector electrode 319, and a second collector electrode 301 on the back surface are formed. Form. Thereafter, dicing is performed to complete the reverse conducting IGBT element 300.

Next, characteristics and features of the SiC reverse conducting IGBT according to the third embodiment will be described. The reverse conducting IGBT 300 was mounted on a TO type high voltage package as in Example 2 and subjected to an operation test. Of course, the first collector electrode 101 and the second collector electrode 119 are electrically connected.
When a forward voltage is applied between the emitter electrode 314 and the collector electrode without applying a gate voltage, a leakage current flows, but a good forward blocking characteristic is exhibited, and a withstand voltage at room temperature, that is, an avalanche breakdown is around 1.17 kV. It is. Moreover, the leakage current before avalanche breakdown is as good as 2.5 × 10 ⁻³ A / cm ² or less at room temperature and 3.8 × 10 ⁻² A / cm ² or less even at a high temperature of 250 ° C.

Further, when a gate voltage of about 20 V, which is equal to or higher than the threshold voltage, is applied to the gate electrode 312 and then a forward voltage is applied between the collector electrode and the emitter electrode 314, the current flowing in the MOSFET section increases almost linearly. As in Example 2, it was possible to pass a predetermined steady-state operating current of about 20 A with a forward voltage of 2.1 V, achieve an extremely low on-resistance of about 105 mΩ, and achieve a remarkable low loss. In this way, despite the withstand voltage of 1.2 kV or higher and the remarkably low on-voltage, the thickness of the reverse conducting IGBT chip is about 300 μm, and the high mechanical strength that the SiC wafer of the base material can sufficiently withstand the processing strain at the time of manufacture. Have. This is an effect obtained by making the low on-resistance and high mechanical strength compatible by separating the electric characteristic realization region and the mechanical strength realization region specific to the present invention.
When the forward voltage is further increased, a snap phenomenon appears and the IGBT portion is turned on. However, when the forward voltage is further increased, 50 A corresponding to 250% overload current can be caused to flow at an on-voltage of about 3.0 V. Low loss during load operation was achieved. The overload factor N of 2.5 is a sufficiently high value as compared with the conventional case.
The time until the snapback phenomenon appears and the IGBT part is turned on is approximately 75 nanoseconds, dIsb / dt is about 89 A / μs, and dVsb / dt is about −5.3 V / μs. Therefore, the influence on the circuit operation is negligible in practical use, and the adverse effect of the snapback phenomenon can be greatly suppressed. This is an effect of the buried end collector structure peculiar to the present invention, and can be realized with a smaller area as compared with the case where only the conventional pilot IGBT is applied.
In addition, the effect of combining the Si substrate and 3C—SiC with the structure of the present invention is greatly contributed to the achievement of the low resistance and suppression of the snapback phenomenon. In other words, the Si substrate has better crystallinity than the current SiC substrate and is excellent in conductivity at the same impurity concentration, so it is suitable for the p buried collector conductive layer, and its resistivity is greatly reduced to 0.0005 Ωcm or less. is made of.

As described above, according to the present embodiment, it has a high mechanical strength, a low on-resistance, a low loss at the time of overload operation, and a significantly lower loss in a steady operation region. Thus, the snapback phenomenon and its deterioration over time can be suppressed.

(Example 4)
Although the configuration and structure of the semiconductor element according to Example 4 are not shown, the Si reverse voltage with a design withstand voltage of 600 V, a rated output current of 40 A, an absolute maximum rated current of 100 A class, and an overload ratio N of 2 is Si reverse. It is a conducting IGBT. Compared to the SiC reverse conducting IGBT of Example 2 above, it is made of Si semiconductor material, the impurity concentration and thickness of the semiconductor layer and semiconductor region are set based on the physical property value of Si, the chip size is Except for a large point of 12.8 mm × 12.4 mm, the element has almost the same configuration as that of the second embodiment.
This embodiment has the following characteristics because all of the electrical property realization region and the mechanical strength realization region are made of Si semiconductors as compared to the other embodiments. That is, the Si single crystal substrate and the Si semiconductor element manufacturing process are cheaper than SiC, and can be easily increased in diameter and are excellent in economy. Furthermore, the crystal quality is higher than that of SiC, and even when the impurity concentration is high, there are few crystal defects and low resistivity can be easily realized. Therefore, the resistivity of the p buried collector conductive layer is greatly reduced to 0.0005 Ωcm or less. Since it can be reduced, the resistance of the reverse conducting IGBT can be reduced and the built-in voltage is about 0.8 V, which is 1/4 of SiC, so that a significant reduction in loss can be achieved.

The drift layer has an impurity concentration of 3 × 10 ¹⁴ cm ⁻³ , a thickness of about 60 μm, and a p buried end collector width of about 200 μm.
The Si-IGBT according to this example had a breakdown voltage at room temperature, that is, a voltage indicating an avalanche breakdown was about 640V. Further, when a gate voltage of about 20 V, which is equal to or higher than the threshold voltage, is applied to the gate electrode and then a forward voltage is applied between the collector electrode and the emitter electrode, the current flowing through the MOSFET portion increases almost linearly. About 40 A of the rated output current required for predetermined steady operation could be passed at .5V. The on-resistance is about 63 mΩ, and the characteristic on-resistance is 91 mΩcm ² . This low characteristic on-resistance is an appropriate low value considering the theoretical correlation between the breakdown voltage of the Si-MOSFET and the characteristic on-resistance. On the other hand, the thickness of the reverse conducting IGBT chip is about 300 μm, and it has a high mechanical strength that the base Si wafer can sufficiently withstand the processing strain at the time of manufacture. This is an effect obtained by separating the electrical property realization region and the mechanical strength realization region specific to the present invention to achieve both low on-resistance and high mechanical strength.

When the forward voltage is further increased, a snap phenomenon appears, the IGBT part turns on, and an on-current starts to flow, and an absolute maximum rated current of 40 A corresponding to an overload current of 250% is caused to flow at a low on-voltage of about 1.9V. And achieved low loss during overload operation.

In the present embodiment, an n trench buffer region is provided between the p ⁺ trench collector region and the n drift layer as in the second embodiment. As a result, in addition to the internal resistance of the n buffer layer on the p buried collector region, the internal resistance in the n trench buffer region having a length of about 60 μm perpendicular to the surface of the element can also be utilized, and the current can be relatively low. A voltage drop corresponding to a built-in voltage of Si of 0.7 V can be achieved and turned on, and Vsb in the snapback phenomenon can be suppressed to a low value. In the case of the structure in which the pilot IGBT is formed only on the p buried collector layer parallel to the surface of the element as in the conventional example 2, it cannot be reduced to Vsb equivalent to the present embodiment unless Wp is set to about 260 μm. In this embodiment, as described above, the equivalent Vsb is achieved with the width of the p buried end collector of about 200 μm, and the snapback phenomenon can be suppressed with a small area.
The time until the snapback phenomenon appears and the IGBT part is turned on is approximately 90 nanoseconds, dIsb / dt is approximately 657 A / μs, and dVsb / dt is approximately −12.5 V / μs. Compared to the value estimated from the structure of Conventional Example 2, the influence on the circuit operation is negligible in practice, and the adverse effect of the snapback phenomenon can be greatly suppressed. This is due to the effect of the buried end collector structure unique to the present invention and the effect that the buried end collector is made of Si having good crystallinity and the same impurity concentration and excellent conductivity.

As described above, according to the present embodiment, an economical Si semiconductor is used, it has a high on-resistance and high mechanical strength, and particularly has a low loss during an overload operation, and also has a smaller area and a snap back. Si reverse conducting IGBT that can suppress the phenomenon can be realized

(Example 5)
This example is the same as Example 1, withstand voltage 1.2 kV class, rated output current 45 A, absolute maximum rated current 135 A class element and overload ratio N 3 corresponding to high overload. is there. 4 embodiment is a cross-sectional view of such 4H-SiC reverse conducting IGBT semiconductor device shown schematically in 4, 3 and one-half of the cell and the p ⁺ trench collector region 415 of the left group cell of Example 1 in FIG. 1 Only half of them are shown and others are omitted and shown as broken line areas.
Compared with the semiconductor device of the first embodiment, the super junction structure is adopted in the n drift region and the super junction fabrication process is also used for forming the p ⁺ trench collector region 415, so that the impurity concentration is different. Except that the n trench buffer region is not provided, it is almost the same as the first embodiment.

As in the first embodiment, this embodiment has a low on-resistance and high mechanical strength, not only a low loss during overload operation, but also a super junction structure. The loss is particularly low in the steady operation region than in the examples. In addition, since the super junction structure manufacturing process is also used, the manufacturing process of the p ⁺ trench collector region 415 can be simplified.

Superjunction is disclosed in Japanese Patent Application Laid-Open Publication No. 2003-273355 and put into practical use, and the detailed description thereof is omitted, but the main points essential for understanding the present embodiment are described below. As shown in FIG. 4, instead of the n ⁻ drift layer 106 of the first embodiment, a structure formed from a p ⁻ column 423 and an n ⁻ column 424 formed by dividing the n ⁻ drift layer by the p ⁻ column. It has become. When the p ^- column 423 is formed in the corresponding portion of the n ^- drift layer, the n ^- column 424 therebetween is automatically formed. Therefore, in FIG. 4, the p ^- column 423 and the n ^- column 424 are provided alternately.

In the first embodiment, when a forward voltage is applied between the main terminals, the pn junction formed by the p body region 107 and the drift layer 106 is reverse-biased, the depletion layer expands in the drift layer, and the electric field is relaxed. The electric field is locally concentrated near the junction and becomes high. In the case of the super junction of this embodiment, when a forward voltage corresponding to the withstand voltage is applied, a depletion layer expands from a pn junction constituted by a low impurity concentration p ^- column 423 and a low impurity concentration n ^- column 424. Since all the columns are depleted, local concentration of the electric field can be prevented. As a result, the reciprocal relationship between the on-resistance and the breakdown voltage of the element can be improved, and the impurity concentration of the p ^- column 423 and the n ^- column 424 can be significantly increased as compared with the impurity concentration of the drift layer of the first embodiment even when the same breakdown voltage. The on-resistance can be greatly reduced.
For this purpose, the impurity concentration and the horizontal width (that is, the distance between columns of the same polarity) of the p ^- column 423 and the n ^- column 424 are set to values that are completely depleted when a forward voltage corresponding to the withstand voltage is applied. It is necessary to set. For example, the impurity concentration of both columns may be 7 × 10 ¹⁶ cm ⁻³ and the width may be 2.5 μm. The thickness of the column in the vertical direction may be 12 μm, which is the same as the thickness between the n buffer layer and the p body region in the first embodiment. The impurity concentrations and dimensions of the other layers are the same as those in the first embodiment except for the p ⁺ trench collector region 415.

Next, a manufacturing flow of the p ^- column 423 and the p ⁺ trench collector region 415, which is a feature of this embodiment, will be described with reference to FIGS. In FIG. 5, for convenience of description focusing on the main points, p body 507 (p ⁺ trench collector region 515 (415 in FIG. 4) and one p ^- column 523 (423 in FIG. 4) on each of the left and right sides thereof are provided. 4 is arranged and schematically shown, and a plurality of semiconductor layers are collectively shown as a semiconductor layer 550 as shown below.

Since the n ^- column 524 (424 in FIG. 4) forms the p ^- column 523 (423 in FIG. 4) as described in [0095], the n ^- drift layer is divided and formed automatically. 5 does not describe the n ^- column numbers and arrows.
First, the p ⁺ buried collector conductive layer 420 and the p buried collector layer 403 are formed on a high concentration n ⁺ substrate having a thickness of about 290 μm constituting the drain layer 402 in FIG. In order to prevent complication, these are collectively shown as a semiconductor layer 550 in FIG.
Next, an n buffer layer 505 (405 in FIG. 4) is formed by epitaxial growth on the front surface of the semiconductor layer 550, and then a p ⁺ trench collector region portion 515-0 connected to the p buried end collector region 417 is formed. It is selectively formed by ion implantation of aluminum.

Next, the n ⁻ semiconductor layer 525 constituting the drift layer is epitaxially grown, further a masking oxide film 526 is formed, and the oxide film on the p ⁺ trench collector region portion 515-0 is removed. Thereafter, when a resist film 527 is formed, the structure of FIG. 5a is obtained.

Next, in order to perform ion implantation for forming the p ⁺ trench collector region 515 (415 in FIG. 4) and the p ⁻ column 523 (423 in FIG. 4), the resist film 527 in the ion implantation portion is selectively removed. As a result, SiC is exposed in the corresponding portion of the p ⁺ trench collector region, but the oxide film is exposed in the corresponding portion of the p ⁻ column 523. Next, when Al ions are implanted with high implantation energy, the structure shown in FIG. 5B is obtained. That is, since the p ⁺ trench collector region corresponding portion 515-1 is exposed, a predetermined high concentration of Al is implanted, but the p ⁻ column corresponding portion 522-1 is masked with an oxide film and thus predetermined Only low concentration of Al is injected.

When the resist film is formed in this state and the above-described step [0099] is performed again, the p ⁺ trench collector region corresponding portion 515-2 and the p ⁻ column corresponding portion 523-2 are formed, and the structure shown in FIG. 5c is obtained. .
In this way, the above-described step [0099] is repeated a plurality of times to complete a p ^- column 523 having a predetermined design width and thickness as shown in FIG. 5d.

Next, an n ⁻ semiconductor layer 509 having the same impurity concentration as that of the n ⁻ semiconductor layer 525 is epitaxially grown, and the above-described step [0099] is performed again to perform the p body region 507 and the p ⁺ trench collector region corresponding portion 516 ( 415) of FIG. 4 is selectively formed. At this time, the thickness of the n ⁻ semiconductor layer 509 is set to be equal to or smaller than the thickness of the p body region 507 so that the p body region 507 (407 in FIG. 4) is surely in contact with the p ⁻ column 523 (423 in FIG. 4). There is a need.
Then, for the p-body region 507 ^{p +} contact region 510 and ^{p +} trench ^{p +} trench contact region 525 for the collector region 515 (425 in FIG. 4) is selectively formed ^{p +} trench collector region 515 (in FIG. 4 415) is completed. Further, an n emitter region 508 (408 in FIG. 4) is selectively formed to have a configuration of 5e. After that, the same manufacturing flow as in Example 1 is performed to complete the element shown in FIG.

The completed element chip was mounted in a package in the same manner as in Example 1 and used for element characteristic measurement. The breakdown voltage at room temperature, that is, the voltage indicating avalanche breakdown is about 1.34 kV. The leak current before avalanche breakdown is as good as 2.8 × 10 ⁻³ A / cm ² at room temperature.

When a gate voltage of about 20 V, which is equal to or higher than the threshold voltage, is applied to the gate electrode 412 and then a forward voltage is applied between the collector electrode and the emitter electrode 414 and the voltage is increased, the energization current of the MOSFET portion increases almost linearly. About 45 A of a predetermined steady-state operating current could be passed at a very low voltage of .4V. The characteristic on-resistance was about 9.96 mΩcm ² , which was extremely low, and a significant low loss could be achieved. When the forward voltage is further increased, a snapback phenomenon appears and the IGBT part is turned on, and 135 A corresponding to an overload current of 300% can be caused to flow at an on voltage of about 3.9 V, thereby achieving a low loss during an overload operation. did it. As for this overload factor N, 3 is remarkably high compared with the past.
On the other hand, the thickness of the reverse conducting IGBT chip is about 300 μm, and it has a high mechanical strength that the base SiC wafer can sufficiently withstand the processing strain at the time of device fabrication. This is an effect obtained by separating the electrical property realization region and the mechanical strength realization region specific to the present invention to achieve both low on-resistance and high mechanical strength.
The time until the snap-back phenomenon appears and the IGBT part is turned on is approximately 90 nanoseconds, dIsb / dt is approximately 92 A / μs, and dVsb / dt is approximately −2.7 V / μs. Therefore, the influence on the circuit operation is negligible in practical use, and the adverse effect due to the snapback phenomenon can be greatly suppressed. This is an effect of the buried end collector structure peculiar to the present invention, and can be realized with a smaller area as compared with the case where only the conventional pilot IGBT is applied.

As described above, according to this embodiment, it has low on-resistance and high mechanical strength, and has low loss during overload operation, and particularly in the steady operation region, it has significantly lower loss than other embodiments. . Further, since the trench collector region can be manufactured by the column manufacturing process, the manufacturing can be simplified.

(Example 6)
The present example is a 4H-SiC reverse conducting IGBT semiconductor element having substantially the same characteristics and specifications as those in Example 1, and is a 1.2 kV class, rated output current of 40 A, and absolute maximum rated current of 90 A class.
FIG. 6 is a cross-sectional view schematically illustrating a SiC reverse conducting IGBT semiconductor device according to the sixth example. Compared to the semiconductor element of the first embodiment, the p buried collector conductive layer is not provided, and the p buried collector layer 603 is thick and has a high impurity concentration. The p ⁺ trench collector region 615 and the n drift layer 606 The element structure and the element shape are substantially the same as those in the first embodiment except that an SiO ₂ oxide film 623 is provided near the front surface and an n-trench buffer region 616 is provided in the back.

Like the first embodiment, this embodiment has a low on-resistance and a high mechanical strength. It not only has a low loss during an overload operation, but also has a very low loss in a steady operation region. In order to significantly suppress the time-dependent increase in Vsb caused by surface stacking faults, it has been devised so as not to significantly impair the effect of suppressing the snapback phenomenon. Also, since no p ⁺ buried collector conductive layer is provided, the device fabrication process can be greatly simplified. Since the p ⁺ buried collector conductive layer is not provided, the loss during the overload operation is slightly increased, but a significantly low loss in the steady operation region can be maintained.

In this embodiment, the p buried collector layer 603 is thick and has a high impurity concentration. For example, the thickness may be about 6 μm and the impurity concentration may be 1 × 10 ²⁰ cm ⁻³ .
The manufacturing method may be based on the following flow. That is, an off-angle n ⁺ high impurity concentration SiC substrate having a thickness of about 290 μm is first used to form a p-layer having a thickness of about 1.0 μm on the front surface by epitaxial growth, and then covered with a resist film, and n ⁺ short circuit region An opening is formed in a portion to be a formation region 604, and further, an n ⁺ short-circuit region 104 is selectively formed by ion implantation of nitrogen with high concentration and high acceleration energy using the resist film as a mask. The above epitaxial growth film formation and selective ion implantation into the n ⁺ short-circuit region are repeated a plurality of times to form the p buried collector layer 603 and the n ⁺ short-circuit region 604 having a predetermined thickness.
After that, it is good to manufacture according to the process flow of Example 1 described after {0059}.

The reason why the increase in Vsb with time can be greatly suppressed without significantly impairing the effect of suppressing the snapback phenomenon will be described below. In this embodiment, the SiO ₂ oxide film 618 is provided only in a portion near the element front surface between the p ⁺ trench collector region 615 and the n drift layer 606, and n in the back portion away from the front surface. A trench buffer region 616 is provided. Therefore, when a forward voltage is applied between the collector electrode and the emitter electrode 614 in a state where a gate voltage equal to or higher than the threshold voltage is applied to the gate electrode 612, the n charge storage layer is interposed between the SiO ₂ oxide film 618 and the n drift layer 609. 620 is formed. As a result, the emitter electrode 614, the emitter region (functioning as a source region) 608, the channel region 609, the n storage layer 620, the n trench buffer region 616, and the p buried end collector as shown by the dotted line c as the energization route of the electron current. The route of the n buffer layer 605, the n short-circuit region 604, the n ⁺ drain layer 602, and the second collector electrode 601 on the region 617 can be secured.
Therefore, the voltage drop in the n trench buffer region 616 is added to the voltage drop in the n buffer layer 605 on the p buried end collector region 617, and unlike the first embodiment, the n trench buffer region 616 and the SiO ₂ oxide film 618 are added. The voltage drop in the n buffer layer becomes maximum in the vicinity of the contact portion. When the electric field drop in the vicinity becomes equal to or higher than the built-in voltage of 2.7 V, holes are injected from the p ⁺ trench collector region 615 in this portion, and the IGBT portion is turned on. Thus, since the IGBT portion is turned on not inside the element front surface but inside the element, an increase in Vsb with time due to stacking faults on the element front surface can be significantly suppressed.
In the description of the above reason, the group cell on the right side of the central p ⁺ trench collector region in FIG. 6 is used, but in reality, the p ⁺ trench collector region 615 of the group cell on the left side in FIG. Is longer than the p ⁺ trench collector region of the right group cell used in the description, and is turned on first from the left IGBT portion. In this way, even if the length of the p buried end collector region 617 at both ends of each group cell is changed, the effect of suppressing the snapback phenomenon is not significantly impaired. Since the SiO ₂ oxide film 618 is provided to suppress the increase in Vsb over time, the n buffer layer is shortened, but can be offset by increasing the length of the p ⁺ trench collector region 615, thereby suppressing the snapback phenomenon. The effect of suppressing the increase in Vsb with time can be enjoyed without much damage.

The characteristics of the SiC reverse conducting IGBT according to the sixth embodiment will be described below.
When a forward voltage is applied between the emitter electrode 614 and the collector electrode without applying a gate voltage, a leakage current flows, but a good forward blocking characteristic is exhibited, and a voltage indicating a withstand voltage at room temperature, that is, an avalanche breakdown is around 1.35 kV. It is. Moreover, the leakage current before avalanche breakdown is 1.5 × 10 ⁻³ A / cm ² or less at room temperature and 2.5 × 10 ⁻² A / cm ² or less even at a high temperature of 250 ° C. Compared to the first embodiment, the withstand voltage is slightly higher and the leakage current is smaller.

When a gate voltage of about 20 V that is equal to or higher than the threshold voltage is applied to the gate electrode 612 and then a forward voltage is applied between the collector electrode and the emitter electrode 614, the current flowing through the MOSFET increases almost linearly. As in Example 1, a predetermined steady-state operating current of about 40 A could be passed with a forward voltage as low as 2.2 V. Accordingly, the on-resistance is as extremely low as about 55 mΩ, and a remarkable low loss can be achieved. When the forward voltage is increased, a snap phenomenon appears and the IGBT part is turned on. When the forward voltage is further increased, 90 A corresponding to an overload current of 225% can be caused to flow at an on-voltage of about 4.1 V. A low loss of time was achieved. The overload factor N is 2.25, which is sufficiently high.
While the above-described extremely low on-resistance of about 55 mΩ is achieved, the thickness of the reverse conducting IGBT chip is about 300 μm, and the high mechanical strength that the SiC wafer of the base material can sufficiently withstand the processing strain during manufacture is achieved. Yes. This is an effect obtained by separating the electrical property realization region and the mechanical strength realization region specific to the present invention to achieve both low on-resistance and high mechanical strength.
In the snap phenomenon, dIsb / dt is about 100 A / μs, and dVsb / dt is about −4.6 V / μs. Therefore, the influence on the circuit operation is negligible in practical use, and the snap phenomenon can be further suppressed as compared with the second embodiment. This is an effect of the trench collector structure and the buried end collector structure peculiar to the present invention, and can be realized in a smaller area compared to the case where only the pilot IGBT of the conventional example is applied.

On the other hand, the effect of suppressing the increase in Vsb with time was examined. First, after conducting a test of repeating the snapback phenomenon 1000 times by alternately repeating the steady operation state of 40A and the overload operation state of 90A, the on-voltage during the overload operation of 90A, that is, the IGBT operation is measured by returning to room temperature. did. As a result, in Example 1, several percent of deteriorated elements whose on-voltage increased by 0.5 V or more were generated, and some elements increased by 15 V or more. However, in the case of the present embodiment, the deterioration element increasing by 0.5 V or more is only 1% or less, and the increase is only 0.9 V at the maximum.
In the present embodiment, similarly to the first embodiment, the drift region can be observed on the element front surface portion that is not covered by the emitter electrode 614, although only a part of the drift region can be observed. In general, stacking faults can be observed by energizing the element and observing electroluminescence. Therefore, as a result of observing the 1% deteriorated element of the above-mentioned Example, no increase in the area of stacking faults near the front surface was observed before and after the above repeated test. On the other hand, in the degraded elements of several percent of Example 1, an increase in the area of stacking faults near the front surface was observed in the majority.

In this embodiment, the SiO ₂ oxide film 618 is provided near the front surface between the p ⁺ trench collector region 615 and the n drift layer 606, and the n trench buffer region 616 is provided in the back thereof. ^An n trench buffer region 616 is provided between the trench collector region 615 and the n drift layer 606, and an SiO ₂ oxide film 618 is provided only near the front surface of the n drift layer 606 and the n trench buffer region 616. Can obtain the same effect.

As described above, according to the present embodiment, low on-resistance and high mechanical strength, not only low loss during overload operation but also extremely low loss in the steady operation region, and increase in Vsb over time. However, the reverse conducting IGBT in which the snapback phenomenon is further suppressed can be realized. Furthermore, the manufacturing process can be greatly simplified.

(Example 7)
This embodiment is a trench gate type 4H-SiC reverse conducting IGBT semiconductor element, which has a breakdown voltage of 900V class, a rated output current of 45A, an absolute maximum rated current of 180A class, and an overload factor N of 4. It is an element that can cope with.
FIG. 7 is a cross-sectional view schematically showing a SiC reverse conducting IGBT which is a semiconductor element according to Example 7.
Compared to the SiC reverse conducting IGBT of Example 6 above, the structure is almost the same as that of Example 6 except that the gate is a trench gate and the cell size is reduced due to the absence of the JFET portion. . Further, similarly to the sixth embodiment, the p buried collector layer 603 is thick and has a high impurity concentration.

Also in this embodiment, the roots of the electron current similar to the dotted line c in FIG. 1 are maintained in the cells at both ends of each cell group, and the emitter electrode 714 and the emitter region (functioning as the source region) 708 of the endmost cell. , Channel region 709, n storage layer around trench gate, field region, n storage layer 724, n trench buffer region 716, n buffer layer 705 on p buried end collector region 717, n short circuit region 704, n drain An electron current flows through the layer 702 and the second collector electrode 701. This electron current causes an electric field drop in the n buffer layer, and the electric field drop becomes maximum near the p ⁺ trench collector region 715 at the boundary between the SiO ₂ oxide film 723 and the n trench buffer region 716 farthest from the short-circuit region 704. When this electron current increases and the electric field drop exceeds the built-in voltage of 2.7 V, hole injection occurs near this boundary and the IGBT portion is turned on. Once the IGBT part is turned on, the resistance of this part is greatly reduced due to conductivity modulation, and a large bipolar current (the combined current of the hole current and the electron current) flows. This current spreads and the entire cell at the end is turned on and is large. Bipolar current flows. Further, in the adjacent cell, the voltage drop is increased due to the large spread current of the bipolar current, hole injection is generated from the p buried collector 703, and the adjacent cell is turned on. This repetition eventually turns on the entire group cell, eventually turns on the entire reverse conducting IGBT, and a large current corresponding to the overload current flows.

In this embodiment, since the on-current of the IGBT portion that is first turned on by the electron current route flows through the inside of the device because the SiO ₂ oxide film 723 is present inside, the stacking fault on the front surface of the device. It is possible to significantly suppress the increase in Vsb with time due to.
As a result of the trench gate, the cell width can be reduced to about half, the number of cells per unit area can be doubled, and a significant reduction in loss can be achieved. Furthermore, since no p ⁺ buried collector conductive layer is provided, the device fabrication process can be greatly simplified. Further, since the p ⁺ buried collector conductive layer is not provided, the loss during the overload operation is somewhat increased. However, the p buried collector 703 is thickened to, for example, 4.5 μm and has a high impurity of 1 × 10 ²⁰ cm ⁻³ . The concentration is compensated.

The characteristics of the SiC reverse conducting IGBT according to the present embodiment will be described below.
When a forward voltage is applied between the emitter electrode 714 and the collector electrode without applying a gate voltage, a leakage current flows, but a good forward blocking characteristic is exhibited. It is. Moreover, the leak current before avalanche breakdown is 3.8 × 10 ⁻³ A / cm ² or less at room temperature.

When a gate voltage of about 20 V, which is equal to or higher than the threshold voltage, is applied to the gate electrode 712 and then a forward voltage is applied between the collector electrode and the emitter electrode 714 and then increased, the conduction current of the MOSFET portion increases almost linearly. It was possible to pass a predetermined steady-state operating current of about 45 A at a significantly low forward voltage of .84V. The overload factor N is 4.0, which is much higher. The on-resistance was as extremely low as about 18.7 mΩ, and a significant reduction in loss during steady operation was achieved. This is the effect of making the trench gate structure and making the p buried collector 703 thick and high in impurity concentration.
When the forward voltage is further increased, a snap phenomenon appears and the IGBT section is turned on. When the forward voltage is further increased, 180 A corresponding to an overload current of 400% can flow at a low on-voltage of about 3.2 V. Low loss in load operation was also achieved. On the other hand, since the thickness of the reverse conducting IGBT chip is as thick as about 300 μm, it has a high mechanical strength that the base SiC wafer can sufficiently withstand the processing strain during manufacture. As described above, the structure unique to the present invention in which the electrical property realization region and the mechanical strength realization region are separated can achieve both low on-resistance and high mechanical strength.
In the snapback phenomenon, dIsb / dt is about +109 A / μs and dVsb / dt is about −1.9 V / μs, which can be greatly reduced compared to the conventional example, and the effect on circuit operation is practical. This level is negligible. As described above, the p ⁺ trench collector structure and the p buried end collector structure peculiar to the present invention can remarkably suppress the snapback phenomenon, and can be realized with a smaller area than when the conventional pilot IGBT is applied. ing.

Since the SiO ₂ oxide film 723 is made longer than that in the sixth embodiment, the n ⁺ trench buffer region 716 is shortened accordingly, so that the internal resistance is reduced and the Isb reduction effect is reduced, so that dIsb / dt is slightly increased. However, there is no problem in practical use. On the other hand, the inhibitory effect of the increase in Vsb with time showed an improvement trend and was good.

As described above, according to the present embodiment, it has a high mechanical strength, a low on-resistance, a low loss during an overload operation, and a remarkably low loss in a steady operation region. The area can suppress the snapback phenomenon and its deterioration over time.

(Example 8)
This embodiment is a 4H-SiC reverse conducting GTO thyristor, which is a device having a breakdown voltage of 2.4 kV class, a rated output current of 40 A, and an absolute maximum rated current of 90 A class.
FIG. 8 is a cross-sectional view schematically showing a SiC reverse conducting GTO thyristor according to an eighth embodiment. The chip size of the SiC reverse conducting GTO 800 is 8.8 mm × 4.5 mm, the active region is 8.0 mm × 4.1 mm, and the width of the breakdown voltage structure part surrounding the active region is 0. 2 mm and 0.4 mm at the top and bottom. The reverse conducting GTO cell in the active region is striped and the cell width is 36 microns. The thickness of the chip is approximately 300 μm.

As shown in FIG. 8, in the SiC reverse conducting GTO 600, the p ⁺ buried collector conductive layer 620 and the first buried collector conductive layer 620 are formed on the front surface of the n ⁺ collector layer 602 having a thickness of about 290 μm and the back surface contacting the second anode electrode 602. The short-circuit region 621 is provided, and the front surface thereof is provided with a p-buried collector layer 603 and a second n ⁺ short-circuit region 604 penetrating through this layer, facing each other. An n buffer layer 605 is provided on the front surface of the layer 603 and the region 604. The n buffer layer 105 is a SiC epitaxial layer. The impurity concentration and thickness of the p buried emitter region 853 may be, for example, 2.0 × 10 ¹⁸ cm ⁻³ and 2.5 μm, respectively. The impurity concentration and the thickness of the n ⁺ short-circuit portion 604 may be 1 × 10 ¹⁹ cm ⁻³ and 2.5 μm, respectively, for example. The impurity concentration and thickness of the n buffer layer 605 may be, for example, 8 × 10 ¹⁵ cm ⁻³ and 1.0 μm, respectively. The p buried emitter layer 603 in the cell may be provided near the center of the cell, and the width thereof may be 18 μm. The width of the n ⁺ short-circuit portion 604 may also be 18 μm.

An n drift layer 606 is provided on the front surface of the n buffer layer 605. The n drift layer 606 is a SiC epitaxial layer. The impurity concentration and thickness of the n drift layer 606 may be, for example, 5 × 10 ¹⁵ cm ⁻³ and 23 μm, respectively.

A p base region 607 is provided on the front surface of the n drift layer 606, and the impurity concentration and thickness may be, for example, 4 × 10 ¹⁷ cm ⁻³ and 2.0 μm, respectively. A plurality of n ⁺ emitter regions 608 are selectively provided on the front surface of each p base region 607, and the impurity concentration and thickness thereof are, for example, 5 × 10 ¹⁸ cm ⁻³ and 1.0 μm, respectively. The horizontal width may be, for example, 20 μm. An emitter electrode 609 is provided on the n ⁺ emitter region 608.

A gate electrode 610 is provided on the p base region 607 on both sides of the n ⁺ emitter region 608. Although not shown, an impurity concentration of 8 × 10 ¹⁸ cm ⁻³ is formed on the front surface of the p base region 607 immediately below the gate electrode 610 in order to form a good ohmic contact between the gate electrode 610 and the p base region 607. Contact regions are provided. The n ⁺ emitter region 608 and the p buried emitter layer 603 may be provided to oppose each other.

The cells are grouped in units as in the first embodiment, and ap ⁺ trench emitter region 615 is provided between each group. An insulating film 614 is provided between the n drift region 606 and the p ⁺ trench emitter region 615 near the front surface of the device to a depth of 8 μm, and the n trench buffer layer 616 extends from 8 μm to about 23 μm. Provided. A plurality of cells between horizontal centers of adjacent p ⁺ trench emitter regions 615 are defined as group cells, and the distance between the centers is hereinafter referred to as a group cell width. The p ⁺ trench emitter region 615 is provided so as to penetrate at least the n drift layer 606 and the n buffer layer 605 and to contact the p buried end emitter region 617 at the end of the group cell. The p buried emitter at the end extends from the n short circuit region 604 of the end cell to the horizontal center of the p ⁺ trench emitter region 615 and is hereinafter referred to as a p buried end emitter 617. Accordingly, the p buried end emitter 617 is wider than the p buried emitter layer 603 of the cells other than the end cells. The p ⁺ trench emitter region 615 is preferably as low a resistance as possible.
A first anode electrode 609 is provided on the exposed surface of the p ⁺ trench emitter region 615 on the main surface side. The first anode electrode 619 is electrically connected to the second anode electrode 601 externally.

The number of cells in each group may be ten, for example, and the width of the exposed surface of the p ⁺ trench emitter region 615 may be 30 μm. The width of the group cell may be 410 μm. FIG. 6 shows a part of two group cells. 3.5 cells out of 10 cells on the left side of the p ⁺ trench emitter region 615 and about 0.2 cells out of 10 cells on the right side. Each cell is described including the end of the group cell, that is, the field region.

The gate electrodes 610 of all cells in each group are connected to the gate electrodes 610 of adjacent cells at one end in the vertical direction of each stripe-like cell. Further, the cathode electrodes 609 of all the cells in each group are connected to the cathode electrodes 609 of the adjacent cells at the other end in the vertical direction of each stripe-like cell. The p buried emitter layer 603 of each cell is connected to the p buried emitter layer 603 of the adjacent cell, and the p buried emitter layers 603 of the cells on both ends of each group are adjacent to the p ⁺ trench emitter region. 615 is connected.

Hereinafter, the operation of this embodiment and the mechanism for suppressing the snapback phenomenon will be described.
First, when a gate current of about 1 A is applied and a forward current is applied and increased between the anode electrode and the cathode electrode 609, the route schematically shown by dotted lines a and b in FIG. The npn transistor current flows through a number of routes including, and the total current functions as a steady operation current.
At that time, in the cells at both ends of each cell group, the cathode electrode 609, the n emitter region 608, the p base region 607, the n storage layer 624, the n trench buffer layer 616, and the p buried end are routed by the route indicated by the dotted line c in FIG. Electron current also flows through the n buffer layer 605, the n short-circuit region 604, the n ⁺ layer collector 602, and the second anode electrode 601 on the partial emitter region 617. This electron current causes an electric field drop in the n buffer layer, but the electric field drop is maximized in the vicinity of the contact portion between the n trench buffer layer 616 and the insulating film 614 farthest from the short-circuit region 604.
When the applied voltage between the anode electrode and the cathode electrode is increased and this electric field drop becomes equal to or higher than the built-in voltage of 2.7 V, holes are injected from the p ⁺ trench emitter region 615 of this portion, and the GTO cell at the end portion Turn on. Once the GTO cell at the end is turned on, the resistance of this part is greatly reduced due to the conductivity modulation, and a large bipolar current (the sum of the hole current and the electron current) flows. This current spreads and the entire cell at the end In the adjacent cell, the voltage drop in the n buffer layer 605 on the p buried emitter layer 603 is increased by the large bipolar current in the adjacent cell, and the injection of holes from the p buried emitter layer 603 occurs. Is turned on, the entire group cell is turned on by repeating this, and finally the whole reverse GTO is turned on, and a large current corresponding to the overload current flows. The turn-on time required during this period is as short as about 200 nanoseconds.

When the p ⁺ trench emitter region 615 peculiar to the present embodiment is not provided, hole injection occurs from the central portion of the p buried emitter 603 due to the electric field drop in the half buffer layer portion on the p buried emitter layer 603. The GTO section turns on. Therefore, since the length of the buffer layer portion where the voltage drop occurs is as short as 9 μm, a very large electron current is required to cause the voltage drop of the built-in voltage 2.7 V, and Vsb becomes large. As a result, dIsb / dt and dVsb / dt resulting from the snapback phenomenon become large, which has a great adverse effect on the circuit.

On the other hand, when the p ⁺ trench emitter region 615 peculiar to the present embodiment is provided, the voltage drop in the n trench buffer region 616 in the route indicated by the dotted line c in FIG. 1 is added, so that the electron current can be suppressed accordingly. In the case of the present embodiment, the total length of the n buffer layer including the n trench buffer region 616 and the n buffer layer on the p buried end emitter 617 is about 56 μm, which is about 6 times longer. Since the electron current required to reach the voltage drop is much smaller, Vsb is significantly smaller. As a result, the snapback phenomenon can be greatly suppressed.
Further, the snapback phenomenon caused by stacking faults on the front surface of the drain layer 606 between the p base region 607 and the p ⁺ trench emitter region 615 is the same as the mechanism described in {0109} of Example 6. Changes over time can also be greatly suppressed.

Next, the characteristics and characteristics of the SiC reverse conducting GTO of this embodiment will be described.
When a forward voltage is applied between the anode electrode and the cathode electrode 609 without applying a gate current, a leakage current flows, but a good forward blocking characteristic is exhibited. It is. Moreover, the leak current before avalanche breakdown is as good as 1.1 × 10 ⁻³ A / cm ² or less at room temperature. These are the effects obtained by providing the SiO ₂ oxide film 614 between the p trench collector region 615 and the n drift layer 606.

Further, when a gate current of about 1 A is applied and then the forward voltage between the anode electrode and the cathode electrode 609 is increased, the current of the npn transistor portion increases almost linearly, and a predetermined voltage is set at a forward voltage of 2.4 V. The steady operating current of about 40 A was able to flow. Bipolar, therefore, the on-resistance is as low as about 60 mΩ, and a very low loss can be achieved. When the forward voltage is further increased, a snapback phenomenon appears and the GTO portion is turned on. When the forward voltage is further increased, 90 A corresponding to an overload current of 225% can be caused to flow at an on-voltage of about 3.9 V. Low loss during load operation was achieved. The overload factor N is 2.25, which is sufficiently higher than before.
In spite of the extremely low on-resistance of about 60 mΩ described above, the thickness of the reverse conducting GTO chip is about 300 μm. Therefore, the SiC wafer as a base material has a high mechanical strength enough to withstand the processing strain during manufacture. Yes. As described above, the structure unique to the present invention in which the electrical property realization region and the mechanical strength realization region are separated can achieve both low on-resistance and high mechanical strength.
The time until the snapback phenomenon appears and the GTO part is turned on is approximately 100 nanoseconds. However, dIsb / dt accompanying the snapback phenomenon is approximately +126 A / μs, and dVsb / dt is approximately −5.5 V / μs. The effect on operation is negligible in practice. As described above, the snap-back phenomenon can be remarkably suppressed by the trench collector structure and the buried end collector structure peculiar to the present invention, and moreover, it can be realized with a smaller area than when only the conventional pilot IGBT is applied.

In addition, after conducting a test in which the snapback phenomenon is repeated 1000 times by alternately repeating the steady operation state of 40A and the overload operation state of 90A, Vsb is returned to room temperature and the 90V overload operation, i.e., when the GTO is turned on. As a result of the measurement, several% of deteriorated elements whose ON voltage increased by 0.7 V or more were generated in Example 1, but in the case of the present Example, it is only 1% or less.

As described above, in the present embodiment, the first and second functional element sections have a low on-resistance and high mechanical strength in the SiC reverse conducting GTO in which only the bipolar operation is performed, and have an overload. Not only is low loss during operation, it is also extremely low loss in the steady operation region, and the increase in Vsb over time due to stacking faults on the front surface of the device is greatly reduced without particularly detracting from the effect of suppressing the snapback phenomenon. It can be suppressed and reliability can be improved.

Although the present invention has been described based on the first to eighth embodiments, the present invention is not limited to these, and it is obvious to those skilled in the art that various modifications can be easily made. For example, various shapes such as a mesh shape can be adopted in addition to the stripe shape that also refers to the cell shape. In addition, although a semiconductor device having a withstand voltage of 1.2 kV has been mentioned, the present invention can be applied to a device having a lower withstand voltage and an element having a higher withstand voltage. In the case of an element with a high withstand voltage, in addition to the channel stopper mentioned in the embodiment, various electric field relaxation techniques such as junction extension termination, field plate, RESURF, and field limiting ring, and super junction techniques can be applied. It is obvious to the contractor.
In addition to the values mentioned for the width of the cell, the width of the n short-circuited portion, and the width of the buried p-collector, it is a matter of course that various values can be adopted depending on various element specifications, for example, steady current specification values. Although the cell structure in which the n short-circuited portion is mainly provided below the p body near the center of the cell has been mentioned, it can be naturally applied to a cell structure or the like that is shifted from the center. Moreover, although mentioning the n-type reverse conducting SiC-IGBT, it is obvious that the same can be applied to p-type reverse conducting SiC-IGBTs having different polarities. Further, the reverse conducting SiC-IGBT having the planar gate structure has been described, but it is obvious that the present invention can be developed to a reverse conducting SiC-IGBT having another gate structure such as a trench gate structure or a V-groove type. Furthermore, the SiC reverse conducting IGBT and the SiC reverse conducting IGBT have been mentioned. However, the present invention can be applied to reverse conducting IGBTs using other wide gap semiconductors such as GaN and diamond. Although the reverse conducting IGBT is mentioned, the reverse conducting GTO, the reverse conducting electrostatic induction thyristor, the reverse conducting MOS thyristor, the reverse conducting GCT, the reverse conducting MCT (MOS control thyristor), and the reverse conducting, which are other bipolar reverse conducting semiconductor elements. It is obvious to those skilled in the art that it can be applied and expanded to an EST (emitter switch thyristor) and can be easily guessed.

The present invention can be used particularly effectively for inverters and various power converters with a power supply voltage of about 2 kV or less for home appliances, automobiles, solar power generation, wind power generation, and electric railway applications, and greatly reduces loss and increases overload capability. Can do. Naturally, it can also be used for inverters and various power converters for electric railway applications of 2 kV or higher, industrial applications, and power business applications.

101, 201, 301, 401, 601, 701: second collector electrodes 102, 202, 302, 402, 602: n drains 103, 203, 303, 403, 603, 703: p buried collector layers 104, 204, 304 404, 604, 704, 804: 2nd n ⁺ short-circuit region 105, 205, 305, 405, 605, 705, 805: n buffer layer 106, 206, 306, 406, 606, 706, 806: n ⁻ drift layer 107 , 207, 307, 407, 607, 707: p body regions 108, 208, 308, 408, 608, 708: n ⁺ emitter regions 109, 209, 309, 409, 609: p ^- channel regions 110, 210, 310 410, 610, 710: p ⁺ contact regions 111, 211, 311; 411, 611, 711: Gate oxide films 112, 212, 312, 412, 612, 712: Gate electrodes 113, 213, 313, 413, 613, 713: Interlayer insulating films 114, 214, 314, 414, 614, 714: Emitter electrodes 115, 215, 315, 415, 615, 715: p ⁺ trench collector regions 116, 216, 316, 416, 616, 716, 816: n trench buffer regions 117, 217, 317, 417, 617, 717: p Buried end collectors 119, 219, 319, 419, 619: first collector electrodes 120, 220, 320, 420, 620: p buried collector conductive layers 121, 221, 321, 421, 621, 821: first n ⁺ Short-circuit region 122, 222, 322, 422: n-channel stopper 23: p columns, 424: n Column, 425: ^{p +} trench contact regions 623,723: SiO ₂ oxide film of the insulating film, 624,724: n charge accumulating layer 701: second anode electrode, 702: ^{n +} collector 703: p buried emitter region, 707: p base region, 719: first anode electrode, 720: p buried emitter conductive layer 801: second anode electrode 802: n collector layer, 803, p buried anode layer 804 : P buried anode conductive layer, 807: p base region, 808: n emitter region 809: cathode electrode, 810: gate electrode, 811: surface protective oxide film 815: p trench anode region, 817: p buried end emitter 823: oxide film 819: first emitter electrode, 820: p buried emitter conductive layer, 824: n storage layer

Claims (5)

A first conductivity type first semiconductor layer (drain layer) and a second conductivity type second semiconductor layer (p-buried) provided on the front surfaces of the first conductivity type first semiconductor layer (drain layer) And a plurality of first conductivity type second semiconductor regions (second short circuit regions) penetrating the second conductivity type second semiconductor layer (p buried collector layer), and further comprising the second conductivity type. The first conductive type third semiconductor layer (n buffer) is formed on the front surfaces of the second semiconductor layer (p buried collector layer) of the type and the second semiconductor region (second short circuit region) of the first conductive type. A first conductive type second semiconductor layer (drift layer) on the front surface of the first conductive type third semiconductor layer (n buffer layer),
A part of the second conductive type second semiconductor layer (p buried collector layer) has a first conductive type second semiconductor layer (drift layer) and the first conductive type second semiconductor layer on the front surface. A third semiconductor region (p trench collector) of the second conductivity type penetrating through the three semiconductor layers (n buffer layer) and a fourth semiconductor region of the first conductivity type (n trench buffer region) of the first conductivity type The fourth semiconductor region (n trench buffer region) is in contact with the first conductivity type second semiconductor layer (n drift layer) and the second conductivity type third semiconductor region (p trench collector), respectively. Provided,
Further, a plurality of second conductive type first semiconductor regions (p body regions) are selectively provided on the front surface of the first conductive type second semiconductor layer (drift layer), and the second conductive type second semiconductor layer (drift layer) is selectively provided. A first conductivity type third semiconductor region (emitter region) is selectively provided on the front surface of each of the conductivity type first semiconductor regions (p body regions),
Each first conductivity type third semiconductor region (emitter region) and each first conductivity type second semiconductor layer (drift layer) of each second conductivity type first semiconductor region (p body region). A control electrode is provided on the surface of the portion sandwiched between the two via an insulating film,
Further, a third main electrode (emitter electrode) is provided in contact with each of the second conductivity type first semiconductor region (p body region) and the first conductivity type third semiconductor region (emitter layer). ,
A second main electrode (collector electrode) is provided in contact with the back surface of the first conductivity type first semiconductor layer (drain layer), and is formed on the surface of the second conductivity type third semiconductor region (p trench collector). A bipolar reverse conducting semiconductor element provided with a first main electrode in contact therewith, wherein the second main electrode (collector electrode) and the first main electrode are electrically connected;
A bipolar reverse conducting semiconductor element in which each semiconductor layer and each semiconductor region are formed of a wide gap semiconductor. A first conductivity type first semiconductor layer (drain layer) and a second conductivity type second semiconductor layer (p-buried) provided on the front surfaces of the first conductivity type first semiconductor layer (drain layer) And a plurality of first conductivity type second semiconductor regions (second short circuit regions) penetrating the second conductivity type second semiconductor layer (p buried collector layer), and further comprising the second conductivity type. The first conductive type third semiconductor layer (n buffer) is formed on the front surfaces of the second semiconductor layer (p buried collector layer) of the type and the second semiconductor region (second short circuit region) of the first conductive type. A first conductive type second semiconductor layer (drift layer) on the front surface of the first conductive type third semiconductor layer (n buffer layer),
A part of the second conductive type second semiconductor layer (p buried collector layer) has a first conductive type second semiconductor layer (drift layer) and the first conductive type second semiconductor layer on the front surface. A third semiconductor region (p trench collector) of the second conductivity type penetrating through the three semiconductor layers (n buffer layer) and a fourth semiconductor region of the first conductivity type (n trench buffer region) of the first conductivity type The fourth semiconductor region (n trench buffer region) is in contact with the first conductivity type second semiconductor layer (n drift layer) and the second conductivity type third semiconductor region (p trench collector), respectively. Provided,
In addition, a plurality of second conductivity type first semiconductor regions (p body regions) and a plurality of trench gates are alternately selected on the front surface of the first conductivity type second semiconductor layer (drift layer). The first conductive type third semiconductor region (emitter region) is in contact with the trench gate at the front surface of each of the second conductive type first semiconductor regions (p body regions). Is provided selectively,
The trench gate has an insulating film extending on a side surface of the trench and a control electrode in contact with the insulating film, and the first conductive type third semiconductor region (emitter region) and the first conductive type second semiconductor layer. The control electrode is provided on the end surface of the second conductivity type first semiconductor region (p body region) sandwiched between (drift layer) via the insulating film,
Furthermore, a third main electrode (emitter electrode) is provided in contact with the second conductive type first semiconductor region (p body region) and the first conductive type third semiconductor region (emitter layer),
A second main electrode (collector electrode) is provided in contact with the back surface of the first conductivity type first semiconductor layer (drain layer), and is formed on the surface of the second conductivity type third semiconductor region (p trench collector). A bipolar reverse conducting semiconductor element provided with a first main electrode in contact therewith, wherein the second main electrode (collector electrode) and the first main electrode are electrically connected;
A bipolar reverse conducting semiconductor element in which each semiconductor layer and each semiconductor region are formed of a wide gap semiconductor. In the bipolar reverse conducting semiconductor device according to any one of claims 1-2,
First conductive type fourth semiconductor region provided between the first conductive type second semiconductor layer (drift layer) and the second conductive type third semiconductor region (p-trench collector). On top of (n trench buffer region)
A bipolar reverse conducting semiconductor in which a second insulating film is provided in contact with the first conductive type second semiconductor layer (drift layer) and the second conductive type third semiconductor region (p trench collector region) element. In the bipolar reverse conducting semiconductor element according to any one of claims 1-3,
A bipolar reverse conducting semiconductor element, wherein the first conductive type first semiconductor layer (drain layer) is formed of a Si semiconductor. In the bipolar reverse conducting semiconductor element according to any one of claims 1-4,
The first conductive type first semiconductor layer (drain layer), the second conductive type second semiconductor layer (p buried collector layer), and the second conductive type second semiconductor layer (p buried collector layer). ) Between the plurality of first conductive type second semiconductor regions (second short circuit regions) penetrating
A plurality of first conductivity type first semiconductor regions penetrating the second conductivity type first semiconductor layer (p buried collector conductive layer) and the second conductivity type first semiconductor layer (p buried collector conductive layer). (First short-circuit region)
The second conductivity type first semiconductor layer (p buried collector conductive layer) is the second conductivity type second semiconductor layer (p buried collector layer) and the first conductivity type first semiconductor region ( The first short-circuit region is a bipolar reverse conducting semiconductor element that has substantially the same planar shape as the second semiconductor region of the first conductivity type (second short-circuit region), and is provided facing each other.

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