CN111261710A - Insulated gate bipolar transistor and preparation method thereof - Google Patents
Insulated gate bipolar transistor and preparation method thereof Download PDFInfo
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- CN111261710A CN111261710A CN201811466031.0A CN201811466031A CN111261710A CN 111261710 A CN111261710 A CN 111261710A CN 201811466031 A CN201811466031 A CN 201811466031A CN 111261710 A CN111261710 A CN 111261710A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 127
- 239000002184 metal Substances 0.000 claims abstract description 57
- 238000004519 manufacturing process Methods 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 24
- 238000005530 etching Methods 0.000 claims description 15
- 238000000059 patterning Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 239000011248 coating agent Substances 0.000 description 7
- 238000000576 coating method Methods 0.000 description 7
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 230000005684 electric field Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
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- 238000009826 distribution Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
Abstract
The invention relates to the technical field of power semiconductor chips and discloses an insulated gate bipolar transistor and a preparation method thereof. In the transistor, when the transistor is electrified, electrons sequentially pass through the emitter bonding metal layer, the device layer, the collector layer and the collector bonding metal layer to realize current conduction, so that a passing path of the current does not pass through the substrate, the transistor can adopt a thicker substrate to bear the ultrathin device layer, an ultrathin thinning process and related complex steps are not needed, and the manufacturing cost and the manufacturing difficulty are reduced.
Description
Technical Field
The invention relates to the technical field of power semiconductor chips, in particular to an insulated gate bipolar transistor and a preparation method thereof.
Background
An Insulated gate bipolar transistor FS-IGBT (Field Stop Insulated gate bipolar transistor) with an electric Field cut-off structure is the most advanced IGBT device in the prior art, and the electric Field distribution of the device is cut off (Field Stop) by adding an N-type semiconductor layer structure, so that the thickness of an N-type voltage-resisting layer is reduced, and the conduction voltage drop and the power loss of the device are reduced. The performance of the IGBT is greatly improved compared with other PT-IGBT and NPT-IGBT structures, and the IGBT is gradually the mainstream design of the IGBT field; the structure of an FS-IGBT in the prior art is shown in fig. 1, and includes an emitter bonding metal layer 05, a dielectric layer 04, a device layer 03, a collector layer 02, and a collector bonding metal layer 06.
However, in terms of manufacturing technology, in order to achieve such a characteristic of field cut-off, the thickness of the substrate layer must be ground to be very thin, which causes great difficulty in manufacturing the entire FS-IGBT chip.
Disclosure of Invention
When the insulated gate bipolar transistor is electrified, current passes through the device layer and then is input into the collector bonding metal layer through the collector layer, so that the conduction of the current is realized, the current is prevented from passing through the substrate, the substrate does not need to be ground, and the manufacturing cost and the manufacturing difficulty are reduced.
In order to achieve the purpose, the invention provides the following technical scheme:
a transistor comprises a substrate, wherein a collector layer is arranged on the substrate, a device layer is arranged on one side, deviating from the substrate, of the collector layer, the projection area of the device layer on the substrate is smaller than that of the collector layer on the substrate, the projection of the device layer on the substrate comprises at least two opposite side edges, a set distance is reserved between the edge of the projection of the collector layer on the substrate, a dielectric layer is coated on the outer surface of the device layer, an emitter bonding metal layer is formed on one side, deviating from the device layer, of the dielectric layer, and a collector bonding metal layer is arranged in a region, deviating from the substrate, of the collector layer.
In the transistor, a collector layer and a device layer are sequentially arranged on a substrate, the projection area of the device layer on the substrate is smaller than that of the collector layer on the substrate, at least two opposite side edges of the projection of the device layer on the substrate have a set distance with the edge of the projection of the collector on the substrate, so that part of the surface of one side of the collector, which is far away from the substrate, is exposed, and a collector bonding metal layer is arranged on the exposed surface of the collector so as to electrically connect the collector bonding metal layer with the collector; the dielectric layer is coated on the outer surface of the device layer, so that the device layer is insulated, when current passes through the device layer, the current can flow out towards the collector in a directional manner, that is, when the transistor is energized, current is input into the device layer through the metal layer, is input into the collector layer through the device layer, is input into the collector bonding metal layer through the collector layer, and is output through the collector bonding metal layer, therefore, the current conducting path does not pass through the substrate, so that a thicker monocrystalline silicon substrate can be adopted to bear the ultrathin device layer in the preparation process of the transistor, the ultrathin device layer is prevented from being damaged in the preparation and packaging processes, the reliability of the transistor is improved, an ultrathin thinning process and related complex steps are not required, the preparation process of the transistor is simplified, and the manufacturing cost and the manufacturing difficulty are reduced.
Preferably, the device layer comprises a field stop layer and a device voltage-withstanding layer which are sequentially arranged on the side, away from the substrate, of the collector layer.
Preferably, a component region is formed on one side of the component voltage-withstanding layer, which is far away from the substrate.
Preferably, the set distance is greater than zero.
Preferably, the set distance ranges from less than or equal to 400 micrometers.
Preferably, the thickness range of the side wall of the dielectric layer formed along the direction vertical to the substrate is greater than or equal to 1 micron.
The invention also provides a preparation method of the transistor, which comprises the following steps:
preparing a collector layer on a substrate;
preparing an epitaxial layer on the side of the collector layer, which faces away from the substrate;
etching the epitaxial layer to form a device layer, wherein the projection area of the device layer on the substrate is smaller than the projection area of the collector layer on the substrate to expose the collector layer, and the projection of the device layer on the substrate comprises at least two opposite side edges and a set distance from the edge of the projection of the collector layer on the substrate;
preparing a dielectric layer wrapping the device layer on the outer surface of the device layer;
patterning the dielectric layer;
preparing a metal layer wrapping the dielectric layer on the outer surface of the dielectric layer, wherein the projection area of the metal layer on the substrate is larger than that of the dielectric layer on the substrate;
and patterning the metal layer to form an emitter bonding metal layer on one side of the dielectric layer, which is far away from the device layer, and a collector bonding metal layer on one side of the collector layer, which is far away from the substrate.
Preferably, the preparing the epitaxial layer on the side of the collector layer facing away from the substrate includes:
preparing a field stop layer on the side of the collector layer, which faces away from the substrate;
and preparing a device voltage-withstanding layer on one side of the field stop layer, which is far away from the collector layer.
Preferably, before the etching the epitaxial layer to form a device layer, and a projection area of the device layer on the substrate is smaller than a projection area of the collector layer on the substrate to expose the collector layer, and a projection of the device layer on the substrate includes at least two opposite side edges and a set distance from an edge of the projection of the collector layer on the substrate, the method further includes:
and preparing a component layer on one side of the component voltage-resisting layer, which is far away from the substrate.
Preferably, the preparing the device layer on the side of the device voltage-withstanding layer away from the substrate includes:
and etching one side of the device pressure-resistant layer, which is far away from the field stop layer, to form a plurality of grooves, and filling materials for preparing components in the grooves to form a component layer, wherein the region of the device pressure-resistant layer, which corresponds to the component layer, is a component forming region.
Drawings
FIG. 1 is a schematic diagram of a prior art transistor;
FIG. 2 is a schematic cross-sectional view of a transistor according to the present invention;
FIG. 3 is a schematic structural diagram of a transistor provided in the present invention;
FIG. 4 is a schematic structural diagram of step 1 in the method for manufacturing a transistor according to the present invention;
FIG. 5 is a schematic structural diagram of step 2 in the method for manufacturing a transistor according to the present invention;
FIG. 6 is a schematic structural diagram of step 3 in the method for manufacturing a transistor according to the present invention;
FIG. 7 is a schematic structural diagram of step 4 in the method for manufacturing a transistor according to the present invention;
FIG. 8 is a schematic structural diagram of step 5 in the method for manufacturing a transistor according to the present invention;
fig. 9 is a schematic structural diagram of step 7 in the method for manufacturing a transistor according to the present invention;
fig. 10 is a schematic structural diagram of step 8 in the method for manufacturing a transistor according to the present invention;
fig. 11 is a schematic structural diagram of step 9 in the method for manufacturing a transistor according to the present invention;
fig. 12 is a schematic structural diagram of step 10 in the method for manufacturing a transistor according to the present invention.
Icon: 1-a substrate; 02. 2-a collector layer; 03. 3-a device layer; 31-a field stop layer; 32-device voltage-withstanding layer; 33-a component forming region; 04. 4-a dielectric layer; 05. 5-an emitter bonding metal layer; 06. 6-a collector bonding metal layer; 7-photoresist; 8-a metal layer; a-a first set distance; b-a second set distance.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 2 to 3, a transistor provided in an embodiment of the present invention includes a substrate 1, a collector layer 2 is disposed on the substrate 1, a device layer 3 is disposed on a side of the collector layer 2 away from the substrate 1, a projection area of the device layer 3 on the substrate 1 is smaller than a projection area of the collector layer 2 on the substrate 1, a projection of the device layer 3 on the substrate 1 includes at least two opposite side edges, a set distance is provided from an edge of the projection of the collector layer 2 on the substrate 1, an outer surface of the device layer 3 is covered with a dielectric layer 4, an emitter bonding metal layer 5 is formed on a side of the dielectric layer 4 away from the device layer 3, and a collector bonding metal layer 6 is disposed in a region of the side of the collector layer 2 away from the substrate 1 and outside the device layer 3.
In the transistor, a collector layer 2 and a device layer 3 are sequentially arranged on a substrate 1, the projection area of the device layer 3 on the substrate 1 is smaller than that of the collector layer 2 on the substrate 1, at least two opposite side edges of the projection of the device layer 3 on the substrate 1 have a set distance with the edge of the projection of the collector on the substrate 1, so that the partial surface of one side of the collector, which is far away from the substrate 1, is exposed, and a collector bonding metal layer 6 is arranged on the exposed surface of the collector, so that the collector bonding metal layer 6 is electrically connected with the collector; the dielectric layer 4 is coated and arranged on the outer surface of the device layer 3, so that the insulation treatment of the device layer 3 is realized, when current passes through the device layer 3, the current can flow out towards the direction of a collector electrode, namely when the transistor is electrified, electrons move into the device layer 3 through the emitter bonding metal layer 5 and move into the collector electrode layer 2 through the device layer 3, finally move into the collector bonding metal layer 6 from the collector electrode layer 2, the conduction of the current is realized through the collector bonding metal layer 6, the passing path of the current does not pass through the substrate 1, so that a thicker monocrystalline silicon substrate can be adopted to bear the ultrathin device layer in the preparation process of the transistor, the damage of the ultrathin device layer in the preparation and packaging processes is prevented, the reliability of the transistor is improved, an ultrathin thinning process and related complex steps are not required, and the preparation process of the transistor is simplified, the manufacturing cost and the manufacturing difficulty are reduced.
As an embodiment of the above-described set distance, the range of the set distance is 400 μm or less.
As shown in fig. 2, as an embodiment of the above-mentioned set distance, the projection of the device layer 3 on the substrate 1 includes two opposite side edges having a set distance with the edge of the projection of the collector layer 2 on the substrate 1, which are a first set distance a and a second set distance b, respectively, both of which are less than 400 micrometers, and at most one of the first set distance and the second set distance is 0; in this embodiment, the first set distance a is greater than the second set distance b.
Specifically, the device layer 3 includes a field stop layer 31 and a device withstand voltage layer 32 which are sequentially provided on the side of the collector layer 2 facing away from the substrate 1.
Specifically, a device region is formed on a side of the device withstand voltage layer 32 away from the substrate 1.
Specifically, the component region comprises a protection ring, a trench gate and a P-N junction.
Specifically, the dielectric layer 4 has a sidewall formed in a direction perpendicular to the substrate 1 in a thickness range of 1 μm or more.
As an embodiment of the above substrate 1, the substrate 1 is made of single crystal silicon.
As an embodiment of the collector layer 2, the collector layer 2 is formed by ion-implanting boron, which is a P-type impurity, into the collector layer 2 to form a P-type doped layer as the collector layer 2 in the present application.
As shown in fig. 4 to 12, an embodiment of the present invention further provides a method for manufacturing a transistor, including:
preparing a collector layer 2 on a substrate 1;
preparing an epitaxial layer on one side of the collector layer 2, which is far away from the substrate 1;
etching the epitaxial layer to form a device layer 3, wherein the projection area of the device layer 3 on the substrate 1 is smaller than the projection area of the collector layer 2 on the substrate 1 to expose the collector layer 2, and the projection of the device layer 3 on the substrate 1 comprises at least two opposite side edges and a set distance from the edge of the projection of the collector layer 2 on the substrate 1;
preparing a dielectric layer 4 for coating the device layer 3 on the outer surface of the device layer 3;
patterning the dielectric layer 4;
preparing a metal layer 8 for coating the dielectric layer 4 on the outer surface of the dielectric layer 4, wherein the projection area of the metal layer 8 on the substrate 1 is larger than that of the dielectric layer 4 on the substrate 1;
the metal layer 8 is patterned to form an emitter bonding metal layer 5 on the side of the dielectric layer 4 facing away from the device layer 3, a gate bonding metal layer, and a collector bonding metal layer 6 on the side of the collector layer 2 facing away from the substrate 1.
In the preparation method of the transistor, the collector layer 2 and the epitaxial layer are sequentially prepared on the substrate 1, the epitaxial layer is etched to form the device layer 3, so that the partial surface of one side of the collector, which is far away from the substrate 1, is exposed, the outer surface of the device layer 3 is coated and prepared with the dielectric layer 4, the device layer 3 is subjected to insulation treatment, then the metal layer 8 is prepared on the outer surface of the dielectric layer 4, and the metal layer 8 is etched to form the emitter bonding metal layer 5, the grid bonding metal layer and the collector bonding metal layer 6, in the preparation method, the emitter bonding metal layer 5, the grid bonding metal layer and the collector bonding metal layer 6 are simultaneously prepared by arranging the metal layer 8 and etching the metal layer 8, and the preparation method of the transistor is simplified, the preparation efficiency is improved.
Specifically, the epitaxial layer is formed on the side of the collector layer 2 facing away from the substrate 1, and includes:
preparing a field stop layer 31 on the side of the collector layer 2 facing away from the substrate 1;
a device withstand voltage layer 32 is prepared on the side of the field stop layer 31 facing away from the collector layer 2.
The field stop layer 31 and the device voltage-withstanding layer 32 are made by an epitaxial process.
Specifically, before etching the epitaxial layer to form the device layer 3, and a projection area of the device layer 3 on the substrate 1 is smaller than a projection area of the collector layer 2 on the substrate 1 to expose the collector layer 2, and a projection of the device layer 3 on the substrate 1 includes at least two opposite sides and a set distance from an edge of the projection of the collector layer 2 on the substrate 1, the method further includes:
the component layer 3 is prepared on the side of the component voltage-withstanding layer 32 away from the substrate 1.
Specifically, preparing the component layer 3 on the side of the component voltage withstand layer 32 away from the substrate 1 includes:
a plurality of grooves are formed on one side of the device voltage-resistant layer 32, which is far away from the field stop layer 31, by etching, and materials for preparing components are filled in the grooves to form a component layer 3, and a region of the device voltage-resistant layer 32, which corresponds to the component layer 3, is a component forming region 33.
Specifically, etching the epitaxial layer to form a device layer 3, wherein a projection area of the device layer 3 on the substrate 1 is smaller than a projection area of the collector layer 2 on the substrate 1 to expose the collector layer 2, and a projection of the device layer 3 on the substrate 1 includes at least two opposite sides having a set distance from an edge of the projection of the collector layer 2 on the substrate 1, including:
coating a photoresist 7 on a side of the component forming region 33 facing away from the substrate 1;
etching the region outside the photoresist 7 to leak the collector layer 2;
the photoresist 7 is stripped.
When the device layer 3 is etched, the device forming region 33 is prevented from being damaged in the etching process by coating the photoresist 7 on the device forming region 33.
Specifically, the dielectric layer 4 is prepared by a chemical vapor deposition process.
Specifically, the metal layer 8 is prepared by a magnetron sputtering process.
In this embodiment, the method for manufacturing a transistor specifically includes:
step 1: preparing a collector layer 2 on a substrate 1;
step 2: preparing an epitaxial layer on one side of the collector layer 2, which is far away from the substrate 1;
and step 3: etching the epitaxial layer to form a device layer 3, wherein the projection area of the device layer 3 on the substrate 1 is smaller than the projection area of the collector layer 2 on the substrate 1 to expose the collector layer 2, and the projection of the device layer 3 on the substrate 1 comprises at least two opposite side edges and a set distance from the edge of the projection of the collector layer 2 on the substrate 1;
and 4, step 4: coating a photoresist 7 on a side of the component forming region 33 facing away from the substrate 1;
and 5: etching the region outside the photoresist 7 to leak the collector layer 2;
step 6: the photoresist 7 is stripped.
And 7: preparing a dielectric layer 4 for coating the device layer 3 on the outer surface of the device layer 3;
and 8: patterning the dielectric layer 4;
and step 9: preparing a metal layer 8 for coating the dielectric layer 4 on the outer surface of the dielectric layer 4, wherein the projection area of the metal layer 8 on the substrate 1 is larger than that of the dielectric layer 4 on the substrate 1;
step 10: the metal layer 8 is patterned to form an emitter bonding metal layer 5 on the side of the dielectric layer 4 facing away from the device layer, a gate bonding metal layer, and a collector bonding metal layer 6 on the side of the collector layer 2 facing away from the substrate 1.
It will be apparent to those skilled in the art that various changes and modifications may be made in the embodiments of the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. The insulated gate bipolar transistor is characterized by comprising a substrate, wherein a collector layer is arranged on the substrate, a device layer is arranged on one side, away from the substrate, of the collector layer, the projection area of the device layer on the substrate is smaller than that of the collector layer on the substrate, the projection of the device layer on the substrate comprises at least two opposite side edges, a set distance is reserved between the edge of the projection of the collector layer on the substrate, a dielectric layer is coated on the outer surface of the device layer, an emitter bonding metal layer is formed on one side, away from the device layer, of the dielectric layer, and a collector bonding metal layer is arranged in a region, away from the device layer, of one side, away from the substrate, of the collector layer.
2. The insulated gate bipolar transistor of claim 1, wherein the device layer comprises a field stop layer and a device voltage-withstanding layer sequentially disposed on a side of the collector layer facing away from the substrate.
3. The IGBT of claim 2, wherein a device region is formed on a side of the device voltage withstand layer facing away from the substrate.
4. The igbt of claim 1, wherein the set distance is greater than zero.
5. The IGBT of claim 4, wherein the set distance is in a range of 400 microns or less.
6. The igbt of claim 1, wherein the dielectric layer has a sidewall thickness in a direction perpendicular to the substrate in a range of less than or equal to 1 μm.
7. A preparation method of an insulated gate bipolar transistor is characterized by comprising the following steps:
preparing a collector layer on a substrate;
preparing an epitaxial layer on the side of the collector layer, which faces away from the substrate;
etching the epitaxial layer to form a device layer, wherein the projection area of the device layer on the substrate is smaller than the projection area of the collector layer on the substrate to expose the collector layer, and the projection of the device layer on the substrate comprises at least two opposite side edges and a set distance from the edge of the projection of the collector layer on the substrate;
preparing a dielectric layer wrapping the device layer on the outer surface of the device layer;
patterning the dielectric layer;
preparing a metal layer wrapping the dielectric layer on the outer surface of the dielectric layer, wherein the projection area of the metal layer on the substrate is larger than that of the dielectric layer on the substrate;
and patterning the metal layer to form an emitter bonding metal layer on one side of the dielectric layer, which is far away from the device layer, and a collector bonding metal layer on one side of the collector layer, which is far away from the substrate.
8. The method for manufacturing the insulated gate bipolar transistor according to claim 7, wherein the manufacturing the epitaxial layer on the side of the collector layer, which is away from the substrate, comprises:
preparing a field stop layer on the side of the collector layer, which faces away from the substrate;
and preparing a device voltage-withstanding layer on one side of the field stop layer, which is far away from the collector layer.
9. The method according to claim 8, wherein before the etching the epitaxial layer to form the device layer and the area of the projection of the device layer on the substrate is smaller than the area of the projection of the collector layer on the substrate to expose the collector layer, and the projection of the device layer on the substrate includes at least two opposite sides having a set distance from the edge of the projection of the collector layer on the substrate, the method further comprises:
and preparing a component layer on one side of the component voltage-resisting layer, which is far away from the substrate.
10. The method for manufacturing the insulated gate bipolar transistor according to claim 9, wherein the manufacturing of the device layer on the side of the device voltage-withstanding layer away from the substrate comprises:
and etching one side of the device pressure-resistant layer, which is far away from the field stop layer, to form a plurality of grooves, and filling materials for preparing components in the grooves to form a component layer, wherein the region of the device pressure-resistant layer, which corresponds to the component layer, is a component forming region.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811466031.0A CN111261710A (en) | 2018-12-03 | 2018-12-03 | Insulated gate bipolar transistor and preparation method thereof |
| PCT/CN2019/109000 WO2020114054A1 (en) | 2018-12-03 | 2019-09-29 | Insulated gate bipolar transistor and fabrication method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811466031.0A CN111261710A (en) | 2018-12-03 | 2018-12-03 | Insulated gate bipolar transistor and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111261710A true CN111261710A (en) | 2020-06-09 |
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| JP4982948B2 (en) * | 2004-08-19 | 2012-07-25 | 富士電機株式会社 | Manufacturing method of semiconductor device |
| KR100906555B1 (en) * | 2007-08-30 | 2009-07-07 | 주식회사 동부하이텍 | Insulated gate bipolar transistor and Method for Manufacturing the same |
| CN104143568A (en) * | 2014-08-15 | 2014-11-12 | 无锡新洁能股份有限公司 | Field stop type IGBT device with terminal structure and manufacturing method thereof |
| JP6557925B2 (en) * | 2015-11-30 | 2019-08-14 | 良孝 菅原 | Semiconductor element |
| CN107845672A (en) * | 2017-10-24 | 2018-03-27 | 贵州芯长征科技有限公司 | IGBT device with Flouride-resistani acid phesphatase structure and preparation method thereof |
| CN209056500U (en) * | 2018-12-03 | 2019-07-02 | 珠海格力电器股份有限公司 | A kind of insulated gate bipolar transistor |
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