JP2901621B2 - Conduction modulation type MOS device - Google Patents
Conduction modulation type MOS deviceInfo
- Publication number
- JP2901621B2 JP2901621B2 JP63261486A JP26148688A JP2901621B2 JP 2901621 B2 JP2901621 B2 JP 2901621B2 JP 63261486 A JP63261486 A JP 63261486A JP 26148688 A JP26148688 A JP 26148688A JP 2901621 B2 JP2901621 B2 JP 2901621B2
- Authority
- JP
- Japan
- Prior art keywords
- drain
- modulation type
- anode
- mos device
- type mos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 26
- 210000000746 body region Anatomy 0.000 claims 3
- 239000000969 carrier Substances 0.000 description 10
- 238000009792 diffusion process Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 9
- 238000002347 injection Methods 0.000 description 9
- 239000007924 injection Substances 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000001514 detection method Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 230000006378 damage Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 102220182705 rs191061766 Human genes 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electronic Switches (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はハイサイド・スイツチ用ICに適した導電変調
型デバイスとその回路に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a conductive modulation type device suitable for a high-side switch IC and a circuit thereof.
従来、導電変調型MOSサイリスタに関してはアイ・イ
ー・デー・エム・コンフアレンス ダイジエスト（1985
年）第724頁から第727頁（IEDM Conf Digest（1985）p
p.724〜727）において論じられている。Conventionally, the conductivity modulation type MOS thyristor has been developed by IEM Conference Digest (1985
Year) pp. 724 to 727 (IEDM Conf Digest (1985) p.
pp. 724-727).
また、ハイサイド・スイツチ回路としてソースフオロ
ア接続させたｎチャネルMOSトランジスタを用い、ゲー
トを電源電圧よりも昇圧させる方法に関しては、例え
ば、米国特許第4420700号が挙げられる。A method of using an n-channel MOS transistor connected to a source follower as a high-side switch circuit and raising the gate voltage above the power supply voltage is described in, for example, US Pat. No. 4,420,700.
上記従来の導電変調型MOSサイリスタは誘電体分離型
の縦型DMOS構造を基にして作られたものであり、大電流
用に適した縦型DMOS構造を基にした構造については検討
がなされてなかつた。The conventional conductive modulation type MOS thyristor described above is based on a vertical DMOS structure of a dielectric isolation type, and a structure based on a vertical DMOS structure suitable for large current has been studied. Never
また、上記従来のハイサイド・スイツチ回路は、スイ
ツチ素子としてｎチャネルMOSトランジスタを用いてい
たが、他の素子を用いた場合については検討がなされて
いなかつた。Further, the above conventional high-side switch circuit uses an n-channel MOS transistor as a switch element, but no consideration has been given to the case where another element is used.
本発明の第１の目的は、大電流用に適した導電変調型
MOSデバイスを提供することにある。A first object of the present invention is to provide a conductive modulation type suitable for a large current.
To provide a MOS device.
本発明の第２の目的は、導電変調型MOSデバイスを用
い、オン抵抗の低減を図つたハイサイド・スイツチ回路
を提供することにある。A second object of the present invention is to provide a high-side switch circuit which uses a conductive modulation type MOS device and reduces on-resistance.
本発明の第３の目的は、導電変調型MOSデバイスを用
い、高速にオン状態からオフ状態に切り換え可能なハイ
サイド・スイツチ回路を提供することにある。A third object of the present invention is to provide a high-side switch circuit which can switch from an ON state to an OFF state at a high speed by using a conductive modulation type MOS device.
上記第１の目的を達成するために導電変調型デバイス
のセル部を従来の大電流縦型DMOSトランジスタや導電変
調型MOSトランジスタと同様のメツシユ型またはストラ
イプ形の構造とし、ドレイン領域に、アノードからの少
数のキヤリアが均一に注入されるように、アノード領域
をシリコン母体の中に埋込んで形成し、さらに、シリコ
ンの主面までアノード領域を延在させてアノード端子を
設けた。In order to achieve the first object, the cell portion of the conductive modulation type device has a mesh type or stripe structure similar to a conventional large current vertical DMOS transistor or a conductive modulation type MOS transistor. The anode region was formed by embedding it in a silicon matrix so that a small number of carriers were uniformly implanted, and the anode region was extended to the main surface of silicon to provide an anode terminal.
また、上記第２の目的を達成するためにｎチャネル導
電変調型MOSデバイスのソースに負荷を接続し、ドレイ
ンに電源を接続し、ゲート端子とアノード端子を電源よ
り昇圧させる手段を設けた。In order to achieve the second object, a load is connected to the source of the n-channel conductivity modulation type MOS device, a power supply is connected to the drain, and means for boosting the gate terminal and the anode terminal from the power supply are provided.
また、上記第２の目的を達成するためにｎチャネル導
電変調型MOSデバイスのソースに負荷を接続し、アノー
ドに電源を接続し、ゲート端子とカソード端子を電源よ
り昇圧させる手段を設けた。In order to achieve the second object, a load is connected to the source of the n-channel conductivity modulation type MOS device, a power source is connected to the anode, and means for boosting the gate terminal and the cathode terminal from the power source are provided.
シリコン母体中に埋込まれたアノードからは、ドレイ
ン中に均一に少数のキヤリアが注入されるため、ドレイ
ン領域を広く形成した大電流用導電変調型MOSデバイス
の場合でも、少数キヤリアの注入が局部的に多くなるこ
とによつて生ずる素子破壊を防止できる。Since a small number of carriers are implanted uniformly into the drain from the anode embedded in the silicon matrix, even in the case of a large-current conductive modulation MOS device with a wide drain region, the implantation of a small number of carriers is localized. It is possible to prevent element destruction caused by an increase in number.
また、ソースフオロア接続された導電変調型MOSデバ
イスにおいて入力端子を電源電圧より昇圧させて駆動さ
せる手段を設けたことにより、導電変調型MOSデバイス
のオン抵抗と電流駆動能力特性を最大限に発揮させた駆
動を行なえる。In addition, the on-resistance and current drive capability characteristics of the conductive modulation type MOS device are maximized by providing means for driving the input terminal of the conductive modulation type MOS device connected to the source follower by raising the input terminal from the power supply voltage. It can be driven.
以下、本発明の実施例を図面により詳細に説明する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
第１図は本発明の第１の実施例の半導体装置の断面図
である。本半導体装置の製造方法は以下のようになる。
まず、高濃度ｎ型シリコン基板１の所定の場所にｎ型埋
込層２とｐ型埋込層３を形成後、、Ｎ型エピタキシヤル
層７の成長を後なう。次に、高濃度ｐ型拡散層８と高濃
度ｎ型拡散層９を形成する。その後は従来のDMOSプロセ
スと同様にして、多結晶シリコン層12をマスクにしてｐ
型拡散層11とｎ型拡散層14を形成後ｐ型拡散層15を形成
する。FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention. The method for manufacturing the semiconductor device is as follows.
First, after the n-type buried layer 2 and the p-type buried layer 3 are formed at predetermined locations on the high-concentration n-type silicon substrate 1, the N-type epitaxial layer 7 is grown. Next, a high-concentration p-type diffusion layer 8 and a high-concentration n-type diffusion layer 9 are formed. After that, in the same manner as in the conventional DMOS process, p
After forming the n-type diffusion layer 11 and the n-type diffusion layer 14, the p-type diffusion layer 15 is formed.
ｎ型拡散層９は、導電変調型MOSデバイスのアノード
領域であるｐ型拡散層８から隣接素子へホールが注入さ
れることによつて生ずる隣接素子の誤動作を防止する。
また、アノード領域８から横方向に注入される少数キヤ
リアを抑え、アノードからドレインへの少数キヤリアの
注入がドレイン直下から均一に行なわれるようになつて
いる。The n-type diffusion layer 9 prevents malfunction of the adjacent element caused by injection of holes from the p-type diffusion layer 8 which is the anode region of the conduction modulation type MOS device to the adjacent element.
Further, a small number of carriers injected laterally from the anode region 8 are suppressed, so that the injection of the small number of carriers from the anode to the drain is uniformly performed from immediately below the drain.
本実施例では、基板の裏面からも電極18を用いてドレ
イン端子をとつているが、ウエルの表面からもドレイン
電極をとれる構造となつているため、ドレインの抵抗が
問題とならない場合は、裏面の電極18は不要である。こ
のことは、以下に述べる実施例でも同様である。In the present embodiment, the drain terminal is formed by using the electrode 18 also from the back surface of the substrate. However, since the structure is such that the drain electrode can be formed also from the surface of the well, if the drain resistance does not matter, the back surface is used. The electrode 18 is unnecessary. This is the same in the embodiments described below.
第２図は、本発明の第１の実施例の半導体装置の平面
図で、第１図のｎ型エピタキシヤル層７を成長する前の
状態を示したものである。本図のａ−ａで示した一点鎖
線部の断面図が第１図となる。アノードとなるｐ型埋込
層３はメツシュ状にドレイン領域全体に配列されてお
り、アノードからドレイン領域への注入が均一に行なわ
れるようになつている。このため、ドレイン領域が広い
大電流MOSトランジスタの場合にも、電流密度を均一化
できる。FIG. 2 is a plan view of the semiconductor device according to the first embodiment of the present invention, showing a state before the n-type epitaxial layer 7 of FIG. 1 is grown. FIG. 1 is a cross-sectional view taken along a dashed-dotted line indicated by aa in FIG. The p-type buried layer 3 serving as the anode is arranged in a mesh shape over the entire drain region, so that the injection from the anode to the drain region is performed uniformly. Therefore, even in the case of a large current MOS transistor having a wide drain region, the current density can be made uniform.
第３図は本発明の第２の実施例の半導体装置の断面図
である。FIG. 3 is a sectional view of a semiconductor device according to a second embodiment of the present invention.
本実施例では、第１図に示した導電変調型MOSデバイ
スが作られた同一チツプ上にロジツク用のCMOSを共存さ
せた場合の断面図である。導電変調型デバイスのドレイ
ンが、ロジツク用CMOSの電源と同一にできる場合には、
PMOSトランジスタに基板バイアスがかからない。In this embodiment, it is a sectional view in the case where logic CMOS is coexistent on the same chip on which the conductivity modulation type MOS device shown in FIG. 1 is formed. If the drain of the conduction modulation device can be the same as the power supply of the logic CMOS,
No substrate bias is applied to the PMOS transistor.
第４図は本発明の第３の実施例の半導体装置の断面図
である。本発明の半導体装置の場合には、高濃度ｎ型シ
リコン基板１の上にｎ型埋込層２を形成後ｐ型エピタキ
シヤル層４を成長させ、その後ｎ型埋込層５を形成す
る。その後の製造プロセスは、第１図の半導体装置と同
様になる。FIG. 4 is a sectional view of a semiconductor device according to a third embodiment of the present invention. In the case of the semiconductor device of the present invention, an n-type buried layer 2 is formed on a high-concentration n-type silicon substrate 1, and then a p-type epitaxial layer 4 is grown, and then an n-type buried layer 5 is formed. The subsequent manufacturing process is the same as that of the semiconductor device shown in FIG.
本実施例においてもｎ型埋込層2,5をドレイン領域内
に自由に配列できるため、ｐ型エピタキシヤル層４から
なるアノード領域からドレイン領域にホールを均一に注
入できる。また、本実施例の場合には、ｐ型エピタキシ
ヤル層４のアノード領域からドレイン領域への注入口を
ｎ型埋込層５により縮めることが可能である。このた
め、ドレイン直下にメツシユ状に配列したアノード領域
の幅は抵抗低減のため広くとり、ドレインへの少数キヤ
リヤ注入口は狭くすることが可能である。Also in this embodiment, since the n-type buried layers 2 and 5 can be freely arranged in the drain region, holes can be uniformly injected from the anode region composed of the p-type epitaxial layer 4 to the drain region. In the case of the present embodiment, the injection port from the anode region to the drain region of the p-type epitaxial layer 4 can be reduced by the n-type buried layer 5. For this reason, the width of the anode region arranged in a mesh shape immediately below the drain can be made wide to reduce the resistance, and the minority carrier injection port to the drain can be made narrow.
第５図は本発明の第４の実施例の半導体装置の断面図
である。本実施例では、ｎ型埋込層５の配列の密度を高
め、隣接するＮ型埋込層が弱接続されるようにしてい
る。これにより、アノードから、ドレインへの注入口の
濃度をｎ型エピタキシヤル領域７の濃度より高くし、ド
レイン領域への少数キヤリアの注入量を抑えることが可
能である。FIG. 5 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention. In this embodiment, the density of the arrangement of the n-type buried layers 5 is increased so that adjacent N-type buried layers are weakly connected. As a result, the concentration of the injection port from the anode to the drain can be made higher than the concentration of the n-type epitaxial region 7, and the injection amount of a small number of carriers into the drain region can be suppressed.
第６図は本発明の第５図の実施例の半導体装置の断面
図である。本実施例では、同一チツプ上にｐ型エピタキ
シヤル層４と高濃度ｐ型拡散層6,8により素子分離され
たMOSトランジスタを共存させている。FIG. 6 is a sectional view of the semiconductor device according to the embodiment of FIG. 5 of the present invention. In this embodiment, MOS transistors separated by p-type epitaxial layers 4 and high-concentration p-type diffusion layers 6 and 8 coexist on the same chip.
ｐ型エピタキシヤル層４の濃度は素子のアイソレーシ
ヨン耐圧（この図の場合には、右側のMOSトランジスタ
のドレインとGNDとの耐圧）に関係するため、高濃度化
できない。しかし、第４図と第５図に示した実施例で
は、このｐ型エピタキシヤル層が導電変調型MOSデバイ
スのアノード領域となつているため、導電変調型MOSデ
バイスにとうては低抵抗化することが望ましい。Since the concentration of the p-type epitaxial layer 4 is related to the isolation breakdown voltage of the element (in this case, the breakdown voltage between the drain of the right MOS transistor and GND), the concentration cannot be increased. However, in the embodiment shown in FIGS. 4 and 5, since the p-type epitaxial layer serves as the anode region of the conductive modulation type MOS device, the resistance is reduced for the conductive modulation type MOS device. It is desirable.
そこで、本実施例では、導電変調型MOSデバイス部に
はｐ型埋込層３と６を追加し、アノード領域の抵抗を下
げている。Therefore, in the present embodiment, the p-type buried layers 3 and 6 are added to the conduction modulation type MOS device to lower the resistance of the anode region.
第７図は本発明の第５の実施例の半導体装置の平面図
で、Ｎ型エピタキシヤル層７を成長する前の状態を示し
たものである。本図のｂ−ｂで示した一点鎖線部の断面
図が第６図となる。FIG. 7 is a plan view of a semiconductor device according to a fifth embodiment of the present invention, showing a state before an N-type epitaxial layer 7 is grown. FIG. 6 is a cross-sectional view taken along the dashed-dotted line indicated by bb in FIG.
第８図は本発明の第６の実施例の半導体回路のブロツ
ク図である。本願の図面では、Ｎチヤネル導電変調型MO
Sデバイスのシンボル図として、通常のＮチヤネルMOSト
ランジスタのシンボル図のドレインにダイオードを付け
円で囲つた図を用いた。FIG. 8 is a block diagram of a semiconductor circuit according to a sixth embodiment of the present invention. In the drawings of the present application, N-channel conductive modulation type MO
As a symbol diagram of the S device, a diagram in which a diode is attached to a drain in a symbol diagram of a normal N-channel MOS transistor and circled is used.
本実施例では、導電変調型MOSデバイスのドレインを
高電圧電源端子に接続し、ソースに負荷を接続させるソ
ースフオロア回路となつている。導電変調型デバイス
は、ゲート駆動回路とアノード駆動回路により制御す
る。アノード駆動回路は、例えばチヤージポンプ回路を
用いることにより、導電変調型MOSデバイスのドレイン
が接続されている電源電圧より昇圧させ、ドレイン内に
少数キヤリアを注入させることが可能である。このため
従来のMOSトランジスタをソースフオロア回路で用いる
場合に比べ、低オン抵抗化がはかれる。この時導電変調
型MOSデバイスのゲート駆動回路も、前記電源電圧より
昇圧させることにより、導電変調型MOSデバイス内に流
れる電流成分が主にMOSトランジスタ電流成分による場
合、さらに低オン抵抗化がはかれる。In the present embodiment, the drain of the conduction modulation type MOS device is connected to a high voltage power supply terminal, and a source follower circuit for connecting a load to a source is provided. The conductivity modulation type device is controlled by a gate drive circuit and an anode drive circuit. For example, by using a charge pump circuit, the anode drive circuit can raise the power supply voltage from the power supply voltage to which the drain of the conductive modulation type MOS device is connected, and inject a small number of carriers into the drain. For this reason, the on-resistance is reduced as compared with the case where a conventional MOS transistor is used in a source follower circuit. At this time, the gate drive circuit of the conduction modulation type MOS device is also stepped up from the power supply voltage to further reduce the on-resistance when the current component flowing in the conduction modulation type MOS device is mainly a MOS transistor current component.
なお、ゲート駆動回路とアノード駆動回路は、導電変
調型MOSデバイスに流れる電流や出力電圧等の情報に基
づき信号処理回路を通すことにより過電流，過電圧対策
を行なつた駆動を実現することが可能である。ゲート駆
動回路，アノード駆動回路，出力電流検出回路，出力電
圧検出回路，信号処理回路は、第６図に示した本発明の
構造を用いれば、素子分離された同一チツプ上の領域に
共存させることが可能である。In addition, the gate drive circuit and anode drive circuit can realize drive with overcurrent and overvoltage countermeasures by passing through a signal processing circuit based on information such as current and output voltage flowing through the conductive modulation type MOS device. It is. The gate drive circuit, the anode drive circuit, the output current detection circuit, the output voltage detection circuit, and the signal processing circuit can coexist in the element-isolated region on the same chip by using the structure of the present invention shown in FIG. Is possible.
なお本実施例と次の実施例での出力電流検出回路は、
導電変調型MOSデバイスのソースの一部を出力電流検出
回路に流す方式を用いた例を示してある。Note that the output current detection circuits in this embodiment and the next embodiment are:
An example is shown in which a method is used in which a part of the source of a conduction modulation type MOS device is supplied to an output current detection circuit.
第９図は本発明の第７の実施例の半導体回路のブロツ
ク図である。本実施例は、導電変調型MOSデバイスのア
ノードを高電圧電源に接続し、ソースに負荷を接続する
ソースフオロア回路となつている。本実施例の場合に
は、ゲート駆動回路とドレイン駆動回路により、導電変
調型MOSデバイスを制御している。本実施例の場合も、
出力電流検出回路と出力電圧検出回路と信号処理回路を
用いることにより、導電変調型MOSデバイスの過電流保
護等の保護対策が可能であり、これらの回路は、第６図
に示した構造により同一チツプに共存させることが可能
である。導電変調型MOSデバイスの電流が主にMOSトラン
ジスタ電流成分からなる時には、ゲート駆動回路を例え
ばチヤージポンプ回路を用いた昇圧回路により電源電圧
よりゲート端子を昇圧させることによりオン抵抗の低減
が図れる。また、ドレイン駆動回路にも昇圧回路を設け
ると、アノードからドレインへの少数キヤリアの注入阻
止能力を向上させることが可能である。このため、従来
の導電変調型MOSトランジスタに比べ高速に導電変調型M
OSデバイスをオフできるという利点がある。FIG. 9 is a block diagram of a semiconductor circuit according to a seventh embodiment of the present invention. In this embodiment, a source follower circuit in which the anode of a conduction modulation type MOS device is connected to a high voltage power supply and a source is connected to a load. In the case of the present embodiment, the conductivity modulation type MOS device is controlled by the gate drive circuit and the drain drive circuit. Also in the case of this embodiment,
By using an output current detection circuit, an output voltage detection circuit, and a signal processing circuit, protection measures such as overcurrent protection of a conduction modulation type MOS device are possible. These circuits have the same structure as shown in FIG. It is possible to coexist on the chip. When the current of the conduction modulation type MOS device mainly consists of a MOS transistor current component, the on-resistance can be reduced by boosting the gate terminal from the power supply voltage by a booster circuit using, for example, a charge pump circuit in the gate drive circuit. If a booster circuit is also provided in the drain drive circuit, the ability to prevent the injection of a small number of carriers from the anode to the drain can be improved. For this reason, the conductivity modulation type MOS transistor is faster than the conventional conduction modulation type MOS transistor.
There is an advantage that the OS device can be turned off.
第10図は本発明の第８の実施例の半導回路である。本
実施例は、第８図に示した回路ブロツクのアノード駆動
回路とゲート駆動回路の主要回路の実施例を示してい
る。FIG. 10 shows a semiconductor circuit according to an eighth embodiment of the present invention. This embodiment shows an embodiment of the main circuits of the anode drive circuit and the gate drive circuit of the circuit block shown in FIG.
導電変調型MOSデバイスＭのゲートは、逆位相のクロ
ツク入力電圧Vi1Gと と、ダイオードD5，D6，D7とキヤパシタC3，C4で構成さ
れる昇圧回路により、高電源電圧VDDHより高い電圧に設
定可能である。このため、MOS電流成分の寄与によるオ
ン抵抗成分を低減できる。The gate of the conductive modulation type MOS device M is connected to the clock input voltage V i1G of opposite phase. And a booster circuit composed of diodes D 5 , D 6 , D 7 and capacitors C 3 , C 4 , the voltage can be set higher than the high power supply voltage V DDH . Therefore, the on-resistance component due to the contribution of the MOS current component can be reduced.
また、導電変調型MOSデバイスのアノードは、アノー
ド駆動入力電圧Vi2Aを“H"に設定し、アノード駆動入力
電圧 を“L"に設定し、クロツク入力電圧Vi1Aと、ダイオード
D1，D2とキヤパシタC2で構成される昇圧回路により高電
源電圧VDDHより高い電圧に設定可能である。このため、
導電変調型MOSデバイスＭのアノードからドレインへ少
数キヤリアが注入され、導電変調型MOSデバイスのアノ
ードとドレインとボデイで構成されるバイポーラトラン
ジスタによる電流成分も追加されることによりオン抵抗
をさらに低減させることが可能である。Also, the anode of the conductive modulation type MOS device sets the anode drive input voltage Vi2A to “H” and sets the anode drive input voltage Is set to “L” and the clock input voltage Vi1A and the diode
A voltage higher than the high power supply voltage V DDH can be set by a booster circuit composed of D 1 and D 2 and a capacitor C 2 . For this reason,
To further reduce the on-resistance by injecting a small number of carriers from the anode to the drain of the conductive modulation type MOS device M and adding a current component by the bipolar transistor composed of the anode, the drain and the body of the conductive modulation type MOS device M Is possible.
ここで、ダイオードD3，D4は導電変調型MOSデバイス
のアノードが昇圧させる電圧を1.3V程度抑えるために設
けてあるが、アノード電圧の昇圧設定値によりダイオー
ドの数を増減してもよい。キヤパシタC1とダイオードD2
は、導電変調型MOSデバイスのアノード電圧の変動低減
のために追加した素子であり、設けなくても本発明の本
来の効果は得られる。導電変調型MOSデバイスをオフさ
せるためには、Vi2Aを“H", を“L"に設定し、さらに、Vi2Gを“H"に設定すれば良
い。また、この時クロツク入力電圧Vi1A，Vi1G， を止めると回路の消費電力を低減できる。Here, the diodes D 3 and D 4 are provided in order to suppress the voltage boosted by the anode of the conductive modulation type MOS device by about 1.3 V. However, the number of diodes may be increased or decreased according to the boost setting value of the anode voltage. Capacitor C 1 and diode D 2
Is an element added to reduce the fluctuation of the anode voltage of the conduction modulation type MOS device, and the original effect of the present invention can be obtained without providing the element. To turn off the conduction modulation type MOS device, set Vi2A to “H”, Is set to “L”, and Vi2G is set to “H”. At this time, the clock input voltages V i1A , V i1G , By stopping the operation, the power consumption of the circuit can be reduced.
第11図は本発明の第９の実施例の半導体回路である。
本実施例では、高電源電圧VDDH自体も低電源電圧VDDLか
ら昇圧させて実現するために、第10図の回路に、クロツ
ク入力電圧V1DDと、ダイオードD8，D9，D10とキヤパシ
タC5，C6から構成される昇圧回路を追加している。FIG. 11 shows a semiconductor circuit according to a ninth embodiment of the present invention.
In this embodiment, in order to realize the high power supply voltage V DDH itself by boosting it from the low power supply voltage V DDL , a clock input voltage V 1DD and diodes D 8 , D 9 and D 10 are added to the circuit of FIG. It is adding booster circuit composed of Kiyapashita C 5, C 6.
本実施例によれば、3Vまたは5V程度の単一低電圧源
で、高効率の高電圧ハイサイド・スイツチ回路を構成で
きる。なお、D11とD12はVDDHの昇圧量を制御するために
設けたツエナーダイオードである。According to this embodiment, a high-efficiency high-voltage high-side switch circuit can be constituted by a single low-voltage source of about 3 V or 5 V. Incidentally, D 11 and D 12 is a Zener diode which is provided for controlling the step-up amount of V DDH.
第12図は本発明の第10の実施例の半導体回路である。
本実施例は、第９図に示した回路ブロツクのドレイン駆
動回路とゲート駆動回路の主要回路の実施例を示してあ
る。導電変調型MOSデバイスのゲート駆動回路は、第10
図に示した昇圧型ゲート駆動回路が使える。また、ドレ
イン駆動回路は、第10図に示した昇圧型アノード駆動回
路が使えるが、ドレイン駆動回路に関しては本実施例で
示すような簡易型の昇圧回路が使える。すなわち、導電
変調型MOSデバイスをオンさせる時には、Vi2Dを“H"の
状態でVi1Dを“L"にし、導電変調型MOSデバイスのアノ
ード・ドレイン間が順バイアスされ、キヤパシタC7が充
電された後にVi1Dも“L"にする。導電変調型MOSデバイ
スのアノード・ドレイン間が順バイアスされるとアノー
ド・ドレイン・ボデイで構成されるバイポーラ動作によ
り、電流駆動能力が向上し、また、導電変調効果により
オン抵抗が低減する。導電変調型MOSデバイスをオフさ
せる場合には、Vi1Dを“H"の状態でVi2Dを“L"にする。
すると、キヤパシタC7に充電された電圧分だけ導電変調
型MOSデバイスのドレインが昇圧するように駆動される
ため、導電変調型MOSデバイスのアノード・ドレイン間
は高速に逆バイアスされ、高速にオフさせることが可能
となる。FIG. 12 shows a semiconductor circuit according to a tenth embodiment of the present invention.
This embodiment shows an embodiment of the main circuits of the drain drive circuit and the gate drive circuit of the circuit block shown in FIG. The gate drive circuit of the conduction modulation type MOS device
The boost gate drive circuit shown in the figure can be used. As the drain drive circuit, the booster anode drive circuit shown in FIG. 10 can be used, but as the drain drive circuit, a simple booster circuit as shown in this embodiment can be used. That is, when turning on the conductivity modulation type MOS device, the "L" level V i1d in the form of a V i2D "H", the anode-drain conductivity modulation type MOS device is forward biased, Kiyapashita C 7 is charged After that, Vi1D is also set to “L”. When a forward bias is applied between the anode and the drain of the conductive modulation type MOS device, the bipolar driving composed of the anode, the drain and the body improves the current driving capability, and the conductive modulation effect reduces the on-resistance. To turn off the conduction modulation type MOS device, Vi2D is set to "L" while Vi1D is set to "H".
Then, since the driven to the drain of the conductivity modulation type MOS device by the voltage charged in the Kiyapashita C 7 boosts, the anode-drain conductivity modulation type MOS device is reverse biased at high speed, is off at a high speed It becomes possible.
本発明によれば、ドレイン内への少数キヤリアの注入
を均一化することができるため大電流用の導電変調型MO
Sデバイスにおいてドレインに流れる電流が局部的に増
加することを防止できるという効果がある。また、本デ
バイスをソースフオロア型回路に用いた場合、従来のMO
Sトランジスタを用いた場合に比べ、オン抵抗の低減と
電流駆動能力向上とスイツチのオフ速度の向上がはかれ
るという効果がある。According to the present invention, since the injection of a small number of carriers into the drain can be made uniform, the conductive modulation type MO for a large current can be used.
In the S device, there is an effect that the current flowing to the drain can be prevented from locally increasing. When this device is used for a source follower type circuit, the conventional MO
As compared with the case where the S transistor is used, there is an effect that the ON resistance can be reduced, the current driving capability can be improved, and the OFF speed of the switch can be improved.
第１図は本発明の第１の実施例の半導体装置の断面図、
第２図は第１図の実施例のｎ型エピタキシヤル層形成前
の平面図、第３図は本発明の第２の実施例の半導体装置
の断面図、第４図は本発明の第３実施例の半導体装置の
断面図、第５図は本発明の第４の実施例の半導体装置の
断面図、第６図は本発明の第５の実施例の半導体装置の
断面図、第７図は第６図の実施例のｎ型エピタキシヤル
層形成前の平面図、第８図は本発明の第６の実施例の半
導体回路ブロツク図、第９図は本発明の第７の実施例の
半導体回路ブロツク図、第10図は本発明の第８の実施例
の半導体回路図、第11図は本発明の第９の実施例の半導
体回路図、第12図は本発明の第10の実施例の半導体回路
である。 １…ｎ型シリコン基板、2,5…ｎ型埋込層、3,6…ｐ型埋
込層、４…ｐ型エピタキシヤル層、７…ｎ型エピタキシ
ヤル層、8,10,11,13,15…ｐ型拡散層、9,14…ｎ型拡散
層、12…多結晶シリコン層、16…絶縁層、17,18…電極
層、Ｍ…ｎチヤネル導電変調型MOSデバイス、M1，M2，M
5，M7，M8，M9，M12，M14，M15…ｎチヤネルMOSトラン
ジスタ、M3，M4，M6，M10，M11，M13，M16，M17…ｐチ
ヤネルMOSトランジスタ、D1〜D12…ダイオード、C1〜C7
…キヤパシタ、VIN…入力電圧、VOUT…出力電圧、V11A
…導電変調型MOSトランジスタのアノード端子昇圧用入
力電圧、V12A…導電変調型MOSトランジスタのアノード
端子立下げ用入力電圧、 …導電変調型MOSデバイスのゲート端子昇圧用入力電
圧、Vi2G…導電変調型MOSデバイス立下げ用入力電圧、V
i1D…導電変調型MOSデバイスのドレイン昇圧用入力電
圧、Vi2D…導電変調型MOSデバイスのドレイン立下げ用
入力電圧、ViDD…高電源電圧昇圧用入力電圧、VDDH…高
電源電圧、VDDL…低電源電圧。FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention,
FIG. 2 is a plan view of the embodiment of FIG. 1 before the formation of the n-type epitaxial layer, FIG. 3 is a cross-sectional view of the semiconductor device of the second embodiment of the present invention, and FIG. FIG. 5 is a cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention; FIG. 6 is a cross-sectional view of a semiconductor device according to a fifth embodiment of the present invention; 6 is a plan view of the embodiment of FIG. 6 before the formation of the n-type epitaxial layer, FIG. 8 is a block diagram of a semiconductor circuit of the sixth embodiment of the present invention, and FIG. 9 is a block diagram of the seventh embodiment of the present invention. FIG. 10 is a semiconductor circuit diagram of an eighth embodiment of the present invention, FIG. 11 is a semiconductor circuit diagram of a ninth embodiment of the present invention, and FIG. 12 is a tenth embodiment of the present invention. It is an example semiconductor circuit. DESCRIPTION OF SYMBOLS 1 ... n-type silicon substrate, 2,5 ... n-type buried layer, 3,6 ... p-type buried layer, 4 ... p-type epitaxy layer, 7 ... n-type epitaxy layer, 8, 10, 11, 13 , 15 ... p-type diffusion layer, 9, 14 ... n-type diffusion layer, 12 ... polycrystalline silicon layer, 16 ... insulating layer, 17, 18 ... electrode layer, M ... n-channel conductivity modulation MOS device, M 1, M 2 , M
5, M 7, M 8, M 9, M 12, M 14, M 15 ... n -channel MOS transistor, M 3, M 4, M 6, M 10, M 11, M 13, M 16, M 17 ... p Channel MOS transistor, D 1 to D 12 … Diode, C 1 to C 7
… Capacitor, V IN … Input voltage, V OUT … Output voltage, V 11A
... Input voltage for boosting the anode terminal of the conductive modulation type MOS transistor, V12A ... Input voltage for falling the anode terminal of the conductive modulation type MOS transistor, … Input voltage for boosting the gate terminal of the conductive modulation type MOS device, V i2G … Input voltage for dropping the conductive modulation type MOS device, V
i1d ... conductivity modulation MOS device drain boosting the input voltage, V I2d ... conductivity modulation MOS device drain standing for lowering the input voltage, V IDD ... high power supply voltage step-up the input voltage, V DDH ... high power supply voltage, V DDL ... low power supply voltage.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 幸田 豊正 群馬県高崎市西横手町111番地 株式会 社日立製作所高崎工場内 (56)参考文献 特開 昭62−131580（ＪＰ，Ａ) 特開 昭63−95673（ＪＰ，Ａ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 29/78 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Toyomasa Koda 111, Nishiyokote-cho, Takasaki City, Gunma Prefecture Inside the Takasaki Plant of Hitachi, Ltd. (56) References JP-A-62-131580 (JP, A) JP-A Sho 63-95673 (JP, A) (58) Fields investigated (Int. Cl. 6 , DB name) H01L 29/78
Claims (1)
する第１導電型の半導体領域と、上記半導体領域内の第
１の主面近傍に形成された第２導電型のボデイ領域と、
上記ボデイ領域内に形成された第１導電型のソース領域
と、上記ボデイ領域のチャネル部となる表面にゲート絶
縁膜を介して形成されたゲート電極と、上記半導体領域
内に埋め込み形成されたメッシュ状の第２導電型のアノ
ード領域とを有し、上記第１の主面側に、前記アノード
領域の電圧と前記ドレイン領域の電圧をそれぞれ独立に
制御可能とするアノード端子とドレイン端子とがそれぞ
れ設けられていることを特徴とすることを特徴とする導
電変調型MOSデバイス。1. A semiconductor region of a first conductivity type having a first main surface and constituting a drain region, and a body region of a second conductivity type formed near a first main surface in the semiconductor region. ,
A first conductivity type source region formed in the body region, a gate electrode formed on a surface of the body region serving as a channel portion via a gate insulating film, and a mesh buried in the semiconductor region. And an anode terminal and a drain terminal that enable the voltage of the anode region and the voltage of the drain region to be independently controlled on the first main surface side, respectively. A conductive modulation type MOS device, characterized in that it is provided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63261486A JP2901621B2 (en) | 1988-10-19 | 1988-10-19 | Conduction modulation type MOS device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63261486A JP2901621B2 (en) | 1988-10-19 | 1988-10-19 | Conduction modulation type MOS device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02109371A JPH02109371A (en) | 1990-04-23 |
| JP2901621B2 true JP2901621B2 (en) | 1999-06-07 |
Family
ID=17362578
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63261486A Expired - Lifetime JP2901621B2 (en) | 1988-10-19 | 1988-10-19 | Conduction modulation type MOS device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2901621B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0683529B1 (en) * | 1994-05-19 | 2003-04-02 | Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno | Power integrated circuit ("PIC") structure with a vertical IGBT, and manufacturing process thereof |
| US5731603A (en) * | 1995-08-24 | 1998-03-24 | Kabushiki Kaisha Toshiba | Lateral IGBT |
| JP6557925B2 (en) * | 2015-11-30 | 2019-08-14 | 良孝 菅原 | Semiconductor element |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA1252225A (en) * | 1985-11-27 | 1989-04-04 | Sel Colak | Lateral insulated gate transistors with coupled anode and gate regions |
-
1988
- 1988-10-19 JP JP63261486A patent/JP2901621B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02109371A (en) | 1990-04-23 |
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