JPWO2012137290A1 - Bandwidth variable amplifier - Google Patents

Abstract

  A variable-band amplifier capable of amplifying the 10G and 1G received signals in the optimum equalization band while reducing the circuit scale and power consumption and keeping the circuit gain constant is obtained. A differential amplifier circuit constituted by a first transistor connected in series to a first resistive load and a second transistor connected in series to a second resistive load, and a positive phase of the differential amplifier circuit A first variable capacitance element having one end connected to the output point, a second variable capacitance element having one end connected to the reverse phase output point of the differential amplifier circuit, the other end of the first variable capacitance element, and A capacitance control terminal connected to the other end of the second variable capacitance element, and capacitance values of the first variable capacitance element and the second variable capacitance element according to a control voltage value applied to the capacitance control terminal. By changing, the band is controlled to a desired value without changing the gain output from the differential amplifier circuit.

Description

  The present invention relates to a variable bandwidth amplifier used in an optical communication system, and in particular, a subscriber termination unit (ONU: Optical Network Unit) of a PON (Passive Optical Network) system which is one method of an access optical communication system. The present invention relates to a band-variable amplifier used in the above.

  Conventionally, a point-to-multipoint access optical communication system called a PON system has been widely used as a system for realizing a public line network using optical fibers. FIG. 7 is a configuration diagram of the PON system. As shown in FIG. 7, the PON system includes a plurality of subscriber terminal apparatuses ONUs 70 (1) to 70 connected to one OLT (Optical Line Terminal) 50, which is a station side apparatus, and an optical star coupler 60. (N).

  Since the PON system having such a configuration can share most of the optical fiber as the transmission line and the OLT 50 with respect to a large number of ONUs 70 (1) to 70 (n), the operation cost can be expected to be economical. . Further, the optical star coupler 60, which is a passive component, has the advantages that it does not require power feeding, is easy to install outdoors, and has high reliability. For this reason, the PON system has been actively introduced in recent years as a trump card for realizing a broadband network.

  For example, in 10G-EPON (10 Gigabit-Ethernet Passive Optical Network) standardized by IEEE 802.3av and capable of communication at both transmission rates of 10 Gbit / s and 1.25 Gbit / s, Such communication is performed.

  In the downstream communication from the OLT 50 to each of the ONUs 70 (1) to 70 (n), a broadcast communication system using an optical wavelength of 1.58 μm band as a 10G signal and an optical wavelength of 1.49 μm band as a 1G signal is used. . Each of the ONUs 70 (1) to 70 (n) divides the transmission rate by a WDM (Wavelength Division Multiplexing) filter that performs wavelength division multiplexing, and extracts only the data addressed to the own station in the assigned time slot.

  On the other hand, in the upstream communication from each ONU 70 (1) to 70 (n) to the OLT 50, communication is performed using the optical wavelength 1.27um band as the 10G signal and the optical wavelength 1.31μm band as the 1G signal. . Then, a time division multiplex communication system for controlling transmission timing is used so that data of both the 10G signal and the 1G signal by the ONUs 70 (1) to 70 (n) do not collide.

  In the upstream communication of such a PON system, the optical receiver of the OLT 50 receives both 10G signal and 1G signal burst optical signals. In order to perform optimum noise equalization for each signal and improve the reception sensitivity characteristic, it is common to provide both 10G and 1G circuits in this optical receiving unit. A technique related to a burst receiving circuit has been proposed (see, for example, Non-Patent Document 1).

  On the other hand, as a configuration for changing the band by a single circuit, for example, a technique for changing the band of the differential amplifier by controlling Gm has been proposed (see, for example, Patent Document 1).

JP 2000-68761 A

COIN2010 TuC1-5 “1.25 / 10.3-Gbit / s Dual-rate Burst-Mode Receiver with Automatic Bit-rate Discrimination for Coexisting PON Systems”

However, the prior art has the following problems.
The technique disclosed in Non-Patent Document 1 requires separate amplifier circuits for 10G signals and 1G signals, and there is a problem that the circuit scale and power consumption increase.

  Further, the technique disclosed in Patent Document 1 has a problem that it is difficult to increase the bandwidth because the circuit gain varies and the active load because the bandwidth is varied by Gm control.

  These problems in the prior art will be described in detail with reference to the drawings. First, FIG. 8 is a diagram showing a configuration of a conventional amplifier circuit according to Non-Patent Document 1. In FIG. The amplifier circuit shown in FIG. 8 includes an input terminal 101, output terminals 102 and 103, and amplifiers 111 and 112.

  Next, the operation will be described. The input terminal 101 is input with respect to both the 10G signal and the 1G signal so that the data of the ONUs 70 (1) to 70 (n) do not collide. The amplifier 101 is an amplifier designed in the equalization band fc = 7.7 GHz, and equalizes and amplifies the 10G signal and outputs it to the output terminal 102. On the other hand, the amplifier 102 is an amplifier designed in the equalization band fc = 0.9 GHz, equalizes and amplifies the 1G signal, and outputs it to the output terminal 103.

  Since the amplifier circuit in Non-Patent Document 1 has such a configuration that requires two amplifiers, the circuit scale and power consumption are required twice as compared with the case where one band variable amplifier is used.

  Next, FIG. 9 is a diagram showing a configuration of a conventional amplifier circuit according to Patent Document 1. In FIG. The amplifier circuit shown in FIG. 9 includes five CMOS transistors 211 to 215, four current sources 241 to 244, and a capacitor 251.

  Further, as input / output terminals and power sources, positive and negative phase input terminals 201a and 201b, output terminals 202a and 202b of a differential amplifier circuit composed of CMOS transistors 211 and 212, and bias terminals of CMOS transistors 213 and 214 which are cascode transistors. 203, a Gm control terminal 204 of the differential amplifier circuit, a positive power source 205, and a negative power source 206.

Next, the operation will be described. The band fc in this circuit configuration is expressed by the following expression (1).
fc = 1 / (2πC (1 / gm)) (1)
In the above equation (1), C is the capacitance of the capacitor 251, and gm is a value determined by the Gm control terminal 204.

The gain A is expressed by the following equation (2).
A = -gm · RL (2)
In the above equation (2), RL is a load resistance, and gm is a value determined by the Gm control terminal 204.

  Therefore, by changing gm, the band fc can be changed by the relationship of the above equation (1), but there is a problem that the circuit gain A also changes by the relationship of the above equation (2). For this reason, the conventional amplifier circuit according to Patent Document 1 has a problem that cannot be applied to the receiving circuit.

  The present invention has been made in order to solve the above-described problems, and is suitable for 10G and 1G received signals while keeping the circuit gain constant while reducing circuit scale and power consumption. An object of the present invention is to obtain a variable bandwidth amplifier that can amplify in a band.

  A variable bandwidth amplifier according to the present invention includes a first transistor connected in series to a first resistive load and a second amplifier connected in series to a second resistive load. A first variable capacitance element having one end connected to the positive phase output point of the differential amplifier circuit, a second variable capacitance element having one end connected to the negative phase output point of the differential amplifier circuit, And a capacitance control terminal connected to the other end of the second variable capacitance element, and according to a control voltage value applied to the capacitance control terminal, the first variable capacitance element and By changing the capacitance value of the second variable capacitance element, the band is controlled to a desired value without changing the gain output from the differential amplifier circuit.

  The band variable amplifier according to the present invention has a configuration in which a variable capacitance element that can change a capacitance value according to the magnitude of an applied voltage is connected to an output point of a differential amplifier circuit, thereby reducing circuit scale and power consumption. It is possible to obtain a variable-band amplifier capable of amplifying the 10G and 1G received signals in the optimum equalization band while reducing the circuit gain and keeping the circuit gain constant.

It is a figure which shows the structure of the variable band amplifier concerning Embodiment 1 of this invention. It is a figure which shows the characteristic of the electrostatic capacitance versus reverse voltage of the varactor diode of the variable band amplifier concerning Embodiment 1 of this invention. It is a figure which shows the operation | movement image of the gain versus frequency characteristic of the band variable amplifier concerning Embodiment 1 of this invention. It is a figure which shows the structure of the band variable amplifier concerning Embodiment 2 of this invention. It is a figure which shows the structure of the band variable amplifier concerning Embodiment 3 of this invention. It is a figure which shows the structure of the band variable amplifier concerning Embodiment 4 of this invention. It is a block diagram of a PON system. It is a figure which shows the structure of the conventional amplifier circuit by a nonpatent literature 1. It is a figure which shows the structure of the conventional amplifier circuit by patent document 1. FIG.

  Embodiments of a variable bandwidth amplifier according to the present invention will be described below in detail with reference to the accompanying drawings. In addition, this invention is not limited by this embodiment.

Embodiment 1 FIG.
FIG. 1 is a diagram showing a configuration of a variable bandwidth amplifier according to the first exemplary embodiment of the present invention. The band-variable amplifier in FIG. 1 includes CMOS transistors 11 and 12, resistors 21 and 22, varactor diodes 31 and 32, and a current source 41. Further, as input / output terminals and power sources, the capacitances of the positive phase and negative phase input terminals 1a and 1b, the positive and negative phase output terminals 2a and 2b, and the varactor diodes 31 and 32 of the differential amplifier circuit composed of the CMOS transistors 11 and 12 are used. A control terminal 3, a positive power source 5, and a negative power source 6 are provided.

  Next, the operation and characteristics of the variable band amplifier according to the first embodiment will be described. FIG. 2 is a diagram showing the characteristics of capacitance versus reverse voltage of the varactor diodes 31 and 32 of the variable bandwidth amplifier according to the first exemplary embodiment of the present invention. As shown in FIG. 2, the varactor diodes 31 and 32, which are variable capacitance elements, have characteristics that the capacitance is large when the reverse voltage is small and the capacitance is small when the reverse voltage is large. doing.

  Therefore, the variable bandwidth amplifier according to the first embodiment takes advantage of the characteristics of FIG. 2 to control the terminal voltage of the capacity control terminal 3 shown in FIG. By changing, the band fc can be controlled.

  FIG. 3 is a diagram showing an operation image of the gain versus frequency characteristic of the variable bandwidth amplifier according to the first exemplary embodiment of the present invention. By changing the capacitance values of the varactor diodes 31 and 32 according to the voltage applied to the capacitance control terminal 3, it is possible to control to fc = 7.7 GHz when the control voltage is High and 0.9 GHz when the control voltage is Low. Further, when such control is performed, gm and RL related to the gain A shown in the above equation (2) do not change. For this reason, it is possible to change only the band to a desired value without gain change.

  As described above, according to the first embodiment, the variable capacitance element that can change the capacitance value to a desired value according to the magnitude of the applied voltage is connected to the output point of the differential amplifier circuit. The band can be controlled to a desired value without changing the gain by using the circuit configuration of one differential amplifier. As a result, it is possible to realize an excellent variable bandwidth amplifier that can reduce the circuit scale and power consumption and obtain an optimum equalization band for 10G and 1G received signals while keeping the circuit gain constant.

Embodiment 2. FIG.
FIG. 4 is a diagram showing a configuration of the variable bandwidth amplifier according to the second exemplary embodiment of the present invention. The band variable amplifier in FIG. 4 includes CMOS transistors 11 to 14, resistors 21 and 22, varactor diodes 31 and 32, and a current source 41. Further, as input / output terminals and a power source, the capacitances of the positive phase and negative phase input terminals 1a and 1b, the positive and negative phase output terminals 2a and 2b, and the varactor diodes 31 and 32 of the differential amplifier circuit composed of the CMOS transistors 11 and 12 are used. A control terminal 3, a bias setting terminal 4 for the CMOS transistors 13 and 14, a positive power source 5, and a negative power source 6 are provided.

  Compared with the configuration of FIG. 1 in the first embodiment, the configuration of FIG. 4 in the second embodiment is different in that CMOS transistors 13 and 14 and a bias setting terminal 4 are further provided. Therefore, these differences will be mainly described below.

  As shown in FIG. 4, the CMOS transistors 13 and 14 having the bias setting terminal 4 are cascade-connected to the CMOS transistors 11 and 12 constituting the differential amplifier circuit. By using such a multistage amplifier circuit, the amplification gain of the mirror capacitance of the differential amplifier circuit composed of the CMOS transistors 11 and 12 can be reduced, and the bandwidth of the entire variable bandwidth amplifier can be increased. Become.

  As described above, according to the second embodiment, by using the cascade-connected differential amplifier circuit, in addition to the effect of the first embodiment, the amplification gain of the mirror capacitance of the differential amplifier circuit is reduced. Therefore, the bandwidth of the entire variable bandwidth amplifier can be increased.

Embodiment 3 FIG.
FIG. 5 is a diagram showing a configuration of the variable bandwidth amplifier according to the third exemplary embodiment of the present invention. 5 includes CMOS transistors 11 to 14, resistors 21 to 24, varactor diodes 31 to 34, and a current source 41. Further, as input / output terminals and power sources, the capacitances of the positive phase and negative phase input terminals 1a and 1b, the positive and negative phase output terminals 2a and 2b, and the varactor diodes 31 to 34 of the differential amplifier circuit composed of the CMOS transistors 11 and 12 are used. A control terminal 3, a bias setting terminal 4 for the CMOS transistors 13 and 14, a positive power source 5, and a negative power source 6 are provided.

  Compared with the configuration of FIG. 4 in the previous second embodiment, the configuration of FIG. 5 in the third embodiment is different in that resistors 23 and 24 and varactor diodes 33 and 34 are further provided. Therefore, these differences will be mainly described below. The basic operation is the same as that of the second embodiment, and a description thereof is omitted.

  As shown in FIG. 5, the newly added varactor diodes 33 and 34 and the second low-pass filter including the resistors 23 and 24 are added to the first low-pass filter including the varactor diodes 31 and 32 and the resistors 21 and 22. Forming. With such a configuration, the order of the filter can be increased.

  As described above, according to the third embodiment, by providing a configuration that increases the order of the filter, in addition to the effects of the second embodiment, the degree of freedom in filter design can be increased.

Embodiment 4 FIG.
FIG. 6 is a diagram showing a configuration of the variable bandwidth amplifier according to the fourth exemplary embodiment of the present invention. The band variable amplifier in FIG. 6 includes CMOS transistors 11 to 14, resistors 21 to 24, varactor diodes 33 and 34, and a current source 41. Further, as input / output terminals and power sources, the capacitances of the positive phase and negative phase input terminals 1a and 1b, the positive and negative phase output terminals 2a and 2b, and the varactor diodes 33 and 34 of the differential amplifier circuit composed of the CMOS transistors 11 and 12 are used. A control terminal 3, a bias setting terminal 4 for the CMOS transistors 13 and 14, a positive power source 5, and a negative power source 6 are provided.

  Compared with the configuration of FIG. 5 in the previous third embodiment, the configuration of FIG. 6 in the fourth embodiment is different in that the varactor diodes 31 and 32 are not provided. Therefore, this difference will be mainly described below. The basic operation is the same as that of the second embodiment, and a description thereof is omitted.

  Varactor diodes 33 and 34 in the fourth embodiment function in the same manner as varactor diodes 31 and 32 in the first embodiment. As a result, the band variable amplifier according to the fourth embodiment can also control the band to a desired value without changing the gain.

  Further, the band variable amplifier according to the fourth embodiment does not have the varactor diodes 31 and 32. For this reason, since the capacitive component connected to the resistors 21 and 22 becomes smaller, it is possible to further widen the band compared to the third embodiment.

  As described above, according to the fourth embodiment, although there is no configuration for increasing the order of the filter, the effect of the second embodiment can be obtained by providing a configuration that can reduce the capacitance component connected to the resistance load. In addition, it is possible to increase the bandwidth of the entire variable bandwidth amplifier.

A variable bandwidth amplifier according to the present invention includes a first transistor connected in series to a first resistive load and a second amplifier connected in series to a second resistive load. A first variable capacitance element having one end connected to the positive phase output point of the differential amplifier circuit, a second variable capacitance element having one end connected to the negative phase output point of the differential amplifier circuit, And a capacitance control terminal connected to the other end of the second variable capacitance element, and according to a control voltage value applied to the capacitance control terminal, the first variable capacitance element and by changing the capacitance value of the second variable capacitance element, without changing the gain output from the differential amplifier circuit, it has a configuration for controlling the bandwidth to a desired value, the first transistor and the first A third transistor inserted in series with the resistive load of And a fourth transistor inserted in series between the second transistor and the second resistive load to constitute a cascode-connected differential amplifier, wherein the collector of the first transistor and the third transistor A third resistive load inserted in series with the emitter of the second transistor; a fourth resistive load inserted in series between the collector of the second transistor and the emitter of the fourth transistor; One end is connected to the connection point between the resistance load and the third transistor, the other end is connected to the capacitance control terminal, and the connection point between the fourth resistance load and the fourth transistor. And a fourth variable capacitance element having one end connected and the other end connected to the capacitance control terminal. The first variable capacitance element, the second variable capacitance element, and the second variable capacitance element are connected in accordance with a control voltage value applied to the capacitance control terminal. Variable capacitance element, third variable A first low-pass filter including a first variable capacitive element, a second variable capacitive element, a first resistive load, and a second resistive load, wherein capacitance values of the quantity element and the fourth variable capacitive element are changed. , A third variable capacitor, a fourth variable capacitor, a third resistance load, and a second low-pass filter including a fourth resistance load constitute a multistage filter .

Claims (6)

A differential amplifier circuit composed of a first transistor connected in series to a first resistive load and a second transistor connected in series to a second resistive load;
A first variable capacitance element having one end connected to a positive phase output point of the differential amplifier circuit;
A second variable capacitance element having one end connected to a negative phase output point of the differential amplifier circuit;
A capacitance control terminal connected to the other end of the first variable capacitance element and the other end of the second variable capacitance element;
By changing the capacitance values of the first variable capacitance element and the second variable capacitance element according to the control voltage value applied to the capacitance control terminal, the gain output from the differential amplifier circuit is increased. A variable bandwidth amplifier having a configuration in which a band is controlled to a desired value without being changed. The variable bandwidth amplifier according to claim 1, wherein
A third transistor inserted in series between the first transistor and the first resistive load;
And a fourth transistor inserted in series between the second transistor and the second resistive load, and a cascode-connected differential amplifier. The variable bandwidth amplifier according to claim 2,
A third resistive load inserted in series between the collector of the first transistor and the emitter of the third transistor;
A fourth resistive load inserted in series between the collector of the second transistor and the emitter of the fourth transistor;
A third variable capacitance element having one end connected to a connection point between the third resistance load and the third transistor and the other end connected to the capacitance control terminal;
A fourth variable capacitance element having one end connected to a connection point between the fourth resistance load and the fourth transistor and the other end connected to the capacitance control terminal;
Capacitance values of the first variable capacitance element, the second variable capacitance element, the third variable capacitance element, and the fourth variable capacitance element according to a control voltage value applied to the capacitance control terminal. The first variable capacitance element, the second variable capacitance element, the first resistance load, the first low-pass filter comprising the second resistance load, the third variable capacitance element, A band-variable amplifier that constitutes a multistage filter including the fourth variable capacitance element, the third resistance load, and a second low-pass filter including the fourth resistance load. The variable bandwidth amplifier according to claim 3,
A variable bandwidth amplifier having a configuration excluding the first variable capacitance element and the second variable capacitance element. The variable bandwidth amplifier according to any one of claims 1 to 4,
Each of the variable capacitance elements is a varactor diode. The variable bandwidth amplifier according to any one of claims 1 to 5, wherein each of the transistors is a bipolar transistor or a CMOS transistor.

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