CN112234945B - Distributed amplifier circuit, gain unit and electronic device - Google Patents
Distributed amplifier circuit, gain unit and electronic device Download PDFInfo
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- CN112234945B CN112234945B CN202011099268.7A CN202011099268A CN112234945B CN 112234945 B CN112234945 B CN 112234945B CN 202011099268 A CN202011099268 A CN 202011099268A CN 112234945 B CN112234945 B CN 112234945B
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- H—ELECTRICITY
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- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
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Abstract
The present disclosure provides a distributed amplifier circuit, a gain unit, and an electronic device. The distributed amplifier circuit includes: an input transmission line and an output transmission line, a first end of the output transmission line being connected to the variable resistor; the input end of each gain unit is connected to the input transmission line, and the output end of each gain unit is connected to the output transmission line; and at least one variable capacitor, one end of each variable capacitor is connected with the output end of the corresponding gain unit, the other end of each variable capacitor is grounded, wherein the resistance value of the variable resistor can be adjusted so that the adjusted resistance value of the variable resistor is matched with the resistance value of the load circuit, and the capacitance value of the variable capacitor can be adjusted so that the characteristic impedance of the output transmission line obtained by adjusting the capacitance value of the variable capacitor is matched with the resistance value of the load circuit.
Description
Technical Field
The present disclosure relates to the field of distributed amplifier technologies, and in particular, to a distributed amplifier circuit, a gain unit, and an electronic device.
Background
The basic principle of the distributed amplifier is that parasitic capacitances at the input and output ends of the transistors and equivalent capacitances and inductances on the input and output transmission lines are combined to form characteristic impedance of the input transmission line and the output transmission line. The root of the distributed amplifier being able to provide high bandwidth is that the characteristic impedance of the output transmission line can be matched to the resistance of the load circuit. When the resistance of the load circuit is determined, the input transmission line, the output transmission line and related devices of the traditional distributed amplifier are all solidified after processing, and cannot be adjusted. The phenomenon of one-to-one correspondence between the distributed amplifier circuit with the characteristic impedance of the transmission line and the specific load circuit is common, namely, the distributed amplifier is only developed by the load circuit corresponding to the specific load resistance value, and the distributed amplifier has no universality.
The structures described in this section are not necessarily structures that have been previously conceived or pursued. Unless otherwise indicated, it should not be assumed that any of the structures described in this section are prior art only as they were included in this section. Similarly, the problems mentioned in this section should not be considered as having been recognized in any prior art unless otherwise indicated.
Disclosure of Invention
It would be advantageous to provide a mechanism that alleviates, mitigates or even eliminates one or more of the above problems.
According to one aspect of the present disclosure, there is provided a distributed amplifier circuit comprising: the input transmission line, the first end of the input transmission line is used for receiving the signal to be amplified, and the second end of the input transmission line is used for receiving the first voltage; an output transmission line having a first end connected to the variable resistor for receiving the second voltage and a second end for outputting the amplified signal to the load circuit; the input end of each gain unit is connected to the input transmission line, and the output end of each gain unit is connected to the output transmission line; and at least one variable capacitor, one end of each variable capacitor is connected with the output end of the corresponding gain unit, the other end of each variable capacitor is grounded, wherein the resistance value of the variable resistor can be adjusted so that the adjusted resistance value of the variable resistor is matched with the resistance value of the load circuit, and the capacitance value of the variable capacitor can be adjusted so that the characteristic impedance of the output transmission line obtained by adjusting the capacitance value of the variable capacitor is matched with the resistance value of the load circuit.
According to another aspect of the present disclosure, there is provided a gain unit comprising: a first transistor and a second transistor; and a first resistor and a second resistor, wherein: the first end of the first transistor is connected to the current bias circuit, the second end of the first transistor is connected to the first end of the second transistor, and the third end of the first transistor is used as an input end of the gain unit; the second end of the second transistor is connected to the third end of the second transistor through the first resistor, the third end of the second transistor is connected to the bias voltage source through the second resistor, and the second end of the second transistor serves as an output end of the gain unit.
According to another aspect of the present disclosure, there is provided an electronic device including: a distributed amplifier as claimed in any preceding claim.
These and other aspects of the disclosure will be apparent from and elucidated with reference to the embodiments described hereinafter.
Drawings
The accompanying drawings illustrate exemplary embodiments and, together with the description, serve to explain exemplary implementations of the embodiments. The illustrated embodiments are for exemplary purposes only and do not limit the scope of the claims. Throughout the drawings, identical reference numerals designate similar, but not necessarily identical, elements.
Fig. 1 is a schematic diagram of an exemplary conventional distributed amplifier;
fig. 2 is a circuit configuration diagram illustrating a distributed amplifier according to an exemplary embodiment of the present disclosure;
fig. 3A and 3B are circuit configuration diagrams illustrating a variable resistor according to an exemplary embodiment of the present disclosure;
fig. 4 to 6 are circuit configuration diagrams illustrating other forms of variable resistors according to exemplary embodiments of the present disclosure;
fig. 7 is a circuit configuration diagram illustrating a gain unit according to an exemplary embodiment of the present disclosure;
fig. 8 to 10 are circuit configuration diagrams illustrating other forms of gain units according to exemplary embodiments of the present disclosure;
fig. 11 is a schematic diagram showing an exemplary circuit configuration of the gain unit shown in fig. 10 applied to the distributed amplifier shown in fig. 2; and
fig. 12 is a schematic diagram illustrating an electronic device according to an exemplary embodiment of the present disclosure.
Detailed Description
It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.
Spatially relative terms, such as "under …," "under …," "lower," "under …," "over …," "upper," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "under" or "beneath" other elements or features would then be oriented "over" the other elements or features. Thus, the exemplary terms "below …" and "below …" may encompass both orientations above … and below …. Terms such as "before …" or "before …" and "after …" or "followed by" may similarly be used, for example, to indicate the order in which light passes through the elements. The device may be oriented in other ways (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items, and the phrase "at least one of a and B" means a alone, B alone, or both a and B.
It will be understood that when an element or layer is referred to as being "on," "connected to," "coupled to," or "adjacent to" another element or layer, it can be directly on, connected to, coupled to, or adjacent to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to," or "directly adjacent to" another element or layer, there are no intervening elements or layers present. However, in no event "on …" or "directly on …" should be construed as requiring one layer to completely cover an underlying layer.
Embodiments of the present disclosure are described herein with reference to schematic illustrations (and intermediate structures) of idealized embodiments of the present disclosure. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present disclosure should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
With the explosive growth of mobile network demands and the growth of short-distance high-speed transmission demands of cloud computing and cloud storage on data centers, higher requirements are put on data transmission rates and bandwidths of communication systems. The transmission rate of the next generation communication system is required to reach 400Gbps, and a high-order modulation data mode such as PAM-4 is used in high-speed data transmission to meet the requirement, which requires not only a high transmission rate and bandwidth of a transmission circuit but also good linearity. The common-emitter and common-source amplifier can generate the phenomenon of amplification factor roll-off at high frequency due to the influence of self parasitic capacitance, and cannot meet the requirements. The basic principle of the distributed amplifier is that parasitic capacitance of the input/output end of the transistor and equivalent capacitance and inductance on the input/output transmission line are combined to form characteristic impedance of the input/output transmission line, so that amplification factor roll-off caused by the parasitic capacitance is eliminated. The distributed amplifier can break through the limitation of gain bandwidth product of the amplifier due to the structural characteristic, realize signal amplification of wider frequency band and provide better linearity.
A conventional distributed amplifier architecture is shown in fig. 1, which includes: an input transmission line, an output transmission line, one or more gain cells, and absorption resistors (Rc and Rb) connected to one ends of the input transmission line and the output transmission line, respectively. Where Zc and Zb represent the characteristic impedance over the unit transmission line segments of the input transmission line and the output transmission line, respectively. As shown in fig. 1, the unit transmission line segment length is l/2, where l represents the length of the transmission line between gain units, i.e., l/2 represents half the length of the transmission line between gain units.
After the processing is completed, the input/output transmission line and the absorption resistors (Rc and Rb) of the traditional distributed amplifier are cured, and the characteristic impedance of the transmission line is not adjustable and can only be matched with a load structure with a specific resistance value, so that the traditional distributed amplifier has no universality. When load products with different resistances exist, different distributed amplifier driving circuits need to be developed to meet the matching requirement, which increases the design difficulty and the driver production cost. There is therefore a strong need for a distributed amplifier circuit that can adapt to various resistive loads.
According to an exemplary embodiment of the present disclosure, there is provided a distributed amplifier circuit, as shown in fig. 2, including: the first end of the input transmission line is used for receiving a signal Vin to be amplified, and the second end of the input transmission line is used for receiving a first voltage Vinb; an output transmission line having a first end connected to the variable resistor Rc for receiving the second voltage Vcc and a second end for outputting the amplified signal Vout to the load circuit; the input end of each gain unit is connected to the input transmission line, and the output end of each gain unit is connected to the output transmission line; and at least one variable capacitor Cc, wherein one end of each variable capacitor Cc in the at least one variable capacitor Cc is connected with the output end of the corresponding gain unit, and the other end of each variable capacitor Cc is grounded. The resistance value of the variable resistor Rc can be adjusted so that the adjusted resistance value of the variable resistor Rc matches the resistance value of the load circuit, and the capacitance value of the variable capacitor Cc can be adjusted so that the characteristic impedance of the output transmission line obtained by adjusting the capacitance value of the variable capacitor Cc matches the resistance value of the load circuit.
The distributed amplifier circuit according to the exemplary embodiments of the present disclosure can adapt to load circuits of various resistance values by adjusting the resistance value of the variable resistor Rc and the capacitance value of the variable capacitor Cc, and has high versatility.
In this disclosure, "matching" means that the respective values thereof are equal in size or equivalent, or are substantially equal or substantially equivalent. For example, the resistance value of the regulated variable resistor Rc and the resistance value of the load circuit may not be exactly equal in consideration of the influence of the manufacturing process, raw materials, and the like thereof, so long as they are equal within the process tolerance range thereof, which indicates a match therebetween. Similarly, the characteristic impedance of the output transmission line obtained by adjusting the capacitance value of the variable capacitor Cc and the resistance value of the load circuit are equivalent within the process tolerance range, so that the characteristic impedance and the resistance value of the load circuit can be matched.
According to some embodiments, the capacitance value of the variable capacitance can be adjusted by the capacitance control voltage. A variable capacitor, i.e., a variable capacitor, whose capacitance value can be changed in accordance with a capacitance control voltage applied thereto, wherein the capacitance value can be changed smoothly within a wide capacitance control voltage range and can be easily controlled with high accuracy. In this way, the output transmission line characteristic impedance of the distributed amplifier circuit can be controlled with high accuracy over a wide range by adjusting the capacitance value of the variable capacitor to adapt to more load circuits of different resistances.
According to some embodiments, the resistance value of the variable resistor can be adjusted by a resistance control voltage. The resistance value of the variable resistor, i.e., the variable resistor, is changed according to the resistance control voltage applied thereto, and the resistance value of the variable resistor can be changed more uniformly by the resistance control voltage to achieve resistance matching more precisely. In an embodiment according to the present disclosure, a variable resistor Rc is connected to the head end of the output transmission line. One end of the variable resistor Rc is connected with the first end of the output transmission line, and the other end of the variable resistor Rc is used for receiving the bias voltage Vcc (namely, the second voltage). The resistance of the variable resistor Rc should be matched with the resistance of the load circuit to absorb the reverse signal transmitted from the output end of the gain unit. The amplified signal in the distributed amplifier is transmitted in two directions at the output end of each gain unit, so that the amplified signal is output in a non-same direction at the reverse output end, but because the reverse signal cannot be completely eliminated, a resistor Rc which can be matched with the resistance value of a load circuit is connected to the reverse output end of an output transmission line to absorb the redundant reverse signal.
After the distributed amplifier circuit is cured, the resistance value of the variable resistor Rc is not a fixed value, but can be changed along with the resistance control voltage to form different resistance values to match load circuits with different resistance values. In this way, the resistance value of the variable resistor Rc can be adjusted in a wide range with high accuracy to adapt to load circuits of different resistance values.
According to some embodiments, as shown in fig. 3A, the circuit structure of the exemplary variable resistor may include: a resistance-adjustable transistor circuit; a first operational amplifier OPA1 and a second operational amplifier OPA2; a first capacitor C1 and a second capacitor C2; and a first voltage dividing circuit and a second voltage dividing circuit; a first resistor R1 and a second resistor R2. The first end of the resistance adjustable transistor circuit is connected with the first input end of the second operational amplifier OPA2, and the second end of the resistance adjustable transistor circuit is connected with the first input end of the first operational amplifier OPA 1; a first end of the first capacitor C1 is connected to a third end of the resistance-adjustable transistor circuit, and a second end of the first capacitor C1 is connected to a node between the first resistor R1 and the second resistor R2; the first end of the second capacitor C2 is connected to the third end of the resistance-adjustable transistor circuit, and the second end of the second capacitor C2 is used for receiving resistance control voltage; the first voltage dividing circuit is connected between the second input end of the first operational amplifier OPA1 and the output end of the first operational amplifier OPA 1; and the second voltage dividing circuit is connected between the second input terminal of the second operational amplifier OPA2 and the output terminal of the second operational amplifier OPA 2. The first and second ends of the resistance-adjustable transistor circuit serve as the two ends of the variable resistor, respectively.
In some examples, the equivalent resistance of the resistance-adjustable transistor circuit may vary according to the magnitude of the voltage input at the third terminal thereof, where "equivalent resistance" may be expressed as a resistance value after being equivalent due to the combined action of the current and the voltage.
According to some embodiments, a resistance-tunable transistor circuit includes a first transistor, a second transistor, and a third transistor. The first end of the first transistor is connected to the second end of the second transistor, the second end of the first transistor is connected to the second end of the third transistor, and the second end of the first transistor is used as the second end of the resistance adjustable transistor circuit; the first end of the second transistor is connected with the first end of the third transistor, and the first end of the second transistor is used as the first end of the resistance-adjustable transistor circuit; and a second terminal of the third transistor is connected to a third terminal of the third transistor, and a third terminal of the first transistor is connected to a third terminal of the second transistor and serves as a third terminal of the resistance-adjustable transistor circuit.
By the three transistors acting together, the resistance value of the variable resistor according to this exemplary embodiment can be changed in accordance with the resistance control voltage applied thereto, and the resistance value thereof can be changed smoothly over a wide range and easily controlled with high accuracy.
According to some embodiments, the first voltage divider circuit comprises a third resistor and a fourth resistor connected in series, and the second voltage divider circuit comprises a fifth resistor and a sixth resistor connected in series. The second input end of the first operational amplifier is connected to a node between the third resistor and the fourth resistor, the output end of the first operational amplifier is connected to a node between the fourth resistor and the first resistor, and one end of the third resistor, which is not connected with the fourth resistor, is grounded; and the second input end of the second operational amplifier is connected to a node between the fifth resistor and the sixth resistor, the output end of the second operational amplifier is connected to a node between the sixth resistor and the second resistor, and one end of the fifth resistor, which is not connected with the sixth resistor, is grounded.
According to some embodiments, as shown in fig. 3B, the circuit structure of the exemplary variable resistor may include: a first transistor M1, a second transistor M2, and a third transistor M3; a first operational amplifier OPA1 and a second operational amplifier OPA2; a first capacitor C1 and a second capacitor C2; and a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6. A first end of the first transistor M1 is connected to a second end of the second transistor M2, and a second end of the first transistor M1 is connected to a first input end of the first operational amplifier OPA1 and a second end of the third transistor M3; a first terminal of the second transistor M2 is connected to a first input terminal of the second operational amplifier OPA2 and a first terminal of the third transistor M3; the second terminal of the third transistor M3 is connected to the third terminal of the third transistor M3; the first end of the first capacitor C1 is connected to the third end of the first transistor M1 and the third end of the second transistor M2, and the second end of the first capacitor C1 is connected to a node between the first resistor R1 and the second resistor R2; the first end of the second capacitor C2 is connected to the third end of the first transistor M1 and the third end of the second transistor M2, and the second end of the second capacitor C2 is used for receiving the resistance control voltage Vctrl; the second input end of the first operational amplifier OPA1 is connected to a node between the third resistor R3 and the fourth resistor R4, and the output end of the first operational amplifier OPA1 is connected to a node between the first resistor R1 and the fourth resistor R4; and, a second input terminal of the second operational amplifier OPA2 is connected to a node between the fifth resistor R5 and the sixth resistor R6, an output terminal of the second operational amplifier OPA2 is connected to a node between the second resistor R2 and the sixth resistor R6, and a second terminal (Vd) of the first transistor M1 and a first terminal (Vs) of the second transistor M2 serve as both ends of the variable resistor, respectively.
According to some embodiments, the first transistor M1, the second transistor M2, and the third transistor M3 in the variable resistor as described above may be MOS transistors or bipolar transistors.
In some examples, the first transistor M1, the second transistor M2, and the third transistor M3 may be NMOS transistors. In the example where the first transistor M1, the second transistor M2, and the third transistor M3 are NMOS transistors, the first terminal of the first transistor M1, the second terminal of the second transistor M2, and the third terminal of the third transistor M3 are sources, the second terminal is a drain, and the third terminal is a gate. In some examples, the first transistor M1, the second transistor M2, and the third transistor M3 may be PMOS transistors, and their connection manners may be adaptively modified.
In some examples, the first transistor M1, the second transistor M2, and the third transistor M3 may be NPN bipolar transistors. In the example where the first transistor M1, the second transistor M2, and the third transistor M3 are NPN bipolar transistors, the first terminal of the first transistor M1, the second terminal of the second transistor M2, and the third terminal of the third transistor M3 are emitters, the second terminal is a collector, and the third terminal is a base. In some examples, the first transistor M1, the second transistor M2, and the third transistor M3 may be PNP bipolar transistors, and their connection manners may be adaptively modified.
According to some embodiments, the resistance values of the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, and the sixth resistor R6 in the variable resistor shown in fig. 3B are the same. The specific resistance values of R1 to R6 are set by the circuit designer according to the specific requirements, and are not limited herein.
According to some embodiments, the capacitance values of the first capacitor C1 and the second capacitor C2 in the variable resistor as shown in fig. 3A and 3B are the same. The specific capacitance values of C1 and C2 are set by the circuit designer according to the specific requirements, and are not limited herein.
As shown in fig. 3, the second terminal (Vd) of the first transistor M1 and the first terminal (Vs) of the second transistor M2 serve as both ends of the variable resistor Rc, respectively, and the second terminal of the second capacitor C2 is used to receive the resistor control voltage Vctrl to realize the resistance value variation of the variable resistor Rc by adjusting the voltage. In the first transistor M1, the second transistor M2 and the third transistorIn the example where the transistor M3 is an NMOS transistor, the drain current I flowing through the first transistor M1 and the second transistor M2 D Can be expressed in the form of formula (1):
where β is the current coefficient, which is related to aspect ratio of the transistor, carrier mobility, oxide capacitance; v (V) th Is the threshold voltage. Under the common regulation of two operational amplifiers OPA1 and OPA2 and six resistors R1-R6, V can be made 1 Expressed in the form of formula (2):
V 1 ＝V DS +2V S when V DS ＞0，R 1～6 ＝R (2)
By connecting two capacitors C1 and C2 with equal capacitance values, the gate voltages of the first transistor M1 and the second transistor M2 can be deduced to be the form of formula (3);
wherein V is ctrl Is a resistance control voltage. Expression (4) of the variable resistance Rc can be deduced from formulas (1) and (3):
for NMOS transistor to operate in the linear region, V GS The condition of equation (5) must be satisfied:
V GS ＞V DS +V th (5)
from the equation (5) and the equations (3) and (4), the maximum resistance value of the variable resistance Rc is derived as shown in the equation (6):
from the above derivationIt can be seen that the resistance value of the variable resistor Rc can be controlled by the resistance control voltage V ctrl And changes from variation to variation.
According to some embodiments, R c_max 200 ohms. For example, the resistance value of the variable resistor Rc can be adjusted in the range of 10 ohms to 200 ohms. After the distributed amplifier circuit is processed and cured, the resistance value of the variable resistor Rc is not a fixed value, but can form different resistance values along with the change of the resistance control voltage so as to match load circuits with different resistance values. It should be noted that the above-described resistance ranges of the variable resistor Rc are merely examples, and are not limiting of the present disclosure. The resistance range of the variable resistor Rc can be selected by those skilled in the art according to different applications and/or requirements.
Fig. 4 to 6 show other exemplary circuit configuration diagrams of variable resistors in a distributed amplifier circuit according to an embodiment of the present disclosure.
As shown in fig. 4, in this exemplary variable resistance circuit structure, a first input terminal and a second input terminal of a summing circuit are respectively connected to a drain and a source of a MOS transistor M, a third input terminal of the summing circuit is connected to a positive terminal of a first control voltage Vb, a negative terminal of the first control voltage Vb is grounded, and an output terminal of the summing circuit is grounded through two resistors R connected in series. The gate of the MOS transistor M1 is connected with the positive terminal of a second control voltage Vc, and the negative terminal of the second control voltage Vc is connected between two resistors R connected in series. The drain and source of the MOS transistor M serve as both ends of the exemplary variable resistor, respectively. In this exemplary structure, the first control voltage Vb and the second control voltage Vc together constitute a resistance control voltage to achieve adjustment of the resistance value magnitude of the exemplary variable resistor by adjusting the voltage magnitudes of the first control voltage Vb and the second control voltage Vc. As shown in fig. 4, the output terminal voltage of the summing circuit may be expressed as: vd+vs+vb, the voltage between two resistors R in series can be expressed as: In this exemplary configuration, the model and size of each device is not specifiedThe body limits, the circuit designer can be set according to the specific requirements.
As shown in fig. 5, in another exemplary variable resistance circuit structure, the drain and source of the MOS transistor M are connected to both ends of the inductance L, respectively, which serve as both ends of the exemplary variable resistance. The gate of the MOS transistor M is configured to receive the resistance control voltage Vctrl to achieve adjustment of the resistance value of the exemplary variable resistor by adjusting the voltage magnitude of the resistance control voltage Vctrl. In this exemplary structure, the model and size of each device are not particularly limited, and the circuit designer may be set according to the specific requirements thereof.
As shown in fig. 6, in another exemplary variable resistance circuit structure, the drain and gate of the MOS transistor M1 are connected, and the drain of the MOS transistor M1 is also connected to a voltage V DD The method comprises the steps of carrying out a first treatment on the surface of the The source electrode of the MOS transistor M1 is connected with the drain electrode of the MOS transistor M4, and the drain electrode and the gate electrode of the MOS transistor M4 are connected; the drain of the MOS transistor M2 is connected with the drain of the MOS transistor M5, the drain of the MOS transistor M2 and the drain of the MOS transistor M5 are also connected with the source of the MOS transistor M1 and the drain of the MOS transistor M4, and the source of the MOS transistor M2 is connected with the voltage V DD The method comprises the steps of carrying out a first treatment on the surface of the The gate of the MOS transistor M5 is grounded, and the source of the MOS transistor M5 is connected with the voltage Vss; the gate of the MOS transistor M2 is connected with the gate of the MOS transistor M3, and the source of the MOS transistor M3 is connected with the voltage V DD The grid electrode and the drain electrode of the MOS transistor M3 are connected, and the drain electrode of the MOS transistor M3 is also connected with the drain electrode of the MOS transistor M6; the source of the MOS transistor M6 and the source of the MOS transistor M4 are connected for receiving the resistance control voltage Vctrl; the gate of the MOS transistor M4 and the gate of the MOS transistor M6 serve as both ends of the exemplary variable resistor, respectively. Wherein V is DD And Vss as the drain and source voltages of MOS transistors, typically V DD May be a dc voltage and Vss may be grounded. Adjusting the magnitude of the resistance value of the exemplary variable resistor is achieved by adjusting the magnitude of the resistance control voltage Vctrl. In this exemplary structure, the model and size of each device are not particularly limited, and the circuit designer may be set according to the specific requirements thereof.
It should be appreciated that the circuit configuration of the variable resistor in the distributed amplifier circuit according to the embodiments of the present disclosure is not limited to the form described above, and any configuration of variable resistor that can be used in the distributed amplifier circuit is possible and is not limited herein.
Returning to fig. 2, in a distributed amplifier circuit according to an embodiment of the present disclosure, the characteristic impedance of an input transmission line may be matched to the resistance of an input signal source for providing a signal to be amplified.
In some examples, the characteristic impedance of the input transmission line need not be designed to be variable. For example, for an input transmission line, the resistance of the input signal source may be generally 50 ohms, so the characteristic impedance of the input transmission line only needs to be designed to be a fixed 50 ohms. The characteristic impedance of the input transmission line does not need to be designed into a variable form, so that the circuit structure is simple, the functional requirement can be met, the design difficulty of the distributed amplifier circuit and the manufacturing cost of the distributed amplifier circuit are reduced, and the distributed amplifier circuit has high practicability.
According to some embodiments, a distributed amplifier circuit according to embodiments of the present disclosure further includes a resistor Rb connected to the second end of the input transmission line. The resistance of the resistor Rb is matched with the resistance of the input signal source.
In the example where the characteristic impedance of the input transmission line is fixed, the resistance value of the resistor Rb may be designed to be equal to the resistance value of the input signal source. For example, for an input transmission line, the resistance of the input signal source may be generally 50 ohms, so the resistance of the resistor Rb only needs to be designed to be a fixed 50 ohms. As described above, the circuit structure is simple, the functional requirement can be met, and the design difficulty and the manufacturing cost of the distributed amplifier circuit are reduced.
The signal to be amplified from the input signal source is input to the distributed amplifier circuit, amplified layer by layer, and the output amplified signal is input to the load circuit to drive the load circuit.
According to some embodiments, the load circuit of the distributed amplifier circuit may be an optical module load circuit. Optical modulators such as Mach-zehnder modulators (Mach-Zehnder Modulator) are widely used in next generation high speed communication systems, and the use of distributed amplifiers as modulator driving circuits can provide a wide frequency band and good linearity to meet the requirements of high rate data transmission. Because the optical module loads of different optical modulator products of different companies and even the same company have different resistances, the optical module loads may have more general 50 ohm loads, and may also have loads adopting resistances of 25 ohms, 30 ohms and the like in order to improve the modulator bandwidth. By adopting the distributed amplifier circuit according to the embodiment of the disclosure, the optical module load circuit can be applied to optical module load circuits with various resistance values. Therefore, the optical module load with different resistance values can be driven by using one distributed amplifier circuit, so that the effect of one core with multiple purposes is achieved. This greatly reduces the technical difficulty of various distributed amplifier circuit designs and the manufacturing cost thereof, and has high practicability.
After the signal input into the distributed amplifier circuit is amplified by at least one gain unit, in-phase superposition is formed at the output end, and the finally generated amplified signal is input into the load circuit.
According to some embodiments, the at least one gain cell comprises a plurality of gain cells, and each gain cell has the same circuit structure. According to some embodiments, each gain cell is a cascode structure. The structure can increase the impedance of the output end of the gain unit and improve the output voltage swing; and meanwhile, the miller effect of the transistor at the input end of the gain unit can be reduced, so that the parasitic capacitance of the input end is reduced.
According to an exemplary embodiment of the present disclosure, there is also provided a gain unit. As shown in fig. 7, the gain unit includes: a first transistor Q1 and a second transistor Q2; and a first resistor R1 and a second resistor R2. A first end of the first transistor Q1 is connected to the current bias circuit, a second end of the first transistor Q1 is connected to a first end of the second transistor Q2, and a third end of the first transistor Q1 serves as an input end of the gain unit; the second terminal of the second transistor Q2 is connected to the third terminal of the second transistor Q2 through the first resistor R1, the third terminal of the second transistor Q2 is connected to the bias voltage source Vb through the second resistor R2, and the second terminal of the second transistor Q2 serves as an output terminal of the gain unit.
The first resistor R1 and the second resistor R2 are added between the third terminal and the second terminal of the second transistor Q2 and the third terminal thereof as feedback resistors, which can increase the linearity of the gain unit and increase the withstand voltage capability between the second terminal and the first terminal of the second transistor Q2.
The bias voltage source Vb is typically a dc bias voltage source, and the third terminal of the second transistor Q2 is connected to the bias voltage source Vb to manually control the transistor to adapt to the circuit bias point variation caused by the variation of the transistor along with the temperature, the process, the voltage, etc.
According to some embodiments, as shown in fig. 8 and 9, the gain unit may further include a first capacitor C1, wherein the third terminal of the second transistor Q2 is grounded through the first capacitor C1. The first capacitor C1 may filter low frequency noise of the bias voltage source Vb.
Although the first transistor Q1 and the second transistor Q2 are illustrated as bipolar transistors in fig. 7 to 9, the first transistor and the second transistor may be MOS transistors according to some embodiments.
In some examples, the first transistor Q1 and the second transistor Q2 may be NMOS transistors. In the example where the first transistor Q1 and the second transistor Q2 are NMOS transistors, the first terminal of the first transistor Q1 and the second transistor Q2 are sources, the second terminal is a drain, and the third terminal is a gate. In some examples, the first transistor Q1 and the second transistor Q2 may be PMOS transistors, and their connection manners may be adaptively modified.
The current bias circuit in the gain cell according to the embodiments of the present disclosure may provide a constant current that is related to the amplification factor of the gain cell.
According to some embodiments, as shown in fig. 8, the current bias circuit may include a third resistor R3 and a third transistor Q3, the third resistor R3 and the third transistor Q3 being coupled in series between the first terminal of the first transistor Q1 and ground. By externally connecting the third terminal of the third transistor Q3 to a bias voltage source, the magnitude of the current flowing through the first transistor Q1 can be controlled. In this exemplary structure, the model and size of each device are not particularly limited, and the circuit designer may be set according to the specific requirements thereof.
According to some embodiments, as shown in fig. 9, the current bias circuit may include a third resistor R3, a fourth resistor R4, and a second capacitor C2, the third resistor R3 and the fourth resistor R4 being coupled in series between the first terminal of the first transistor Q1 and ground, the second capacitor C2 being connected in parallel with the fourth resistor R4. In this exemplary structure, the model and size of each device are not particularly limited, and the circuit designer may be set according to the specific requirements thereof.
According to some embodiments, the second terminal of the first transistor Q1 may be connected to the first terminal of the second transistor Q2 through an inductance. As shown in fig. 10, an inductance is connected between the second terminal of the first transistor Q1 and the first terminal of the second transistor Q2 on the basis of the circuit configuration of fig. 8. By the inductor, the bandwidth of the gain unit can be improved, so that the requirement of users on the increasing bandwidth is further met.
According to some embodiments, gain cells as shown in fig. 7-10 can be used for distributed amplifiers. For example, the gain cells described in the above embodiments may be used in the distributed amplifier circuits described above according to embodiments of the present disclosure.
A schematic circuit configuration of the application of the gain unit shown in fig. 10 to the distributed amplifier circuit shown in fig. 2 is shown in fig. 11. In this exemplary circuit configuration, the amplification effect of the distributed amplifier is the sum of the amplification effects of the respective gain units, and the gain thereof is as shown in formula (7):
wherein g m Is the transconductance of the gain units, N is the number of the gain units, zb and Zc are the characteristic impedance of the input transmission line and the output transmission line respectively, and Ab and Ac are the attenuation of the input transmission line and the output transmission line respectively.
More gain cells appear to increase the amplification factor, however, as the number of gain cells increases, the attenuation of the input transmission line and the output transmission line becomes a main factor limiting the gain, and the maximum number of gain cells in the distributed amplifier circuit is shown in formula (8):
in some examples, the number of gain cells selected may be 6, and each gain cell may be 300 microns apart.
The parasitic capacitance of the input end and the output end of the transistor and the equivalent capacitance and inductance on the input transmission line and the output transmission line are combined to form the characteristic impedance of the input transmission line and the output transmission line, the characteristic impedance of the input transmission line and the output transmission line is matched with the signal source resistance and the load resistance, and the characteristic impedance is shown in formulas (9) and (10):
wherein L' b 、C′ b Is the inductance and capacitance value, L 'of the input transmission line unit length between the gain units' c 、C′ c The inductance and capacitance value of the output transmission line unit length between the gain units, l is the length of the transmission line between the gain units, C in Is the parasitic capacitance of the input end of the gain unit, C out Is the parasitic capacitance at the output of the gain cell. After processing and curing, the traditional distributed amplifier is L' b 、C′ b 、L′ c 、C′ c 、C in 、C out Both have cured, resulting in the characteristic impedance of the input and output transmission lines not being altered, which can only match the input signal source and load circuit of fixed resistance. For the input transmission line, the input signal source resistance can be 50 ohms, so the characteristic impedance of the input transmission line can be designed to be 50 ohms, and the input transmission line is not required to be designed to be variable. For a pair ofWith the distributed amplifier circuit according to the embodiment of the present disclosure, on the output transmission line, the output end of each gain unit may be connected in parallel with a variable capacitor Cc capable of voltage regulation, so that the formula (10) is changed into the form of the formula (11):
The variable capacitance Cc may be varied in value with the capacitance control voltage to vary the characteristic impedance Z of the output transmission line c Thereby matching the load circuits with different resistance values.
In some examples, a distributed amplifier circuit according to embodiments of the present disclosure may employ a SiGe BiCMOS process. Devices manufactured by SiGe BiCMOS processes, which are a combination of SiGe heterojunction bipolar transistor processes and CMOS processes, have been developed as mainstream devices for manufacturing radio frequency transceivers with advantages of excellent frequency response characteristics, low noise, high linearity, high efficiency, and the like, and have been further applied to distributed amplifier circuits. The SiGe BiCMOS process can be directly used to create various parts of the devices in the distributed amplifier circuit, including the various devices that make up the gain cell. Wherein a voltage controlled variable capacitor element is provided in the SiGe BiCMOS process used, which is directly applicable to the variable capacitance Cc of the output of each gain cell.
In examples where the distributed amplifier circuit according to embodiments of the present disclosure employs a SiGe BiCMOS process, the transistors used in its gain cells may be, for example, bipolar transistors. Since the circuit structure of the gain cell may also be formed by other forms of circuit elements, the distributed amplifier circuit according to embodiments of the present disclosure may also employ other fabrication processes, such as CMOS, CMOS SOI, gaAs processes, and the like.
According to an exemplary embodiment of the present disclosure, there is also provided an electronic apparatus. The electronic device may comprise a distributed amplifier circuit as described above.
Fig. 12 illustrates an exemplary schematic diagram of the electronic device, according to some embodiments. The electronic device 1200 may include a signal source 1210, a distributed amplifier 1220, and an optical module load 1230. The distributed amplifier 1220 may embody any of the distributed amplifier circuits described above and variations thereof, and the gain cells in the distributed amplifier 1220 may embody any of the gain cells described above and variations thereof.
While the disclosure has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative and schematic and not restrictive; the present disclosure is not limited to the disclosed embodiments. Variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed subject matter, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps than those listed and the indefinite article "a" or "an" does not exclude a plurality, and the term "plurality" means two or more. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
Aspect 1. A distributed amplifier circuit comprising:
an input transmission line, a first end of the input transmission line being configured to receive a signal to be amplified, and a second end of the input transmission line being configured to receive a first voltage;
an output transmission line having a first end connected to the variable resistor for receiving the second voltage and a second end for outputting the amplified signal to the load circuit;
at least one gain cell, an input of each gain cell of the at least one gain cell being connected to the input transmission line, an output of each gain cell being connected to the output transmission line; and
at least one variable capacitor, one end of each variable capacitor is connected with the output end of the corresponding gain unit, the other end of each variable capacitor is grounded,
wherein the resistance of the variable resistor is adjustable such that the adjusted resistance of the variable resistor matches the resistance of the load circuit, an
The capacitance value of the variable capacitor can be adjusted so that the characteristic impedance of the output transmission line obtained by adjusting the capacitance value of the variable capacitor is matched with the resistance value of the load circuit.
Aspect 2. The distributed amplifier circuit of aspect 1, wherein the capacitance value of the variable capacitance is adjustable by a capacitance control voltage.
Aspect 3. The distributed amplifier circuit of aspect 1, wherein the resistance value of the variable resistor is adjustable by a resistor control voltage.
Aspect 4 the distributed amplifier circuit of aspect 3, wherein the variable resistor comprises:
a resistance-adjustable transistor circuit;
a first operational amplifier and a second operational amplifier;
a first capacitor and a second capacitor;
a first voltage dividing circuit and a second voltage dividing circuit; and
a first resistor and a second resistor,
wherein:
the first end of the resistance adjustable transistor circuit is connected with the first input end of the second operational amplifier, and the second end of the resistance adjustable transistor circuit is connected with the first input end of the first operational amplifier;
a first end of the first capacitor is connected to a third end of the resistance-adjustable transistor circuit, and a second end of the first capacitor is connected to a node between the first resistor and the second resistor;
the first end of the second capacitor is connected to the third end of the resistance-adjustable transistor circuit, and the second end of the second capacitor is used for receiving the resistance control voltage;
The first voltage dividing circuit is connected between the second input end of the first operational amplifier and the output end of the first operational amplifier; and
the second voltage dividing circuit is connected between the second input end of the second operational amplifier and the output end of the second operational amplifier
The first end and the second end of the resistance-adjustable transistor circuit are respectively used as two ends of the variable resistor.
Aspect 5 the distributed amplifier circuit of aspect 4, wherein the resistance-tunable transistor circuit comprises a first transistor, a second transistor, and a third transistor, wherein:
a first end of the first transistor is connected to a second end of the second transistor, the second end of the first transistor is connected to a second end of the third transistor, and the second end of the first transistor is used as a second end of the resistance adjustable transistor circuit;
the first end of the second transistor is connected with the first end of the third transistor, and the first end of the second transistor is used as the first end of the resistance-adjustable transistor circuit; and
the second end of the third transistor is connected to the third end of the third transistor, and
Wherein the third terminal of the first transistor is connected to the third terminal of the second transistor and serves as the third terminal of the resistance-tunable transistor circuit.
Aspect 6 the distributed amplifier circuit of aspect 5, wherein the first voltage divider circuit comprises a third resistor and a fourth resistor connected in series, and the second voltage divider circuit comprises a fifth resistor and a sixth resistor connected in series, wherein:
a second input end of the first operational amplifier is connected to a node between the third resistor and the fourth resistor, an output end of the first operational amplifier is connected to a node between the fourth resistor and the first resistor, and one end of the third resistor which is not connected with the fourth resistor is grounded; and
the second input end of the second operational amplifier is connected to a node between the fifth resistor and the sixth resistor, the output end of the second operational amplifier is connected to a node between the sixth resistor and the second resistor, and one end of the fifth resistor, which is not connected with the sixth resistor, is grounded.
Aspect 7. The distributed amplifier circuit of aspect 6, wherein the resistances of the first resistor, the second resistor, the third resistor, the fourth resistor, the fifth resistor, and the sixth resistor are the same.
Aspect 8. The distributed amplifier circuit of aspect 4, wherein the capacitance values of the first capacitor and the second capacitor are the same.
Aspect 9. The distributed amplifier circuit of aspect 5, wherein the first transistor, the second transistor, and the third transistor are MOS transistors or bipolar transistors.
Aspect 10. The distributed amplifier circuit of aspect 1, wherein the characteristic impedance of the input transmission line matches a resistance of an input signal source for providing the signal to be amplified.
Aspect 11 the distributed amplifier circuit of aspect 1, further comprising a resistor connected to the second end of the input transmission line, wherein the resistance value of the resistor matches the resistance value of the input signal source.
Aspect 12 the distributed amplifier circuit of any of aspects 1-11, wherein the load circuit is an optical module load circuit.
Aspect 13 the distributed amplifier circuit of any of aspects 1-11, wherein the at least one gain cell comprises a plurality of gain cells, and each gain cell has the same circuit structure.
Aspect 14 the distributed amplifier circuit of aspect 13, wherein each gain cell is a cascode structure.
Aspect 15. A gain unit comprising:
a first transistor and a second transistor; and
a first resistor and a second resistor,
wherein:
a first end of the first transistor is connected to a current bias circuit, a second end of the first transistor is connected to a first end of the second transistor, and a third end of the first transistor is used as an input end of the gain unit;
the second end of the second transistor is connected to the third end of the second transistor through the first resistor, the third end of the second transistor is connected to a bias voltage source through the second resistor, and the second end of the second transistor serves as an output end of the gain unit.
Aspect 16 the gain cell of aspect 15, wherein the second terminal of the first transistor is connected to the first terminal of the second transistor through an inductance.
Aspect 17 the gain cell of aspect 15, further comprising a first capacitor, wherein a third terminal of the second transistor is coupled to ground through the first capacitor.
Aspect 18 the gain cell of aspect 15, wherein the current bias circuit includes a third resistor and a third transistor, the third resistor and the third transistor coupled in series between the first terminal of the first transistor and ground.
Aspect 19 the gain cell of aspect 15, wherein the current bias circuit comprises a third resistor, a fourth resistor, and a second capacitor, the third resistor and the fourth resistor coupled in series between the first terminal of the first transistor and ground, the second capacitor in parallel with the fourth resistor.
Aspect 20 the gain cell of aspect 15, wherein the first transistor and the second transistor are MOS transistors or bipolar transistors.
Aspect 21 the gain unit of any one of aspects 15-20, wherein the gain unit is for a distributed amplifier.
Aspect 22. An electronic device, comprising:
the distributed amplifier circuit of any of aspects 1-14.
Claims (13)
1. A distributed amplifier circuit comprising:
an input transmission line, a first end of the input transmission line being configured to receive a signal to be amplified, and a second end of the input transmission line being configured to receive a first voltage;
an output transmission line having a first end connected to the variable resistor for receiving the second voltage and a second end for outputting the amplified signal to the load circuit;
at least one gain cell, an input of each gain cell of the at least one gain cell being connected to the input transmission line, an output of each gain cell being connected to the output transmission line; and
At least one variable capacitor, one end of each variable capacitor is connected with the output end of the corresponding gain unit, the other end of each variable capacitor is grounded,
wherein the resistance of the variable resistor is adjustable such that the adjusted resistance of the variable resistor matches the resistance of the load circuit, an
Wherein the capacitance value of the variable capacitor is adjustable so that the characteristic impedance of the output transmission line obtained by adjusting the capacitance value of the variable capacitor matches the resistance value of the load circuit,
wherein, the resistance value of the variable resistor can be adjusted by a resistance control voltage, the variable resistor includes:
a resistance-adjustable transistor circuit;
a first operational amplifier and a second operational amplifier;
a first capacitor and a second capacitor;
a first voltage dividing circuit and a second voltage dividing circuit; and
a first resistor and a second resistor,
wherein:
the first end of the resistance adjustable transistor circuit is connected with the first input end of the second operational amplifier, and the second end of the resistance adjustable transistor circuit is connected with the first input end of the first operational amplifier;
a first end of the first capacitor is connected to a third end of the resistance-adjustable transistor circuit, and a second end of the first capacitor is connected to a node between the first resistor and the second resistor;
The first end of the second capacitor is connected to the third end of the resistance-adjustable transistor circuit, and the second end of the second capacitor is used for receiving the resistance control voltage;
the first voltage dividing circuit is connected between the second input end of the first operational amplifier and the output end of the first operational amplifier; and
the second voltage dividing circuit is connected between the second input end of the second operational amplifier and the output end of the second operational amplifier
The first end and the second end of the resistance-adjustable transistor circuit are respectively used as two ends of the variable resistor.
2. The distributed amplifier circuit of claim 1 wherein the capacitance value of the variable capacitance is adjustable by a capacitance control voltage.
3. The distributed amplifier circuit of claim 1, wherein the resistance-tunable transistor circuit comprises a first transistor, a second transistor, and a third transistor, wherein:
a first end of the first transistor is connected to a second end of the second transistor, the second end of the first transistor is connected to a second end of the third transistor, and the second end of the first transistor is used as a second end of the resistance adjustable transistor circuit;
The first end of the second transistor is connected with the first end of the third transistor, and the first end of the second transistor is used as the first end of the resistance-adjustable transistor circuit; and
the second end of the third transistor is connected to the third end of the third transistor, and
wherein the third terminal of the first transistor is connected to the third terminal of the second transistor and serves as the third terminal of the resistance-tunable transistor circuit.
4. A distributed amplifier circuit as claimed in claim 3, wherein the first voltage divider circuit comprises a third resistor and a fourth resistor connected in series, and the second voltage divider circuit comprises a fifth resistor and a sixth resistor connected in series, wherein:
a second input end of the first operational amplifier is connected to a node between the third resistor and the fourth resistor, an output end of the first operational amplifier is connected to a node between the fourth resistor and the first resistor, and one end of the third resistor which is not connected with the fourth resistor is grounded; and
the second input end of the second operational amplifier is connected to a node between the fifth resistor and the sixth resistor, the output end of the second operational amplifier is connected to a node between the sixth resistor and the second resistor, and one end of the fifth resistor, which is not connected with the sixth resistor, is grounded.
5. The distributed amplifier circuit of claim 4, wherein the first resistor, the second resistor, the third resistor, the fourth resistor, the fifth resistor, and the sixth resistor have the same resistance value.
6. The distributed amplifier circuit of claim 1, wherein the capacitance values of the first and second capacitances are the same.
7. A distributed amplifier circuit as claimed in claim 3, wherein said first, second and third transistors are MOS transistors or bipolar transistors.
8. The distributed amplifier circuit of claim 1 wherein the characteristic impedance of the input transmission line matches the impedance of an input signal source used to provide the signal to be amplified.
9. The distributed amplifier circuit of claim 1, further comprising a resistor connected to the second end of the input transmission line, wherein the resistance value of the resistor matches the resistance value of an input signal source for providing the signal to be amplified.
10. The distributed amplifier circuit of any of claims 1-9, wherein the load circuit is an optical module load circuit.
11. The distributed amplifier circuit of any of claims 1-9, wherein the at least one gain cell comprises a plurality of gain cells, and each gain cell has the same circuit structure.
12. The distributed amplifier circuit of claim 11, wherein each gain cell is a cascode structure.
13. An electronic device, comprising:
the distributed amplifier circuit of any of claims 1-12.
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