KR960028197A - Contrast Mute Circuit of Multi-Sync Monitor - Google Patents

Contrast Mute Circuit of Multi-Sync Monitor Download PDF

Info

Publication number
KR960028197A
KR960028197A KR1019940040263A KR19940040263A KR960028197A KR 960028197 A KR960028197 A KR 960028197A KR 1019940040263 A KR1019940040263 A KR 1019940040263A KR 19940040263 A KR19940040263 A KR 19940040263A KR 960028197 A KR960028197 A KR 960028197A
Authority
KR
South Korea
Prior art keywords
microprocessor
pulse width
voltage
setting unit
width modulated
Prior art date
Application number
KR1019940040263A
Other languages
Korean (ko)
Other versions
KR0133144B1 (en
Inventor
윤성진
Original Assignee
배순훈
대우전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 배순훈, 대우전자 주식회사 filed Critical 배순훈
Priority to KR1019940040263A priority Critical patent/KR0133144B1/en
Publication of KR960028197A publication Critical patent/KR960028197A/en
Application granted granted Critical
Publication of KR0133144B1 publication Critical patent/KR0133144B1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/80—Camera processing pipelines; Components thereof
    • H04N23/81—Camera processing pipelines; Components thereof for suppressing or minimising disturbance in the image signal generation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/08—Separation of synchronising signals from picture signals
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/26—Pc applications
    • G05B2219/2615—Audio, video, tv, consumer electronics device

Abstract

본 발명은 멀티 동기 모니터에 관한 것으로, 특히 멀티 동기 모니터의 모드 전환시 출력전압을 뮤트시킴으로써, 화면에 나타나는 노이즈를 제거할 수 있도록, 컴퓨터로부터 입력되는 수직 동기신호 및 수평 동기신호의 유무를 판단하여 설정된모드에 따른 펄스폭 변조신호를 출력시키는 마이크로 프로세서와 상기 마이크로 프로세서에서 출력되는 펄스폭 변조신호의 직류레벨을 결정하는 직류레벨 설정부, 상기 직류레벨 설정부에서 결정 스위칭되어 전압을 분배하여 출력시키는 전압분배부 및 상기 마이크로 프로세서로부터 출력되는 펄스폭 변조 신호의 모드 전환시 출력전압을 뮤투시키는 뮤트 회로부로 구성한 멀티 동기 모니터의 콘트라스트 뮤트 회로를 제공한 것이다.The present invention relates to a multi-synchronous monitor, and in particular, by muting the output voltage during mode switching of the multi-synchronous monitor, the presence or absence of a vertical sync signal and a horizontal sync signal inputted from a computer can be determined by removing noise on the screen. A microprocessor for outputting a pulse width modulated signal according to a set mode and a DC level setting unit for determining the DC level of the pulse width modulation signal output from the microprocessor, the DC level setting unit is switched in the DC level setting unit to distribute the voltage The present invention provides a contrast muting circuit of a multi-synchronous monitor comprising a voltage divider and a mute circuit unit for muting an output voltage when switching a mode of a pulse width modulated signal output from the microprocessor.

Description

멀티동기 모니터의 큰트라스트 뮤트회로Large mute circuit of multi-synchronous monitor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의한 멀티 동기 모니터의 콘트라스트 뮤트 회로도이다.2 is a contrast mute circuit diagram of a multi-synchronous monitor according to the present invention.

Claims (1)

컴퓨터로부터 입력되는 수직 동기신호 및 수평 동기신호의 유무를 판단하여 설정된 모드에 따른 펄스폭 변조신호를 출력시키는 마이크로 프로세서(1)와 ; 상기 마이크로 프로세서(1)에서 출력되는 펄스폭 변조신호의 직류 레벨을 결정하는 직류레벨 설정부(2); 상기 직류레벨 설정부(2)에서 결정된 직류 레벨의 노이즈를 제거하고 RC 시정수에 의해 적분하여 저주파 노이즈를 줄이는 평활부(3) ; 상기 평활부(3)에서 출력되는 전압으로 스위칭되어 전압을 분배하여 출력시키는 전압 분배부(4) 및 ; 상기 마이크로 프로세서(1)로부터 출력되는 펄스폭 변조신호의 모드 전환시 출력전압을 뮤트시키는 뮤트 회로부(5)로 구성됨을 특징으로 하는 동기 모니터의 콘트라스트 뮤트 회로.A microprocessor (1) for determining the presence or absence of the vertical synchronizing signal and the horizontal synchronizing signal input from the computer and outputting a pulse width modulated signal according to a set mode; A DC level setting unit (2) for determining a DC level of the pulse width modulated signal output from the microprocessor (1); A smoothing unit 3 which removes the noise of the DC level determined by the DC level setting unit 2 and integrates the RC time constant to reduce low frequency noise; A voltage divider 4 which is switched to the voltage output from the smoothing unit 3 and divides and outputs the voltage; And a mute circuit unit (5) for muting the output voltage when switching the mode of the pulse width modulated signal output from the microprocessor (1). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940040263A 1994-12-31 1994-12-31 A contrast mute circuit of multi-sync monitor KR0133144B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940040263A KR0133144B1 (en) 1994-12-31 1994-12-31 A contrast mute circuit of multi-sync monitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940040263A KR0133144B1 (en) 1994-12-31 1994-12-31 A contrast mute circuit of multi-sync monitor

Publications (2)

Publication Number Publication Date
KR960028197A true KR960028197A (en) 1996-07-22
KR0133144B1 KR0133144B1 (en) 1998-04-16

Family

ID=19406065

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940040263A KR0133144B1 (en) 1994-12-31 1994-12-31 A contrast mute circuit of multi-sync monitor

Country Status (1)

Country Link
KR (1) KR0133144B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100517179B1 (en) * 1998-10-29 2005-11-25 주식회사 현대오토넷 Apparatus and method for removing video noise of vehicle video CD
CN112234945A (en) * 2020-10-14 2021-01-15 联合微电子中心有限责任公司 Distributed amplifier circuit, gain cell and electronic device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102350623B1 (en) 2014-12-26 2022-01-11 엘에스전선 주식회사 Termination connection part for power cable

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100517179B1 (en) * 1998-10-29 2005-11-25 주식회사 현대오토넷 Apparatus and method for removing video noise of vehicle video CD
CN112234945A (en) * 2020-10-14 2021-01-15 联合微电子中心有限责任公司 Distributed amplifier circuit, gain cell and electronic device
CN112234945B (en) * 2020-10-14 2024-02-27 联合微电子中心有限责任公司 Distributed amplifier circuit, gain unit and electronic device

Also Published As

Publication number Publication date
KR0133144B1 (en) 1998-04-16

Similar Documents

Publication Publication Date Title
KR950010575A (en) Video display device
KR880014813A (en) PLL Image Detection Circuit
KR960028197A (en) Contrast Mute Circuit of Multi-Sync Monitor
KR910007373A (en) Active filter automatic adjustment circuit for video signal processing
KR900701118A (en) Automatic Switching Circuit
KR910013877A (en) Character generator
KR960028240A (en) TV's mode control unit with PC mode
KR100407961B1 (en) Apparatus for processing input signal of a display device
KR920020484A (en) Recording state display circuit of VRF
KR930015358A (en) PLL circuit
KR100192052B1 (en) Device for stabilizing synchronous signal
KR950027439A (en) Wide Vision Driving Circuit by Sampling Clock Modulation
KR910020526A (en) Vision automatic adjustment circuit
KR920002121Y1 (en) Video signal same period stabilizing circuit
KR950007469A (en) Image stabilization device
KR950010507A (en) Horizontal frequency automatic regulation circuit
KR910008621Y1 (en) Melody generating circuit
KR960028251A (en) Input signal selection circuit of the monitor
KR950033786A (en) Monitor horizontal sync signal processing circuit
KR920005652A (en) Selective noise reduction device for Y signal in video signal processing device
KR950025637A (en) Contrast control device when recording VCR
KR20000010419A (en) Power operation motive signal managing device of multisync monitor and a method thereof
KR970071437A (en) L. Mr. Screen-centric implementations of LCD monitors
KR930020946A (en) Keystone Correction Circuit of Monitor
KR970056812A (en) Multi-adaptive horizontal size automatic conversion circuit of video display device

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20011128

Year of fee payment: 5

LAPS Lapse due to unpaid annual fee