JPWO2012132273A1 - Appearance inspection method and apparatus - Google Patents

Abstract

Imaging obtained as a pre-scan process using a low-power lens of an appearance inspection apparatus in order to hold the relationship between the stage coordinates on the stage of the appearance inspection apparatus and the formed object address of the formation of the object to be inspected Using the image, the formation address is assigned in association with the stage coordinates. During the actual inspection process, the formation address is used to reduce the search time for the object to be inspected, and the inspection tact is the sum of the inspection preparation process and the actual inspection. Reduce time.

Description

  The present invention relates to an appearance inspection method and apparatus for a formed object in which a fine pattern is formed on an object to be inspected. In particular, when a wafer (for example, a semiconductor wafer or LED wafer) is diced and then divided into a large number of chips in an expanding process, the arrangement and rotation angle of the formation on the semiconductor chip, which is the object to be inspected, is uniform. The present invention relates to a visual inspection method and apparatus that can be performed at a high speed even when there is no screen.

  Recently, in the appearance inspection method and / or apparatus for the formed object on the inspection object, each minute pattern is condensed on the formation on the inspection object on which the predetermined pattern is formed. There are many that are arranged in. In addition, in the appearance inspection of the object to be inspected, there is a need to perform an appearance inspection after stretching the wafer sheet that becomes the base of the predetermined shape object in the expanding process after dicing and separating the individual shape objects. Has increased.

  Furthermore, recently, the individual sizes of the shaped objects have become increasingly smaller, and 20,000 to 100,000 objects are arranged on one object to be inspected. Therefore, the inspection time is also increased, and the tact time of the appearance inspection is increasing.

  By the way, with respect to known techniques related to the present application, Patent Document 1 describes an invention relating to an appearance inspection process in which an inner surface inclination angle of an object to be inspected is obtained and rotation correction is performed in accordance with the angle.

  Further, in Patent Document 2, the pixel of interest in the reference image and the image to be inspected having the smaller spatial change in the neighboring pixel value is selected as the allowable pixel and the other is selected as the target pixel, and the allowable pixel A range is set. An arbitrary value within the allowable range is regarded as the value of the allowable pixel, and the target pixel and the allowable pixel are compared to calculate a difference value between these pixels. An invention relating to the creation of a difference map indicating the difference between the image to be inspected and the reference image based on the difference value is described.

  Furthermore, Patent Document 3 describes the following invention. An appearance inspection is performed to detect defects in a large number of inspection objects formed as a collection of inspection objects. At that time, it is necessary to inspect as many times as the number of illuminations, the angle, and other imaging magnifications change in accordance with the inspection recipe conditions. The amount by which the angle of each object to be inspected deviates from the reference horizontal angle is stored as correction data. In repeated inspections from the next time, the stored information is called and corrected for appearance inspection. Therefore, the appearance inspection time is shortened by avoiding the measurement work of the position and rotation angle in each case.

JP 2004-0669645 A JP 2003-057019 A JP2011-012971A

  As described in the background art, a large number of shape objects on the object to be inspected are separated after being subjected to an expanding process after dicing, and then the appearance inspection of all the shape objects is performed with only a large number of shape objects. There is a problem that the inspection process is completed without being overlooked by overlooking the shape object, and a workaround for the problem is desired.

In order to achieve such an object, the present invention has the following configuration.
That is, the invention according to the present invention uses a captured image obtained by capturing an object to be inspected held in a sheet that has undergone an expanding process after dicing processing having a shaped object placed on a stage in an imaging process. A method for inspecting the appearance of the inspection object,
A binarization process is performed on a captured image obtained by imaging the object to be inspected based on a threshold value set in advance for each shape object, and positions of individual shape objects extracted based on the result are determined in advance on the stage. A stage coordinate setting process for setting corresponding to the stage coordinates,
In consideration of the elongation percentage of the sheet in the expanding step between the shaped objects, other range using the stage coordinates of the predetermined shaped object for the other shaped object range that should be next to the predetermined shaped object Search process to search for shape objects,
A step of assigning a shape object address to another shape object with respect to another shape object found in the search process, and associating the shape object address with stage coordinates for each shape object; Prepared,
After the step of associating the stage coordinates of the shaped object with the shaped object address, an actual inspection is performed based on the shaped object address.

In the above method, the object to be inspected is a semiconductor wafer, and the shape object is a semiconductor chip.
The stage coordinates of the shaped object are obtained by performing binarization processing of the captured image, obtaining the barycentric coordinates of the semiconductor chip extracted from the binary image,
It is preferable to set the coordinates shifted by a relative distance from the center of gravity coordinates to a predetermined corner of the semiconductor chip.

  Further, in the above method, the shape object address is obtained by sequentially searching for shape objects in four directions from the set reference shape object using the stage coordinates, and the stage coordinates and the shape object address of the entire area to be inspected. Repeat the process of setting and associating.

  Further, in the above method, before the stage coordinate setting step, two semiconductor chips serving as a reference separated on a preset semiconductor wafer are searched and individually imaged, and the position coordinates of the semiconductor chip are detected. It is preferable to provide a main alignment step of obtaining the inclination of the semiconductor wafer from the above and aligning the semiconductor wafer according to the result. .

  Furthermore, in the above method, before the main alignment step, after binarizing the plurality of captured images of the semiconductor wafer imaged at a lower magnification than in the main alignment, the continuous alignment is performed based on the binary image. It is preferable to provide a sub-alignment step of obtaining the inclination of the semiconductor wafer from the alignment state of the plurality of semiconductor chips and aligning the semiconductor wafer based on the result.

Moreover, in order to achieve such an object, the present invention adopts the following configuration.
Inspecting the object to be inspected using a picked-up image obtained by picking up the object to be inspected held on a sheet that has undergone an expanding process after dicing processing having a shape object placed on the stage using an image pickup means An appearance inspection device,
A binarization process is performed on a captured image obtained by imaging the object to be inspected based on a threshold value set in advance for each shape object, and positions of individual shape objects extracted based on the result are determined in advance on the stage. Stage coordinate setting means for setting corresponding to the stage coordinates,
In consideration of the elongation percentage of the sheet in the expanding step between the shaped objects, other range using the stage coordinates of the predetermined shaped object for the other shaped object range that should be next to the predetermined shaped object A shape object is searched, and other shape objects found in the search process are given a shape object address to another shape object based on a predetermined shape object, and the shape object address and stage coordinates are assigned to each shape object. And means for associating with
An actual inspection is performed based on the shape object address after the association between the stage coordinates of the shape object and the shape object address.

  According to the said structure, the said 1st method invention can be implemented suitably.

  In the present invention, after the dicing process, in particular, as a stage before actual inspection of a large number of objects (for example, semiconductor chips) on an object to be inspected (for example, a wafer) that has undergone an expanding process, a captured image with a low-power lens is obtained. The position and presence of all the semiconductor chips that are a large number of shapes are grasped in advance by measuring the approximate position of the object to be inspected in advance. According to the present invention, it is possible to avoid oversight at the time of an actual inspection of a shape object in imaging using a high magnification lens due to a positional deviation associated with the stretching of a wafer sheet during an expanding process, and Enables actual inspection without oversight of shapes. In addition, it is possible to determine the position where the shape object on the inspection object is absent.

  In addition, according to the present invention, after inspecting a semiconductor chip on a wafer that has undergone an expanding process after dicing, the semiconductor chip that is an inspection object at a distant position in the wafer due to the expansion of the wafer itself Can be overlooked.

  In the post-inspection actual inspection process, the inspection tact is slowed by expanding the search range of the object to be inspected to the entire area, but the position of each semiconductor chip is preliminarily determined in advance in the prescan process described in the present invention. This makes it possible to narrow the search range of the object to be inspected and shorten the inspection tact. It is also effective in preventing overlooked shapes. In the prescan process, a wide range of images can be captured by using a low-magnification lens. Therefore, an increase in tact time due to the execution of the prescan process can be achieved by narrowing the search range of the object to be inspected. It is suppressed.

  The cause of the tact time reduction is that, when the pre-scan process of the present invention is performed during wafer inspection, the chip addresses corresponding to the stage coordinates are set in advance for all semiconductor chips on the wafer. The stage coordinate corresponding to the actual position of the semiconductor chip is obtained from the chip address of the corresponding semiconductor chip registered, the stage moving distance when positioning is shortened, and all semiconductor chips can be searched in a short time, The effect that the inspection time can be shortened in total is obtained.

BRIEF DESCRIPTION OF THE DRAWINGS The external appearance inspection apparatus whole structure schematic diagram explaining embodiment of this invention. The figure explaining extraction of the correction angle used as the standard of the inspection subject of the present invention. The figure explaining the to-be-inspected target object and shaped object of this invention. The flowchart which shows the flow of the external appearance inspection preparation process as described in Example 1 of this invention. The figure explaining the imaging visual field of the external appearance inspection apparatus of this invention. The figure explaining the binarization of the to-be-inspected object of this invention, a gravity center measurement, and a stage coordinate setting process. The figure explaining assignment of a chip address from the stage coordinates of a semiconductor chip in a test subject of the present invention. The flowchart which shows the flow of the external appearance inspection preparation process as described in Example 2 of this invention.

1 Object to be inspected 10 Reference line 11 Shaped object (semiconductor chip)
12 Wafer 13 Wafer Sheet 15 Reference Chip 16 Pad (Electrode)
151 NO. 1 chip 152 NO. 2-chip 122 shape object address (chip address)
2 Computer 21 Pattern Extraction Unit 22 Correction Amount Calculation Unit 23 Position Correction / Rotation Correction Unit 24 Appearance Inspection Data Processing Unit 5 Appearance Inspection Device 51 Frame 52 Stage 521 Stage Coordinates 52X X Direction Relative Distance 52 Y Y Direction Relative Distance 53 Objective Lens 54 Imaging Device 55 Imaging field of view 56 Captured image 57 Wide-range imaging field of view 58 Base 6 Correction angle

  Embodiments of the present invention will be described below with reference to the drawings.

[Appearance inspection equipment]
FIG. 1 is an overall schematic diagram of an apparatus for explaining an embodiment of the present invention. The appearance inspection apparatus 5 includes a stage 52 on a base 58. A shaped object (hereinafter, described as a semiconductor chip 11 as a specific example) formed on the wafer 12 corresponding to the inspection object 1 (hereinafter, described as a specific example as a wafer 12) is placed on the stage 52. Then, the objective lens 53 is used to capture an image, and the imaging device 54 installed on the frame 51 is used to capture an image. The captured image data is sent to a computer 2 having an arithmetic processing function coupled by a cable, and stored as information of individual semiconductor chips 11 on the wafer 12. The computer 2 includes an extraction unit 21, a correction amount calculation unit 22, a position correction / rotation correction unit 23, and an appearance inspection data processing unit 24. The appearance inspection data processing unit 24 of the computer 2 also includes the above-described captured image data. And sent to a DB data file 25 as a storage unit. Here, the computer 2 functions as stage coordinate setting means and means for associating the stage coordinates with the shape object address of the present invention.

[Wafer 12]
Next, the wafer 12 will be described. In order to give concreteness, an example is used. For example, with respect to the wafer 12 shown in FIG. 3A, a schematic diagram of the semiconductor chip 11 in a state in which the wafer 12 held through the wafer sheet that has undergone the dicing process is extended by an expanding process to facilitate handling is shown in FIG. Shown in (b).

[Start of appearance inspection preparation process]
Next, with respect to the appearance inspection apparatus 5 and the wafer 12, a series of appearance inspection preparation steps will be described using the flowchart of FIG.

[Preparation process 1]
First, the wafer 12 after dicing shown in FIG. 3A is subjected to an expanding process, and then placed on the stage 52 of the appearance inspection apparatus 5.

[Preparation process 2]
First, as described later, alignment is performed as positioning of the wafer 12 on the stage 52. That is, when the wafer 12 having the form shown in FIG. 3A is placed on the stage 52 of the appearance inspection apparatus 5, as shown in FIG. As in a normal microscope, an image of a circular imaging field of view 55 is obtained.

  However, as illustrated in FIG. 2, the captured image 56 when captured as electronic data using the imaging device 54 is rectangular. When the captured images 56 are sequentially captured, the stage 52 is moved while the captured images 56 on the stage 52 of the appearance inspection apparatus 5 are acquired, and the imaging is repeated. For example, imaging from the upper first stage leftmost semiconductor chip 11 in FIG. 3A is started, and then imaging is repeated in the right lateral direction and repeated. Note that the magnification of the captured image 56 is approximately the same as the magnification of the captured image 56 that is used again in the actual inspection process, which will be described later, using a captured image magnification corresponding to a range narrower than the captured image magnification at the time of prescan imaging, which will be described later. To do.

  Next, when imaging of the first row is completed, an image of the semiconductor chip 11 to be inspected sequentially in the left lateral direction is taken down by one step. As described above, when the stage 52 is moved and the captured image 56 of the semiconductor chip 11 is acquired, while the stage 52 moves from the left end to the right end of the array of the semiconductor chips 11 arranged, the wafer 12 It is necessary to position the wafer 12 at a substantially correct position so that an image obtained by the imaging device 54 of the upper semiconductor chip 11 is within the imaging visual field 55 of the imaging device 54.

[Preparation process 3]
A global alignment method is used as a method of positioning the wafer 12 at a substantially correct position. The global alignment corresponds to the main alignment process of the present invention.

  That is, two semiconductor chips 11 serving as a reference used for global alignment are determined by a recipe created before the appearance inspection preparation process.

  As shown in FIG. 2, the two semiconductor chips 11 are either in the center of the same row of the semiconductor chips 11 arranged on the wafer 12 on the stage 52 and the captured image 56 on the rightmost row in the same row, or in the vertical direction (not shown). The semiconductor chip 11 is set as far as possible in the same row or column, such as the captured image 56 at the center and the bottom.

  Based on the recipe, the semiconductor chip 11 serving as a reference is divided for each region, and the imaging device 54 is set to a high magnification and images are taken. The extraction unit 21 extracts the semiconductor chip 11 (NO.1 chip 151, NO.2 chip 152) serving as a reference by pattern matching between the captured image and the reference image. No. in the acquired image. 1 chip 151, NO. When the two chips 152 are not found, an image of the neighboring area is acquired, and both semiconductor chips 11 are extracted by repeating the trial and error.

  The NO. 1 chip 151, NO. Appearance so that the captured image 56 obtained by the imaging device 54 moves within the frame of the imaging visual field 55 when the stage 52 is moved in the row direction while imaging is performed in the row direction using the two chips 152. The global alignment is performed in order to adjust the mounting position of the wafer 12 on the stage 52 of the inspection apparatus 5 by rotating the stage 52. Specifically, as shown in FIG. 2, the global alignment method includes two selected NO. 1 chip 151, NO. A specific point in a common pattern of the semiconductor chips 11 of the two chips 152 is registered, a search is performed by image processing to find the reference line 10, and based on the positional relationship between the two semiconductor chips 11. The correction amount calculation unit 22 calculates the correction angle 6 and the stage 52 is operated by the position correction / rotation correction unit 23 based on the correction angle to correct the angle of the wafer 12.

[Preparation process 4] (Start of pre-scan process)
Next, the objective lens 53 is adjusted to a lens having a lower magnification than that at the time of global alignment, and the imaging of the wide range imaging visual field 57 after the expanding process of the wafer 12 is started. It is sent to the DB data file 25 through the appearance inspection data processing 24 and stored. Since the wafer 12 has already undergone the expanding process, in order to image all the semiconductor chips 11 on the wafer 12, the wafer 12 in the expanding process is taken into account in a wider range than the wafer 12 before the expanding process in consideration of the elongation of the wafer sheet. The wide-range imaging visual field 57 is imaged in consideration of the extended range of the possibility that the semiconductor chip 11 exists.

  Actually, the wide imaging field 57 using the low-magnification objective lens 53 is wide, but the wide imaging field 57 of the entire wafer 12 cannot be partitioned by one image, so that the entire wafer 12 is covered. The stage 52 is moved, and a plurality of picked-up images 56 are picked up repeatedly by the image pickup device 54 and sent to the DB data file 25 through the appearance inspection data processing 24 of the computer 2 and stored therein.

  For example, when the expansion rate of the wafer sheet in one direction of the expansion process set in advance is set to a minimum of 0.8 to a maximum of 1.4, in order to cover the maximum area of the entire wafer 12, When the size is 3 inches, the semiconductor chip 11 may exist in a range expanded 1.4 times at the maximum in order to prevent the semiconductor chip 11 from being overlooked. It is necessary to perform imaging as a process. Further, the elongation rate of the wafer sheet in the expanding process is very small because the dimension of the semiconductor chip 11 during dicing is smaller than the dimension of the wafer 12 before processing when the expanding process after dicing is performed. In such a case, since the distance between the semiconductor chips may be smaller than the original dimension of the wafer 12, even after the expanding process, the elongation percentage of the wafer sheet may be smaller than 1.0.

[Preparation process 5] (binarization process)
After all the images on the wafer 12 have been captured, the extraction unit 21 divides each captured image 56 into previously set luminance values (0 to 255 levels) for binarization, and is also set in advance. The threshold value of the image is used to divide the luminance value of the image into regions having luminance values that are equal to or higher than the threshold value and extract necessary portions of each region.

  When binarization processing is performed with the set threshold value, the semiconductor chip 11 on the wafer 12 is mostly gray. The gray color portion is a black area, and the area that needs to recognize the stage coordinates 521 of the semiconductor chip 11 is basically a white background portion. If only the white background obtained by binarization is recognized and extracted, it is possible to grasp the stage coordinates 521 at a location necessary for the actual inspection described later.

  Specifically, when the image of the wafer 12 is binarized, a portion with a luminance value of 0 becomes “black”, and a “gray” portion between “black” and “white” indicates the individual luminance of the corresponding portion. The luminance value after the stage is set, and finally the portion of the luminance value 255 becomes “white”. Generally, the part used for the actual inspection of the semiconductor chip 11 is a pad (electrode) 16 part, and the normal color is close to white. As shown in FIG. 6, a pad (electrode) 16 portion which is a white portion is extracted in the binarization process.

  The brightness value of the selection criterion depends on the wafer 12 that is actually used, and is set by the operator. The binarization operation is performed on all captured images 56 that have been captured. Using the individual images of the picked-up images 56 obtained by dividing the wafer 12 through the expanding process, the size of the extracted portion is expressed in units of pixels (= unit constituting a digital image [pixel] handled by a computer). ) Is obtained by converting the number of pixels measured in (1) into “area”. Specifically, the area of the pad (electrode) 16 portion which is an individual white portion extracted in the binarization step is obtained. A range of the maximum and minimum areas is set in advance for the area, and an area within the range is set as an actual inspection target. The reason why the image of the set area range is extracted is that data exceeding the range can be empirically regarded as dust that does not correspond to the pads (electrodes) 16 of the semiconductor chip 11 and other images unnecessary for actual inspection. is there.

[Preparation process 6]
The following steps are performed by the appearance inspection data processing unit 24. As shown in FIG. 6, when the pads (electrodes) 16 of the semiconductor chip, which is the actual inspection object extracted in the step, exist as a pair, each pair is detected, and two locations in the area unit for each pair. The center of gravity of each pair is measured by combining the pads (electrodes) 16 and set as the center of gravity coordinates as a pair.

  The stage coordinate 521 of each semiconductor chip 11 is set to a position shifted by the relative distance by the X-direction relative distance 52X and the Y-direction relative distance 52Y, which are set in advance based on the measured barycentric coordinates. The relative distance in this embodiment is the distance between the corner coordinates determined in advance from the outer shape of the semiconductor chip 11 and the calculated center of gravity.

  Accordingly, the coordinates obtained by shifting the relative distances in the X direction and the Y direction by the X direction relative distance 52X and the Y direction relative distance 52Y set in advance with respect to the measured barycentric coordinates are the stage coordinates of each semiconductor chip 11. In the same manner, the stage coordinates 521 for all the semiconductor chips 11 on the wafer 12 to be measured are set.

[Preparation process 7]
Among the stage coordinates 521 of all the semiconductor chips 11, NO. Is selected for rotationally correcting the wafer 12 obtained in the global alignment process, and the stage coordinates 521 and the chip address 122 are preset. One chip 151 is set as the reference chip 15, and the address of the stage coordinates 521 (X, Y) of the reference chip 15 is determined and assigned as the reference chip address 122.

[Preparation process 8]
A procedure for finding all the semiconductor chips 11 on the wafer 12 which is the gist of the present application will be described. As shown in FIG. 7A, the NO. One chip 151 is set as the reference chip 15 and the chip address 122 of the reference chip 15 is set to (m, n). Next, as shown in FIG. 7B, the stage coordinates of the peripheral semiconductor chips 11 in the desired range are determined for the semiconductor chips 11 around the reference chip 15 in consideration of the expansion rate of the wafer sheet. Explore. When the stage coordinates of the reference chip 15 are (X, Y) and the chip address 122 is (m, n), the chip address 122 corresponding to the stage coordinates 521 of the semiconductor chip in the four directions around the reference chip 15 is the reference address. The upper neighbor of the chip 15 is (m, [n-1]), the left neighbor is ([m-1], n), the right neighbor is ([m + 1], n), and the lower neighbor is (m, [n + 1]). Set to Thereby, the stage coordinates 521 and the chip address 122 of each semiconductor chip 11 in the surrounding four directions can be associated with each other.

  Further, as shown in FIG. 7C, the semiconductor chip 11 in the three directions is further searched based on the semiconductor chip 11 in which the peripheral four-direction chip address 122 and the stage coordinates 521 set in FIG. Then, the stage coordinates 521 of the new semiconductor chip 11 and the chip address 122 are obtained and associated. This operation is repeated, and the chip address 122 of the semiconductor chip 11 on the entire wafer 12 and the stage coordinates 521 are obtained and associated. Similarly, the semiconductor chip 11 associated with the other chip address 122 and the stage coordinates 521 is repeated until the search of the entire area of the wafer 12 is completed. Thereby, the association between the stage coordinates 521 and the chip address 122 can be determined for the semiconductor chips 11 on all the wafers 12, and all of the information is stored in the DB file 25 through the appearance inspection data processing unit 24 of the computer 2. The

[End of visual inspection preparation process]
As described above, the stage coordinates 521 and the corresponding chip address 122 are associated with all the semiconductor chips 11 on the wafer 12, and the actual inspection process is started. Here, in the actual inspection process, the chip address 122 is determined for all the target semiconductor chips 11. Where the target semiconductor chip 11 is located is because the stage coordinates 521 and the chip address 122 are associated with each other in the pre-scanning step, the stage 52 of the appearance inspection apparatus 5 is changed to the semiconductor chip 11 to be actually inspected. By moving in the order of the corresponding addresses and aligning with the stage coordinates 521 corresponding to the addresses, the actual inspection can be performed efficiently at high speed and without inspection leakage. The above is the description of the pre-scan process of the present invention based on FIG.

Comparative example

  Actual results of time reduction when pre-scanning is actually performed as an appearance inspection preparation process of the inspection object 1 will be described.

The difference in tact time when a wafer 12 having an outer diameter of 4 inches that has undergone an expanding process after dicing is subjected to a pre-scan process based on the conventional method and the present invention will be described. Here, the conventional method is a case where an actual inspection is performed after the global alignment is performed.
When inspection was performed by the conventional method: 7 minutes 34 seconds.
When the pre-scan according to the present invention was performed, it was 1 minute 49 seconds (pre-scan time: 9 seconds, actual inspection time: 1 minute 40 seconds).

  Thereby, in the case of the inspection time of the wafer 12 using the pre-scan process according to the present invention, an effect of shortening 5 minutes 45 seconds is obtained. The factor of shortening the tact time is that when the wafer 12 is inspected, when the pre-scan process of the present invention is performed, the chip addresses 122 are already set for all the semiconductor chips 11 on the wafer 12, so that the actual inspection is performed. The search range when searching for the chip address 122 of the corresponding semiconductor chip 11 registered at the time is narrowed, the positions of all the corresponding semiconductor chips 11 can be reached in a short time, and the inspection time is shortened overall. An effect is obtained.

  In the present embodiment, using the apparatus of the first embodiment, [Preparation Step 2] and [Preparation Step 3] included in the global alignment step described in the flowchart of FIG. 4 are performed in the middle of the pre-scanning step. . Therefore, the description of the same processing steps will be simplified and different parts will be described in detail. In the following, description will be given along the flowchart shown in FIG.

[Preparation process]
First, the wafer 12 after dicing shown in FIG. 3A is subjected to an expanding process, and then placed on the stage 52 of the appearance inspection apparatus 5.

[Start prescan]
Next, the objective lens 53 is adjusted to a low-magnification lens, and the image of each wide area in the wide-range imaging visual field 57 after the expanding process of the wafer 12 is started while moving the stage 52, and the captured image 56 is converted into a computer. 2 is sent to the DB data file 25 through the appearance inspection data processing unit 24 and stored. Since the wafer 12 has already undergone the expanding process, in order to image all the semiconductor chips 11 on the wafer 12, the wafer 12 in the expanding process is taken into account in a wider range than the wafer 12 before the expanding process in consideration of the elongation of the wafer sheet. The wide-range imaging visual field 57 is imaged in consideration of the extended range of the possibility that the semiconductor chip 11 exists.

[Binarization processing]
After the imaging of all the images on the wafer 12 is completed, the extraction unit 21 divides the luminance value of the image into regions having luminance values equal to or higher than the threshold value and using the threshold value set in advance, the semiconductor chip 11 and the pad 16 is extracted.

[Calculation of barycentric coordinates]
As shown in FIG. 6, when the extracted semiconductor chip pads 16 exist as pairs, each pair is repeatedly detected for each semiconductor chip 11, and two pads 16 are combined for each pair in the area unit for each pair. Find the barycentric coordinates for each.

[Estimation of reference chip]
When the center of gravity of each semiconductor chip 11 is obtained, an image containing the largest number of semiconductor chips 11 is selected based on the number of center-of-gravity coordinates included in the acquired plurality of images. Here, for example, the correction amount calculation unit 22 compares the barycentric coordinates of the semiconductor chip 11 along one axis in either the vertical direction or the horizontal direction shown in FIG. Calculate the slope.

  The appearance inspection data processing unit 24 uses the outer shape of the semiconductor chip 11 and the inclination of the wafer included in all captured images obtained by the binarization process, and the NO. 1 chip 151 and NO. The position of the two chips 152 is estimated.

  NO. 1 chip 151 and NO. When the estimation of the two chips 152 is completed, the stage 52 is rotated by the calculated inclination, and the corrected NO. 1 chip 151 and NO. The barycentric coordinates of the two chips 152 are calculated. The above process corresponds to the sub-alignment process of the present invention.

[Global alignment]
The magnification of the objective lens 53 is increased as compared with the prescan. Estimated NO. 1 chip 151 and NO. The stage 52 is moved so that each of the center-of-gravity coordinates of the two chips 152 falls within the imaging field of view. The wafer 12 is imaged at each position. Thereafter, as shown in FIG. 2, the reference line 10 is set to the two images acquired by the correction amount calculation unit 22, and NO. 1 chip 151 and NO. The correction angle 6 is calculated from the positional relationship between the two chips 152. Based on the correction angle, the position correction / rotation correction unit 23 rotates the stage 52 to correct the angle of the wafer 12.

[Correction of barycentric coordinates]
The center-of-gravity coordinates are corrected according to the amount of rotation for all the semiconductor chips 11 on the wafer 12 whose rotation is corrected by the global alignment.

[Calculation of stage coordinates]
The following processing is performed by the appearance inspection data processing unit 24. The stage coordinates 521 of each semiconductor chip 11 are set based on the corrected center-of-gravity coordinates, which are set in advance by shifting the relative distance by the X-direction relative distance 52X and the Y-direction relative distance 52Y. Similar to the first embodiment, the relative distance is the distance between the corner coordinates determined in advance from the outer shape of the semiconductor chip 11 and the calculated center of gravity.

[Address setting for reference chip (No. 1 chip)]
NO. After rotation correction by global alignment The stage coordinates of one chip 151 are extracted and an address is set. That is, NO. One chip 151 is set as the reference chip 15, and the address of the stage coordinates 521 (X, Y) of the reference chip 15 is determined as the reference chip address 122 and assigned.

[Address assignment to semiconductor chip]
As in the first embodiment, an address is assigned to each semiconductor chip 11 as follows. As shown in FIG. 7A, the NO. One chip 151 is set as the reference chip 15 and the chip address 122 of the reference chip 15 is set to (m, n). Next, as shown in FIG. 7B, the stage coordinates of the peripheral semiconductor chips 11 in the desired range are determined for the semiconductor chips 11 around the reference chip 15 in consideration of the expansion rate of the wafer sheet. Explore. When the stage coordinates of the reference chip 15 are (X, Y) and the chip address 122 is (m, n), the chip address 122 corresponding to the stage coordinates 521 of the semiconductor chip in the four directions around the reference chip 15 is the reference address. The upper neighbor of the chip 15 is (m, [n-1]), the left neighbor is ([m-1], n), the right neighbor is ([m + 1], n), and the lower neighbor is (m, [n + 1]). Set to Thereby, the stage coordinates 521 and the chip address 122 of each semiconductor chip 11 in the surrounding four directions can be associated with each other.

  Further, as shown in FIG. 7C, the semiconductor chip 11 in the three directions is further searched based on the semiconductor chip 11 in which the peripheral four-direction chip address 122 and the stage coordinates 521 set in FIG. Then, the stage coordinates 521 of the new semiconductor chip 11 and the chip address 122 are obtained and associated. Repeat the operation.

[Determination of unset address]
When the semiconductor chip 11 is searched in a certain direction and the assignment of the chip address 122 is completed, it is determined whether there is a stage coordinate to which no address is assigned. If there are no stage coordinates without address assignment, the appearance inspection reference process is terminated. If there are stage coordinates without address assignment, address assignment is performed.

[Address estimation allocation]
When another semiconductor chip 11 adjacent to the semiconductor chip 11 serving as the base axis exists beyond a predetermined distance, a search error occurs, and no chip address is assigned to the other semiconductor chip 11. Therefore, for example, the chip addresses of other semiconductor chips 11 are estimated and assigned as follows. The semiconductor chip 11 that has been registered with an address at the closest position to another semiconductor chip 11 for which no chip address is set (hereinafter referred to as “reference semiconductor chip 11”) is extracted. If the distance is the same, either one is selected. The distance between the stage coordinates of both semiconductor chips 11 and the direction in which another semiconductor chip 11 exists is obtained from the reference semiconductor chip 11. An approximate chip address that is not associated with the stage coordinates within a predetermined range of the direction and distance from the reference semiconductor chip 11 is estimated and assigned as the other chip address.

  Chip addresses are estimated and assigned to all unconfigured semiconductor chips 1. The chip address of the semiconductor chip 11 on the entire wafer 12 and the stage coordinates are obtained and correlated. When the association is confirmed, all the information is stored in the DB file 25 through the appearance inspection data processing unit 24 of the computer 2.

[End of visual inspection preparation process]
As described above, the stage coordinates 521 and the corresponding chip address 122 are associated with all the semiconductor chips 11 on the wafer 12, and the actual inspection process is started.

  According to this embodiment, all the semiconductor chips 11 on the wafer 12 are imaged in the wide imaging field 57 by pre-scanning, and the tilt of the wafer 12 is obtained from the alignment state of the semiconductor chips 11 in the captured image in the sub-alignment process. It is done. By correcting the inclination, the outer shape of the semiconductor chip 11 can be returned to an appropriate position. Therefore, a captured image including the reference chip 15 can be reliably acquired by one imaging based on the position information of the reference chip 15 set in the recipe. Therefore, as in the first embodiment, iterative processing by trial and error for obtaining the reference chip 15 that occurs when the global alignment is performed first is eliminated, and the tact time can be shortened.

  The present invention can also be implemented in the following forms.

  In both the above embodiments, the center of gravity of the semiconductor chip 11 is obtained by using the pads 16 of the two electrodes. However, the center of gravity can also be calculated by using the outer shape of the semiconductor chip 11 and the coordinates of its corners. .

  Moreover, in the said Example, although demonstrated taking the semiconductor wafer 12 as an example, it is not limited to the said embodiment, For example, it can apply also to the wafer of LED.

  When inspecting a picked-up image appearing on a shape object of various objects to be inspected and performing an inspection using an appearance inspection apparatus that detects defects in the shape object, as a recent trend, various objects to be inspected, that is, main wafers are After the dicing process and the expanding process, there is an increasing demand for inspection of the shape in the wafer, that is, mainly the semiconductor chip.

  In recent years, the inspection time for each wafer has increased due to the increase in the outer diameter of the wafer, the increase in the number of semiconductor chips in the wafer, and further miniaturization and densification. It is desired to shorten this. In addition, there is an increasing number of cases where it is desired to inspect a wafer after it has already undergone dicing and an expanding process. Accordingly, shortening the tact time for wafer inspection in the above situation is urgent, and the utility value as a method for reducing the tact time for wafer inspection by using the pre-scan function proposed in the present invention is high.

Claims (6)

Method for inspecting appearance of object to be inspected using picked-up image obtained by picking up image of object to be inspected held in sheet after expanded process after dicing process having shape object placed on stage Because
A binarization process is performed on a captured image obtained by imaging the object to be inspected based on a threshold value set in advance for each shape object, and positions of individual shape objects extracted based on the result are determined in advance on the stage. A stage coordinate setting process for setting corresponding to the stage coordinates,
In consideration of the elongation percentage of the sheet in the expanding step between the shaped objects, other range using the stage coordinates of the predetermined shaped object for the other shaped object range that should be next to the predetermined shaped object Search process to search for shape objects,
A step of assigning a shape object address to another shape object with respect to another shape object found in the search process, and associating the shape object address with stage coordinates for each shape object; Prepared,
An appearance inspection method comprising: performing an actual inspection based on the shape object address after the step of associating the stage coordinates of the shape object with the shape object address. The inspection object is a semiconductor wafer, and the shape object is a semiconductor chip,
The stage coordinates of the shaped object are obtained by performing binarization processing of the captured image, obtaining the barycentric coordinates of the semiconductor chip extracted from the binary image,
The appearance inspection method according to claim 1, wherein the coordinates are set to be shifted by a relative distance from the center-of-gravity coordinates to a predetermined corner of the semiconductor chip.   The shape object address is a process of sequentially searching for shape objects in four directions from the set reference shape object using the stage coordinates, and setting and associating the stage coordinates and the shape object address of the entire inspection object. 3. An appearance inspection method according to claim 1, wherein the appearance inspection method is obtained repeatedly.   Before the stage coordinate setting step, two reference semiconductor chips separated on a preset semiconductor wafer are searched and individually imaged, and the inclination of the semiconductor wafer is obtained from the position coordinates of the semiconductor chip. 4. The appearance inspection method according to claim 2, further comprising a main alignment step of aligning the semiconductor wafer according to the result.   Before the main alignment step, a plurality of captured images of a semiconductor wafer imaged at a lower magnification than that at the time of main alignment are binarized, and then a plurality of semiconductors arranged in succession based on the binary image. 5. The appearance inspection method according to claim 4, further comprising a sub-alignment step of obtaining an inclination of the semiconductor wafer from the chip alignment state and aligning the semiconductor wafer based on the result. Inspecting the object to be inspected using a picked-up image obtained by picking up the object to be inspected held on a sheet that has undergone an expanding process after dicing processing having a shape object placed on the stage using an image pickup means An appearance inspection device,
A binarization process is performed on a captured image obtained by imaging the object to be inspected based on a threshold value set in advance for each shape object, and positions of individual shape objects extracted based on the result are determined in advance on the stage. Stage coordinate setting means for setting corresponding to the stage coordinates,
In consideration of the elongation percentage of the sheet in the expanding step between the shaped objects, other range using the stage coordinates of the predetermined shaped object for the other shaped object range that should be next to the predetermined shaped object A shape object is searched, and other shape objects found in the search process are given a shape object address to another shape object based on a predetermined shape object, and the shape object address and stage coordinates are assigned to each shape object. And means for associating with
An appearance inspection apparatus that performs an actual inspection based on the shape object address after the association between the stage coordinates of the shape object and the shape object address.

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